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Kinson Chikfe931032011-07-21 10:01:34 -07001/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29#include <mdp4.h>
30#include <debug.h>
31#include <reg.h>
32#include <target/display.h>
33#include <platform/timer.h>
34#include <platform/iomap.h>
35
Ajay Dudanib01e5062011-12-03 23:23:42 -080036void
37mdp_setup_dma_p_video_config(unsigned short pack_pattern,
38 unsigned short img_width,
39 unsigned short img_height,
40 unsigned long input_img_addr,
41 unsigned short img_width_full_size,
42 unsigned char ystride)
43{
44 dprintf(SPEW, "MDP4.2 Setup for DSI Video Mode\n");
Kinson Chikfe931032011-07-21 10:01:34 -070045
Ajay Dudanib01e5062011-12-03 23:23:42 -080046 // ----- programming MDP_AXI_RDMASTER_CONFIG --------
47 /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
48 the only port connected */
49 //TODO: Seems to still work without this
50 writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
51 writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
52 writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
Kinson Chikfe931032011-07-21 10:01:34 -070053
Ajay Dudanib01e5062011-12-03 23:23:42 -080054 /* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */
55 writel(0x00000049, MDP_DISP_INTF_SEL);
Kinson Chikfe931032011-07-21 10:01:34 -070056
Ajay Dudanib01e5062011-12-03 23:23:42 -080057 /* DMA P */
58 writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
Kinson Chikfe931032011-07-21 10:01:34 -070059
Ajay Dudanib01e5062011-12-03 23:23:42 -080060 /* RGB 888 */
61 writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG);
Kinson Chikfe931032011-07-21 10:01:34 -070062
Ajay Dudanib01e5062011-12-03 23:23:42 -080063 writel(0x0, MDP_DMA_P_OUT_XY);
Kinson Chikfe931032011-07-21 10:01:34 -070064
Ajay Dudanib01e5062011-12-03 23:23:42 -080065 writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
Kinson Chikfe931032011-07-21 10:01:34 -070066
Ajay Dudanib01e5062011-12-03 23:23:42 -080067 writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
Kinson Chikfe931032011-07-21 10:01:34 -070068
Ajay Dudanib01e5062011-12-03 23:23:42 -080069 writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
Kinson Chikfe931032011-07-21 10:01:34 -070070}
71
Ajay Dudanib01e5062011-12-03 23:23:42 -080072int
73mdp_setup_dma_p_video_mode(unsigned short disp_width,
74 unsigned short disp_height,
75 unsigned short img_width,
76 unsigned short img_height,
77 unsigned short hsync_porch0_fp,
78 unsigned short hsync_porch0_bp,
79 unsigned short vsync_porch0_fp,
80 unsigned short vsync_porch0_bp,
81 unsigned short hsync_width,
82 unsigned short vsync_width,
83 unsigned long input_img_addr,
84 unsigned short img_width_full_size,
85 unsigned short pack_pattern, unsigned char ystride)
Kinson Chikfe931032011-07-21 10:01:34 -070086{
87
Ajay Dudanib01e5062011-12-03 23:23:42 -080088 // unsigned long mdp_intr_status;
89 int status = FAIL;
90 unsigned long hsync_period;
91 unsigned long vsync_period;
92 unsigned long vsync_period_intmd;
Kinson Chikfe931032011-07-21 10:01:34 -070093
Ajay Dudanib01e5062011-12-03 23:23:42 -080094 dprintf(SPEW, "MDP4.1 for DSI Video Mode\n");
Kinson Chikfe931032011-07-21 10:01:34 -070095
Ajay Dudanib01e5062011-12-03 23:23:42 -080096 hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1;
97 vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1;
98 vsync_period = vsync_period_intmd * hsync_period;
Kinson Chikfe931032011-07-21 10:01:34 -070099
Ajay Dudanib01e5062011-12-03 23:23:42 -0800100 // ----- programming MDP_AXI_RDMASTER_CONFIG --------
101 /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
102 the only port connected */
103 writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
104 writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
105 writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
106 /* sets PRIM_INTF_SEL to 0x1 and SEC_INTF_SEL to 0x2 and DSI_VIDEO_INTF_SEL */
107 writel(0x00000049, MDP_DISP_INTF_SEL);
108 writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
Kinson Chikfe931032011-07-21 10:01:34 -0700109
Ajay Dudanib01e5062011-12-03 23:23:42 -0800110 // ------------- programming MDP_DMA_P_CONFIG ---------------------
111 writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
Kinson Chikfe931032011-07-21 10:01:34 -0700112
Ajay Dudanib01e5062011-12-03 23:23:42 -0800113 writel(0x00000000, MDP_DMA_P_OUT_XY);
114 writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
115 writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
116 writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
117 writel(0x00ff0000, MDP_DMA_P_OP_MODE);
118 writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL);
119 writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
120 writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
121 writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp,
122 MDP_DSI_VIDEO_DISPLAY_HCTL);
123 writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
124 writel((img_height + vsync_porch0_bp) * hsync_period,
125 MDP_DSI_VIDEO_DISPLAY_V_END);
126 writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
127 writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
128 writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
129 // end of cmd mdp
Kinson Chikfe931032011-07-21 10:01:34 -0700130
Ajay Dudanib01e5062011-12-03 23:23:42 -0800131 writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
Kinson Chikfe931032011-07-21 10:01:34 -0700132
Ajay Dudanib01e5062011-12-03 23:23:42 -0800133 status = PASS;
134 return status;
Kinson Chikfe931032011-07-21 10:01:34 -0700135}
136
Ajay Dudanib01e5062011-12-03 23:23:42 -0800137int
138mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
139 unsigned short num_of_lanes)
Kinson Chikfe931032011-07-21 10:01:34 -0700140{
141
Ajay Dudanib01e5062011-12-03 23:23:42 -0800142 int status = 0;
143 unsigned long input_img_addr = MIPI_FB_ADDR;
144 unsigned short image_wd = mipi_fb_cfg.width;
145 unsigned short image_ht = mipi_fb_cfg.height;
146 unsigned short pack_pattern = 0x12;
147 unsigned char ystride = 3;
Kinson Chikfe931032011-07-21 10:01:34 -0700148
Ajay Dudanib01e5062011-12-03 23:23:42 -0800149 writel(0x03ffffff, MDP_INTR_ENABLE);
150 writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
Kinson Chikfe931032011-07-21 10:01:34 -0700151
Ajay Dudanib01e5062011-12-03 23:23:42 -0800152 // ------------- programming MDP_DMA_P_CONFIG ---------------------
153 writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
Kinson Chikfe931032011-07-21 10:01:34 -0700154
Ajay Dudanib01e5062011-12-03 23:23:42 -0800155 writel(0x00000000, MDP_DMA_P_OUT_XY);
156 writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE);
157 writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
Kinson Chikfe931032011-07-21 10:01:34 -0700158
Ajay Dudanib01e5062011-12-03 23:23:42 -0800159 writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE);
Kinson Chikfe931032011-07-21 10:01:34 -0700160
Ajay Dudanib01e5062011-12-03 23:23:42 -0800161 writel(0x00000000, MDP_DMA_P_OP_MODE);
Kinson Chikfe931032011-07-21 10:01:34 -0700162
Ajay Dudanib01e5062011-12-03 23:23:42 -0800163 writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
164 writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN);
Kinson Chikfe931032011-07-21 10:01:34 -0700165
Ajay Dudanib01e5062011-12-03 23:23:42 -0800166 writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG);
167 writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
168 writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
169 writel(0x8a, MDP_DISP_INTF_SEL);
Kinson Chikfe931032011-07-21 10:01:34 -0700170
Ajay Dudanib01e5062011-12-03 23:23:42 -0800171 return status;
Kinson Chikfe931032011-07-21 10:01:34 -0700172}
173
174void mdp_disable(void)
175{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800176 writel(0x00000000, MDP_DSI_VIDEO_EN);
Kinson Chikfe931032011-07-21 10:01:34 -0700177}
178
179void mdp_shutdown(void)
180{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800181 mdp_disable();
182 mdelay(60);
183 writel(0x00000000, MDP_INTR_ENABLE);
184 writel(0x00000003, MDP_OVERLAYPROC0_CFG);
Kinson Chikfe931032011-07-21 10:01:34 -0700185}
186
187void mdp_start_dma(void)
188{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800189 writel(0x00000001, MDP_DMA_P_START);
Kinson Chikfe931032011-07-21 10:01:34 -0700190}