anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define usb30_pipe_source_val 2 |
| 43 | |
| 44 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 45 | |
| 46 | |
| 47 | /* Clock Operations */ |
| 48 | static struct clk_ops clk_ops_reset = |
| 49 | { |
| 50 | .reset = clock_lib2_reset_clk_reset, |
| 51 | }; |
| 52 | |
| 53 | static struct clk_ops clk_ops_branch = |
| 54 | { |
| 55 | .enable = clock_lib2_branch_clk_enable, |
| 56 | .disable = clock_lib2_branch_clk_disable, |
| 57 | .set_rate = clock_lib2_branch_set_rate, |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 58 | .reset = clock_lib2_branch_clk_reset, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
| 61 | static struct clk_ops clk_ops_rcg_mnd = |
| 62 | { |
| 63 | .enable = clock_lib2_rcg_enable, |
| 64 | .set_rate = clock_lib2_rcg_set_rate, |
| 65 | }; |
| 66 | |
| 67 | static struct clk_ops clk_ops_rcg = |
| 68 | { |
| 69 | .enable = clock_lib2_rcg_enable, |
| 70 | .set_rate = clock_lib2_rcg_set_rate, |
| 71 | }; |
| 72 | |
| 73 | static struct clk_ops clk_ops_cxo = |
| 74 | { |
| 75 | .enable = cxo_clk_enable, |
| 76 | .disable = cxo_clk_disable, |
| 77 | }; |
| 78 | |
| 79 | static struct clk_ops clk_ops_pll_vote = |
| 80 | { |
| 81 | .enable = pll_vote_clk_enable, |
| 82 | .disable = pll_vote_clk_disable, |
| 83 | .auto_off = pll_vote_clk_disable, |
| 84 | .is_enabled = pll_vote_clk_is_enabled, |
| 85 | }; |
| 86 | |
| 87 | static struct clk_ops clk_ops_vote = |
| 88 | { |
| 89 | .enable = clock_lib2_vote_clk_enable, |
| 90 | .disable = clock_lib2_vote_clk_disable, |
| 91 | }; |
| 92 | |
| 93 | /* Clock Sources */ |
| 94 | static struct fixed_clk cxo_clk_src = |
| 95 | { |
| 96 | .c = { |
| 97 | .rate = 19200000, |
| 98 | .dbg_name = "cxo_clk_src", |
| 99 | .ops = &clk_ops_cxo, |
| 100 | }, |
| 101 | }; |
| 102 | |
| 103 | static struct pll_vote_clk gpll0_clk_src = |
| 104 | { |
| 105 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 106 | .en_mask = BIT(0), |
| 107 | .status_reg = (void *) GPLL0_STATUS, |
| 108 | .status_mask = BIT(30), |
| 109 | .parent = &cxo_clk_src.c, |
| 110 | |
| 111 | .c = { |
| 112 | .rate = 800000000, |
| 113 | .dbg_name = "gpll0_clk_src", |
| 114 | .ops = &clk_ops_pll_vote, |
| 115 | }, |
| 116 | }; |
| 117 | |
| 118 | /* SDCC Clocks */ |
| 119 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = |
| 120 | { |
| 121 | F( 144000, cxo, 16, 3, 25), |
| 122 | F( 400000, cxo, 12, 1, 4), |
Joonwoo Park | 095007a | 2014-06-27 17:57:45 -0700 | [diff] [blame] | 123 | F( 20000000, gpll0, 15, 1, 2), |
| 124 | F( 25000000, gpll0, 12, 1, 2), |
| 125 | F( 50000000, gpll0, 12, 0, 0), |
| 126 | F(100000000, gpll0, 6, 0, 0), |
Channagoud Kadabi | 6608d02 | 2015-04-20 11:31:56 -0700 | [diff] [blame] | 127 | F(171430000, gpll0, 3, 50, 0), |
Joonwoo Park | 095007a | 2014-06-27 17:57:45 -0700 | [diff] [blame] | 128 | F(200000000, gpll0, 3, 0, 0), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 129 | F_END |
| 130 | }; |
| 131 | |
| 132 | static struct rcg_clk sdcc1_apps_clk_src = |
| 133 | { |
| 134 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 135 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 136 | .m_reg = (uint32_t *) SDCC1_M, |
| 137 | .n_reg = (uint32_t *) SDCC1_N, |
| 138 | .d_reg = (uint32_t *) SDCC1_D, |
| 139 | |
| 140 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 141 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 142 | .current_freq = &rcg_dummy_freq, |
| 143 | |
| 144 | .c = { |
| 145 | .dbg_name = "sdc1_clk", |
| 146 | .ops = &clk_ops_rcg_mnd, |
| 147 | }, |
| 148 | }; |
| 149 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 150 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk_sdx20[] = |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 151 | { |
| 152 | F( 144000, cxo, 16, 3, 25), |
| 153 | F( 400000, cxo, 12, 1, 4), |
| 154 | F( 20000000, gpll0, 15, 1, 2), |
| 155 | F( 25000000, gpll0, 12, 1, 2), |
| 156 | F( 50000000, gpll0, 12, 0, 0), |
| 157 | F( 100000000, gpll0, 6, 0, 0), |
Mayank Grover | b902952 | 2017-04-12 14:57:07 +0530 | [diff] [blame^] | 158 | F(200000000, gpll0, 3, 0, 0), |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 159 | F_END |
| 160 | }; |
| 161 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 162 | static struct rcg_clk sdcc1_apps_clk_src_sdx20 = |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 163 | { |
| 164 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 165 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 166 | .m_reg = (uint32_t *) SDCC1_M, |
| 167 | .n_reg = (uint32_t *) SDCC1_N, |
| 168 | .d_reg = (uint32_t *) SDCC1_D, |
| 169 | |
| 170 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 171 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk_sdx20, |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 172 | .current_freq = &rcg_dummy_freq, |
| 173 | |
| 174 | .c = { |
| 175 | .dbg_name = "sdc1_clk", |
| 176 | .ops = &clk_ops_rcg_mnd, |
| 177 | }, |
| 178 | }; |
| 179 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 180 | static struct branch_clk gcc_sdcc1_apps_clk_sdx20 = |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 181 | { |
| 182 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 183 | .parent = &sdcc1_apps_clk_src_sdx20.c, |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 184 | |
| 185 | .c = { |
| 186 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 187 | .ops = &clk_ops_branch, |
| 188 | }, |
| 189 | }; |
| 190 | |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 191 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 192 | { |
| 193 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 194 | .parent = &sdcc1_apps_clk_src.c, |
| 195 | |
| 196 | .c = { |
| 197 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 198 | .ops = &clk_ops_branch, |
| 199 | }, |
| 200 | }; |
| 201 | |
| 202 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 203 | { |
| 204 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 205 | .has_sibling = 1, |
| 206 | |
| 207 | .c = { |
| 208 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 209 | .ops = &clk_ops_branch, |
| 210 | }, |
| 211 | }; |
| 212 | |
| 213 | /* UART Clocks */ |
| 214 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 215 | { |
Joonwoo Park | 095007a | 2014-06-27 17:57:45 -0700 | [diff] [blame] | 216 | F( 3686400, gpll0, 1, 96, 15625), |
| 217 | F( 7372800, gpll0, 1, 192, 15625), |
| 218 | F(14745600, gpll0, 1, 384, 15625), |
| 219 | F(16000000, gpll0, 5, 2, 15), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 220 | F(19200000, cxo, 1, 0, 0), |
Joonwoo Park | 095007a | 2014-06-27 17:57:45 -0700 | [diff] [blame] | 221 | F(24000000, gpll0, 5, 1, 5), |
| 222 | F(32000000, gpll0, 1, 4, 75), |
| 223 | F(40000000, gpll0, 15, 0, 0), |
| 224 | F(46400000, gpll0, 1, 29, 375), |
| 225 | F(48000000, gpll0, 12.5, 0, 0), |
| 226 | F(51200000, gpll0, 1, 32, 375), |
| 227 | F(56000000, gpll0, 1, 7, 75), |
| 228 | F(58982400, gpll0, 1, 1536, 15625), |
| 229 | F(60000000, gpll0, 10, 0, 0), |
| 230 | F(63160000, gpll0, 9.5, 0, 0), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 231 | F_END |
| 232 | }; |
| 233 | |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 234 | static struct rcg_clk blsp1_uart3_apps_clk_src = |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 235 | { |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 236 | .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR, |
| 237 | .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR, |
| 238 | .m_reg = (uint32_t *) BLSP1_UART3_APPS_M, |
| 239 | .n_reg = (uint32_t *) BLSP1_UART3_APPS_N, |
| 240 | .d_reg = (uint32_t *) BLSP1_UART3_APPS_D, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 241 | |
| 242 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 243 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 244 | .current_freq = &rcg_dummy_freq, |
| 245 | |
| 246 | .c = { |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 247 | .dbg_name = "blsp1_uart3_apps_clk", |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 248 | .ops = &clk_ops_rcg_mnd, |
| 249 | }, |
| 250 | }; |
| 251 | |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 252 | static struct branch_clk gcc_blsp1_uart3_apps_clk = |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 253 | { |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 254 | .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR, |
| 255 | .parent = &blsp1_uart3_apps_clk_src.c, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 256 | |
| 257 | .c = { |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 258 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 259 | .ops = &clk_ops_branch, |
| 260 | }, |
| 261 | }; |
| 262 | |
| 263 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 264 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 265 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 266 | .en_mask = BIT(10), |
| 267 | |
| 268 | .c = { |
| 269 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 270 | .ops = &clk_ops_vote, |
| 271 | }, |
| 272 | }; |
| 273 | |
| 274 | /* USB Clocks */ |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 275 | static struct branch_clk gcc_sys_noc_usb30_axi_clk = |
| 276 | { |
| 277 | .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR, |
| 278 | .has_sibling = 1, |
| 279 | |
| 280 | .c = { |
| 281 | .dbg_name = "gcc_sys_noc_usb3_axi_clk", |
| 282 | .ops = &clk_ops_branch, |
| 283 | }, |
| 284 | }; |
| 285 | |
| 286 | static struct branch_clk gcc_usb_phy_cfg_ahb_clk = { |
| 287 | .cbcr_reg = (uint32_t *) USB_PHY_CFG_AHB_CBCR, |
| 288 | .has_sibling = 1, |
| 289 | |
| 290 | .c = { |
| 291 | .dbg_name = "gcc_usb_phy_cfg_ahb_clk", |
| 292 | .ops = &clk_ops_branch, |
| 293 | }, |
| 294 | }; |
| 295 | |
| 296 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = |
| 297 | { |
| 298 | F(125000000, gpll0, 1, 5, 24), |
| 299 | F_END |
| 300 | }; |
| 301 | |
| 302 | static struct rcg_clk usb30_master_clk_src = |
| 303 | { |
| 304 | .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR, |
| 305 | .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR, |
| 306 | .m_reg = (uint32_t *) GCC_USB30_MASTER_M, |
| 307 | .n_reg = (uint32_t *) GCC_USB30_MASTER_N, |
| 308 | .d_reg = (uint32_t *) GCC_USB30_MASTER_D, |
| 309 | |
| 310 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 311 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
| 312 | .current_freq = &rcg_dummy_freq, |
| 313 | |
| 314 | .c = { |
| 315 | .dbg_name = "usb30_master_clk_src", |
| 316 | .ops = &clk_ops_rcg, |
| 317 | }, |
| 318 | }; |
| 319 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 320 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk_sdx20[] = |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 321 | { |
| 322 | F(30000000, gpll0, 10, 0, 0), |
| 323 | F(60000000, gpll0, 5, 0, 0), |
| 324 | F(120000000, gpll0, 5, 0, 0), |
| 325 | F(171430000, gpll0, 3.5, 0, 0), |
| 326 | F(200000000, gpll0, 3, 0, 0), |
| 327 | F_END |
| 328 | }; |
| 329 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 330 | static struct rcg_clk usb30_master_clk_src_sdx20 = |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 331 | { |
| 332 | .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR, |
| 333 | .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR, |
| 334 | .m_reg = (uint32_t *) GCC_USB30_MASTER_M, |
| 335 | .n_reg = (uint32_t *) GCC_USB30_MASTER_N, |
| 336 | .d_reg = (uint32_t *) GCC_USB30_MASTER_D, |
| 337 | |
| 338 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 339 | .freq_tbl = ftbl_gcc_usb30_master_clk_sdx20, |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 340 | .current_freq = &rcg_dummy_freq, |
| 341 | |
| 342 | .c = { |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 343 | .dbg_name = "usb30_master_clk_src_sdx20", |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 344 | .ops = &clk_ops_rcg, |
| 345 | }, |
| 346 | }; |
| 347 | |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 348 | static struct branch_clk gcc_usb30_master_clk = |
| 349 | { |
| 350 | .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR, |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 351 | .bcr_reg = (uint32_t *) USB_30_BCR, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 352 | .parent = &usb30_master_clk_src.c, |
| 353 | |
| 354 | .c = { |
| 355 | .dbg_name = "gcc_usb30_master_clk", |
| 356 | .ops = &clk_ops_branch, |
| 357 | }, |
| 358 | }; |
| 359 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 360 | static struct branch_clk gcc_usb30_master_clk_sdx20 = |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 361 | { |
| 362 | .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR, |
| 363 | .bcr_reg = (uint32_t *) USB_30_BCR, |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 364 | .parent = &usb30_master_clk_src_sdx20.c, |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 365 | |
| 366 | .c = { |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 367 | .dbg_name = "gcc_usb30_master_clk_sdx20", |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 368 | .ops = &clk_ops_branch, |
| 369 | }, |
| 370 | }; |
| 371 | |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 372 | static struct clk_freq_tbl ftbl_gcc_usb30_pipe_clk[] = { |
| 373 | F( 19200000, cxo, 1, 0, 0), |
| 374 | F_EXT_SRC( 125000000, usb30_pipe, 1, 0, 0), |
| 375 | F_END |
| 376 | }; |
| 377 | |
| 378 | static struct rcg_clk usb30_pipe_clk_src = { |
| 379 | .cmd_reg = (uint32_t *) USB3_PIPE_CMD_RCGR, |
| 380 | .cfg_reg = (uint32_t *) USB3_PIPE_CFG_RCGR, |
| 381 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 382 | .freq_tbl = ftbl_gcc_usb30_pipe_clk, |
| 383 | .current_freq = &rcg_dummy_freq, |
| 384 | |
| 385 | .c = { |
| 386 | .dbg_name = "usb30_pipe_clk_src", |
| 387 | .ops = &clk_ops_rcg, |
| 388 | }, |
| 389 | }; |
| 390 | |
| 391 | static struct branch_clk gcc_usb30_pipe_clk = { |
| 392 | .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR, |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 393 | .bcr_reg = (uint32_t *) USB3_PIPE_BCR, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 394 | .parent = &usb30_pipe_clk_src.c, |
| 395 | .has_sibling = 0, |
| 396 | |
| 397 | .c = { |
| 398 | .dbg_name = "gcc_usb30_pipe_clk", |
| 399 | .ops = &clk_ops_branch, |
| 400 | }, |
| 401 | }; |
| 402 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 403 | static struct branch_clk gcc_usb30_pipe_clk_sdx20 = { |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 404 | .bcr_reg = (uint32_t *) USB3_PIPE_BCR, |
| 405 | .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR, |
| 406 | .has_sibling = 1, |
| 407 | .halt_check = 0, |
| 408 | |
| 409 | .c = { |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 410 | .dbg_name = "usb30_pipe_clk_sdx20", |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 411 | .ops = &clk_ops_branch, |
| 412 | }, |
| 413 | }; |
| 414 | |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 415 | |
Karthik Jadala | 8e6b219 | 2017-02-08 12:59:16 +0530 | [diff] [blame] | 416 | static struct branch_clk gcc_usb30_pipe_clk_mdm9650 = { |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 417 | .bcr_reg = (uint32_t *) USB3_PIPE_BCR, |
| 418 | .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR, |
| 419 | .has_sibling = 1, |
| 420 | .halt_check = 0, |
| 421 | |
| 422 | .c = { |
Karthik Jadala | 8e6b219 | 2017-02-08 12:59:16 +0530 | [diff] [blame] | 423 | .dbg_name = "usb30_pipe_clk_mdm9650", |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 424 | .ops = &clk_ops_branch, |
| 425 | }, |
| 426 | }; |
| 427 | |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 428 | static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = { |
| 429 | F( 1000000, cxo, 1, 5, 96), |
| 430 | F_END |
| 431 | }; |
| 432 | |
| 433 | static struct rcg_clk usb30_aux_clk_src = { |
| 434 | .cmd_reg = (uint32_t *) USB3_AUX_CMD_RCGR, |
| 435 | .cfg_reg = (uint32_t *) USB3_AUX_CFG_RCGR, |
| 436 | .m_reg = (uint32_t *) USB3_AUX_M, |
| 437 | .n_reg = (uint32_t *) USB3_AUX_N, |
| 438 | .d_reg = (uint32_t *) USB3_AUX_D, |
| 439 | |
| 440 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 441 | .freq_tbl = ftbl_gcc_usb30_aux_clk, |
| 442 | .current_freq = &rcg_dummy_freq, |
| 443 | |
| 444 | .c = { |
| 445 | .dbg_name = "usb30_aux_clk_src", |
| 446 | .ops = &clk_ops_rcg_mnd, |
| 447 | }, |
| 448 | }; |
| 449 | |
| 450 | static struct branch_clk gcc_usb30_aux_clk = { |
| 451 | .cbcr_reg = (uint32_t *) USB3_AUX_CBCR, |
| 452 | .parent = &usb30_aux_clk_src.c, |
| 453 | |
| 454 | .c = { |
| 455 | .dbg_name = "gcc_usb30_aux_clk", |
| 456 | .ops = &clk_ops_branch, |
| 457 | }, |
| 458 | }; |
| 459 | |
| 460 | static struct reset_clk gcc_usb30_phy_reset = { |
Sridhar Parasuram | 673c6bb | 2014-12-29 13:39:35 -0800 | [diff] [blame] | 461 | .bcr_reg = (uint32_t) USB3_PHY_BCR, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 462 | |
| 463 | .c = { |
| 464 | .dbg_name = "usb30_phy_reset", |
| 465 | .ops = &clk_ops_reset, |
| 466 | }, |
| 467 | }; |
| 468 | |
Joonwoo Park | 76641c7 | 2014-05-22 16:37:10 -0700 | [diff] [blame] | 469 | static struct reset_clk gcc_usb2a_phy_sleep_clk = { |
Sridhar Parasuram | 673c6bb | 2014-12-29 13:39:35 -0800 | [diff] [blame] | 470 | .bcr_reg = (uint32_t) QUSB2A_PHY_BCR, |
Joonwoo Park | 76641c7 | 2014-05-22 16:37:10 -0700 | [diff] [blame] | 471 | |
| 472 | .c = { |
| 473 | .dbg_name = "usb2b_phy_sleep_clk", |
| 474 | .ops = &clk_ops_reset, |
| 475 | }, |
| 476 | }; |
| 477 | |
vijay kumar | 7d06bbb | 2015-11-24 13:04:55 +0530 | [diff] [blame] | 478 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 479 | F(160000000, gpll0, 5, 0, 0), |
| 480 | F_END |
| 481 | }; |
| 482 | |
| 483 | static struct rcg_clk ce1_clk_src = { |
| 484 | .cmd_reg = (uint32_t *) GCC_CRYPTO_CMD_RCGR, |
| 485 | .cfg_reg = (uint32_t *) GCC_CRYPTO_CFG_RCGR, |
| 486 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 487 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 488 | .current_freq = &rcg_dummy_freq, |
| 489 | |
| 490 | .c = { |
| 491 | .dbg_name = "ce1_clk_src", |
| 492 | .ops = &clk_ops_rcg, |
| 493 | }, |
| 494 | }; |
| 495 | |
| 496 | static struct vote_clk gcc_ce1_clk = { |
| 497 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_CBCR, |
| 498 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 499 | .en_mask = BIT(2), |
| 500 | |
| 501 | .c = { |
| 502 | .dbg_name = "gcc_ce1_clk", |
| 503 | .ops = &clk_ops_vote, |
| 504 | }, |
| 505 | }; |
| 506 | |
| 507 | static struct vote_clk gcc_ce1_ahb_clk = { |
| 508 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR, |
| 509 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 510 | .en_mask = BIT(0), |
| 511 | |
| 512 | .c = { |
| 513 | .dbg_name = "gcc_ce1_ahb_clk", |
| 514 | .ops = &clk_ops_vote, |
| 515 | }, |
| 516 | }; |
| 517 | |
| 518 | static struct vote_clk gcc_ce1_axi_clk = { |
| 519 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AXI_CBCR, |
| 520 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 521 | .en_mask = BIT(1), |
| 522 | |
| 523 | .c = { |
| 524 | .dbg_name = "gcc_ce1_axi_clk", |
| 525 | .ops = &clk_ops_vote, |
| 526 | }, |
| 527 | }; |
| 528 | |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 529 | static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { |
| 530 | F( 60000000, gpll0, 10, 0, 0), |
| 531 | F_END |
| 532 | }; |
| 533 | |
| 534 | static struct rcg_clk usb30_mock_utmi_clk_src = { |
| 535 | .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR, |
| 536 | .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR, |
| 537 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 538 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, |
| 539 | .current_freq = &rcg_dummy_freq, |
| 540 | |
| 541 | .c = { |
| 542 | .dbg_name = "usb30_mock_utmi_clk_src", |
| 543 | .ops = &clk_ops_rcg, |
| 544 | }, |
| 545 | }; |
| 546 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 547 | static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src_sdx20[] = { |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 548 | F( 19200000, cxo, 1, 0, 0), |
| 549 | F_END |
| 550 | }; |
| 551 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 552 | static struct rcg_clk usb30_mock_utmi_clk_src_sdx20 = { |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 553 | .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR, |
| 554 | .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR, |
| 555 | .set_rate = clock_lib2_rcg_set_rate_hid, |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 556 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src_sdx20, |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 557 | .current_freq = &rcg_dummy_freq, |
| 558 | |
| 559 | .c = { |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 560 | .dbg_name = "usb30_mock_utmi_clk_src_sdx20", |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 561 | .ops = &clk_ops_rcg, |
| 562 | }, |
| 563 | }; |
| 564 | |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 565 | static struct branch_clk gcc_usb30_mock_utmi_clk = { |
| 566 | .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR, |
| 567 | .has_sibling = 0, |
| 568 | .parent = &usb30_mock_utmi_clk_src.c, |
| 569 | |
| 570 | .c = { |
| 571 | .dbg_name = "usb30_mock_utmi_clk", |
| 572 | .ops = &clk_ops_branch, |
| 573 | }, |
| 574 | }; |
| 575 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 576 | static struct branch_clk gcc_usb30_mock_utmi_clk_sdx20 = { |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 577 | .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR, |
| 578 | .has_sibling = 0, |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 579 | .parent = &usb30_mock_utmi_clk_src_sdx20.c, |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 580 | |
| 581 | .c = { |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 582 | .dbg_name = "usb30_mock_utmi_clk_sdx20", |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 583 | .ops = &clk_ops_branch, |
| 584 | }, |
| 585 | }; |
| 586 | |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 587 | static struct branch_clk gcc_usb30_sleep_clk = { |
| 588 | .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR, |
| 589 | .has_sibling = 1, |
| 590 | |
| 591 | .c = { |
| 592 | .dbg_name = "usb30_sleep_clk", |
| 593 | .ops = &clk_ops_branch, |
| 594 | }, |
| 595 | }; |
| 596 | |
| 597 | |
| 598 | |
anisha agarwal | dd04af6 | 2014-11-17 10:57:49 -0800 | [diff] [blame] | 599 | static struct clk_lookup msm_clocks_9640[] = |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 600 | { |
| 601 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 602 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 603 | CLK_LOOKUP("sdc1_core_clk_sdx20", gcc_sdcc1_apps_clk_sdx20.c), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 604 | |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 605 | CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c), |
| 606 | CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 607 | |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 608 | CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c), |
| 609 | CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c), |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 610 | CLK_LOOKUP("usb30_master_clk_sdx20", gcc_usb30_master_clk_sdx20.c), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 611 | CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c), |
Karthik Jadala | 8e6b219 | 2017-02-08 12:59:16 +0530 | [diff] [blame] | 612 | CLK_LOOKUP("usb30_pipe_clk_mdm9650", gcc_usb30_pipe_clk_mdm9650.c), |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 613 | CLK_LOOKUP("usb30_pipe_clk_sdx20", gcc_usb30_pipe_clk_sdx20.c), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 614 | CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c), |
| 615 | |
Joonwoo Park | 76641c7 | 2014-05-22 16:37:10 -0700 | [diff] [blame] | 616 | CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 617 | CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c), |
| 618 | |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 619 | CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c), |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 620 | CLK_LOOKUP("usb30_mock_utmi_clk_sdx20", gcc_usb30_mock_utmi_clk_sdx20.c), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 621 | CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c), |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 622 | CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c), |
vijay kumar | 7d06bbb | 2015-11-24 13:04:55 +0530 | [diff] [blame] | 623 | CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c), |
| 624 | CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c), |
| 625 | CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c), |
| 626 | CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 627 | }; |
| 628 | |
| 629 | void platform_clock_init(void) |
| 630 | { |
anisha agarwal | dd04af6 | 2014-11-17 10:57:49 -0800 | [diff] [blame] | 631 | clk_init(msm_clocks_9640, ARRAY_SIZE(msm_clocks_9640)); |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 632 | } |