Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | #include <platform.h> |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define gpll4_source_val 2 |
| 43 | #define cxo_mm_source_val 0 |
| 44 | #define gpll0_mm_source_val 1 |
| 45 | |
| 46 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 47 | |
| 48 | |
| 49 | /* Clock Operations */ |
| 50 | static struct clk_ops clk_ops_branch = |
| 51 | { |
| 52 | .enable = clock_lib2_branch_clk_enable, |
| 53 | .disable = clock_lib2_branch_clk_disable, |
| 54 | .set_rate = clock_lib2_branch_set_rate, |
| 55 | }; |
| 56 | |
| 57 | static struct clk_ops clk_ops_rcg_mnd = |
| 58 | { |
| 59 | .enable = clock_lib2_rcg_enable, |
| 60 | .set_rate = clock_lib2_rcg_set_rate, |
| 61 | }; |
| 62 | |
| 63 | static struct clk_ops clk_ops_rcg = |
| 64 | { |
| 65 | .enable = clock_lib2_rcg_enable, |
| 66 | .set_rate = clock_lib2_rcg_set_rate, |
| 67 | }; |
| 68 | |
| 69 | static struct clk_ops clk_ops_cxo = |
| 70 | { |
| 71 | .enable = cxo_clk_enable, |
| 72 | .disable = cxo_clk_disable, |
| 73 | }; |
| 74 | |
| 75 | static struct clk_ops clk_ops_pll_vote = |
| 76 | { |
| 77 | .enable = pll_vote_clk_enable, |
| 78 | .disable = pll_vote_clk_disable, |
| 79 | .auto_off = pll_vote_clk_disable, |
| 80 | .is_enabled = pll_vote_clk_is_enabled, |
| 81 | }; |
| 82 | |
| 83 | static struct clk_ops clk_ops_vote = |
| 84 | { |
| 85 | .enable = clock_lib2_vote_clk_enable, |
| 86 | .disable = clock_lib2_vote_clk_disable, |
| 87 | }; |
| 88 | |
| 89 | /* Clock Sources */ |
| 90 | static struct fixed_clk cxo_clk_src = |
| 91 | { |
| 92 | .c = { |
| 93 | .rate = 19200000, |
| 94 | .dbg_name = "cxo_clk_src", |
| 95 | .ops = &clk_ops_cxo, |
| 96 | }, |
| 97 | }; |
| 98 | |
| 99 | static struct pll_vote_clk gpll0_clk_src = |
| 100 | { |
| 101 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 102 | .en_mask = BIT(0), |
| 103 | .status_reg = (void *) GPLL0_STATUS, |
| 104 | .status_mask = BIT(17), |
| 105 | .parent = &cxo_clk_src.c, |
| 106 | |
| 107 | .c = { |
| 108 | .rate = 800000000, |
| 109 | .dbg_name = "gpll0_clk_src", |
| 110 | .ops = &clk_ops_pll_vote, |
| 111 | }, |
| 112 | }; |
| 113 | |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 114 | static struct pll_vote_clk gpll4_clk_src = |
| 115 | { |
| 116 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 117 | .en_mask = BIT(5), |
| 118 | .status_reg = (void *) GPLL4_MODE, |
| 119 | .status_mask = BIT(30), |
| 120 | .parent = &cxo_clk_src.c, |
| 121 | |
| 122 | .c = { |
| 123 | .rate = 1152000000, |
| 124 | .dbg_name = "gpll4_clk_src", |
| 125 | .ops = &clk_ops_pll_vote, |
| 126 | }, |
| 127 | }; |
| 128 | |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 129 | /* SDCC Clocks */ |
| 130 | static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = |
| 131 | { |
| 132 | F( 144000, cxo, 16, 3, 25), |
| 133 | F( 400000, cxo, 12, 1, 4), |
| 134 | F( 20000000, gpll0, 10, 1, 4), |
| 135 | F( 25000000, gpll0, 16, 1, 2), |
| 136 | F( 50000000, gpll0, 16, 0, 0), |
| 137 | F(100000000, gpll0, 8, 0, 0), |
| 138 | F(177770000, gpll0, 4.5, 0, 0), |
Aparna Mallavarapu | f47a868 | 2015-04-20 13:22:08 +0530 | [diff] [blame] | 139 | F(192000000, gpll4, 6, 0, 0), |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 140 | F(384000000, gpll4, 3, 0, 0), |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 141 | F_END |
| 142 | }; |
| 143 | |
| 144 | static struct rcg_clk sdcc1_apps_clk_src = |
| 145 | { |
| 146 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 147 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 148 | .m_reg = (uint32_t *) SDCC1_M, |
| 149 | .n_reg = (uint32_t *) SDCC1_N, |
| 150 | .d_reg = (uint32_t *) SDCC1_D, |
| 151 | |
| 152 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 153 | .freq_tbl = ftbl_gcc_sdcc1_apps_clk, |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 154 | .current_freq = &rcg_dummy_freq, |
| 155 | |
| 156 | .c = { |
| 157 | .dbg_name = "sdc1_clk", |
| 158 | .ops = &clk_ops_rcg_mnd, |
| 159 | }, |
| 160 | }; |
| 161 | |
| 162 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 163 | { |
| 164 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 165 | .parent = &sdcc1_apps_clk_src.c, |
| 166 | |
| 167 | .c = { |
| 168 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 169 | .ops = &clk_ops_branch, |
| 170 | }, |
| 171 | }; |
| 172 | |
| 173 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 174 | { |
| 175 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 176 | .has_sibling = 1, |
| 177 | |
| 178 | .c = { |
| 179 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 180 | .ops = &clk_ops_branch, |
| 181 | }, |
| 182 | }; |
| 183 | |
| 184 | static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = |
| 185 | { |
| 186 | F( 144000, cxo, 16, 3, 25), |
| 187 | F( 400000, cxo, 12, 1, 4), |
| 188 | F( 20000000, gpll0, 10, 1, 4), |
| 189 | F( 25000000, gpll0, 16, 1, 2), |
| 190 | F( 50000000, gpll0, 16, 0, 0), |
| 191 | F(100000000, gpll0, 8, 0, 0), |
| 192 | F(177770000, gpll0, 4.5, 0, 0), |
| 193 | F(200000000, gpll0, 4, 0, 0), |
| 194 | F_END |
| 195 | }; |
| 196 | |
| 197 | static struct rcg_clk sdcc2_apps_clk_src = |
| 198 | { |
| 199 | .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR, |
| 200 | .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR, |
| 201 | .m_reg = (uint32_t *) SDCC2_M, |
| 202 | .n_reg = (uint32_t *) SDCC2_N, |
| 203 | .d_reg = (uint32_t *) SDCC2_D, |
| 204 | |
| 205 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 206 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk, |
| 207 | .current_freq = &rcg_dummy_freq, |
| 208 | |
| 209 | .c = { |
| 210 | .dbg_name = "sdc2_clk", |
| 211 | .ops = &clk_ops_rcg_mnd, |
| 212 | }, |
| 213 | }; |
| 214 | |
| 215 | static struct branch_clk gcc_sdcc2_apps_clk = |
| 216 | { |
| 217 | .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR, |
| 218 | .parent = &sdcc2_apps_clk_src.c, |
| 219 | |
| 220 | .c = { |
| 221 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 222 | .ops = &clk_ops_branch, |
| 223 | }, |
| 224 | }; |
| 225 | |
| 226 | static struct branch_clk gcc_sdcc2_ahb_clk = |
| 227 | { |
| 228 | .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR, |
| 229 | .has_sibling = 1, |
| 230 | |
| 231 | .c = { |
| 232 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 233 | .ops = &clk_ops_branch, |
| 234 | }, |
| 235 | }; |
| 236 | |
| 237 | /* UART Clocks */ |
| 238 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = |
| 239 | { |
| 240 | F( 3686400, gpll0, 1, 72, 15625), |
| 241 | F( 7372800, gpll0, 1, 144, 15625), |
| 242 | F(14745600, gpll0, 1, 288, 15625), |
| 243 | F(16000000, gpll0, 10, 1, 5), |
| 244 | F(19200000, cxo, 1, 0, 0), |
| 245 | F(24000000, gpll0, 1, 3, 100), |
| 246 | F(25000000, gpll0, 16, 1, 2), |
| 247 | F(32000000, gpll0, 1, 1, 25), |
| 248 | F(40000000, gpll0, 1, 1, 20), |
| 249 | F(46400000, gpll0, 1, 29, 500), |
| 250 | F(48000000, gpll0, 1, 3, 50), |
| 251 | F(51200000, gpll0, 1, 8, 125), |
| 252 | F(56000000, gpll0, 1, 7, 100), |
| 253 | F(58982400, gpll0, 1,1152, 15625), |
| 254 | F(60000000, gpll0, 1, 3, 40), |
| 255 | F_END |
| 256 | }; |
| 257 | |
| 258 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 259 | { |
| 260 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 261 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 262 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 263 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 264 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 265 | |
| 266 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 267 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk, |
| 268 | .current_freq = &rcg_dummy_freq, |
| 269 | |
| 270 | .c = { |
| 271 | .dbg_name = "blsp1_uart2_apps_clk", |
| 272 | .ops = &clk_ops_rcg_mnd, |
| 273 | }, |
| 274 | }; |
| 275 | |
| 276 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 277 | { |
| 278 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 279 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 280 | |
| 281 | .c = { |
| 282 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 283 | .ops = &clk_ops_branch, |
| 284 | }, |
| 285 | }; |
| 286 | |
| 287 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 288 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 289 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 290 | .en_mask = BIT(10), |
| 291 | |
| 292 | .c = { |
| 293 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 294 | .ops = &clk_ops_vote, |
| 295 | }, |
| 296 | }; |
| 297 | |
| 298 | /* USB Clocks */ |
| 299 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 300 | { |
Aparna Mallavarapu | bbec463 | 2015-05-27 17:48:01 +0530 | [diff] [blame^] | 301 | F(100000000, gpll0, 10, 0, 0), |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 302 | F(133330000, gpll0, 6, 0, 0), |
| 303 | F_END |
| 304 | }; |
| 305 | |
| 306 | static struct rcg_clk usb_hs_system_clk_src = |
| 307 | { |
| 308 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 309 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 310 | |
| 311 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 312 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 313 | .current_freq = &rcg_dummy_freq, |
| 314 | |
| 315 | .c = { |
| 316 | .dbg_name = "usb_hs_system_clk", |
| 317 | .ops = &clk_ops_rcg, |
| 318 | }, |
| 319 | }; |
| 320 | |
| 321 | static struct branch_clk gcc_usb_hs_system_clk = |
| 322 | { |
| 323 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 324 | .parent = &usb_hs_system_clk_src.c, |
| 325 | |
| 326 | .c = { |
| 327 | .dbg_name = "gcc_usb_hs_system_clk", |
| 328 | .ops = &clk_ops_branch, |
| 329 | }, |
| 330 | }; |
| 331 | |
| 332 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 333 | { |
| 334 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 335 | .has_sibling = 1, |
| 336 | |
| 337 | .c = { |
| 338 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 339 | .ops = &clk_ops_branch, |
| 340 | }, |
| 341 | }; |
| 342 | |
Padmanabhan Komanduru | fba6632 | 2015-04-13 12:47:31 -0700 | [diff] [blame] | 343 | /* Display clocks */ |
| 344 | static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = { |
| 345 | F_MM(19200000, cxo, 1, 0, 0), |
| 346 | F_END |
| 347 | }; |
| 348 | |
| 349 | static struct clk_freq_tbl ftbl_mdp_clk[] = { |
| 350 | F_MM( 80000000, gpll0, 10, 0, 0), |
| 351 | F_MM( 100000000, gpll0, 8, 0, 0), |
| 352 | F_MM( 200000000, gpll0, 4, 0, 0), |
| 353 | F_MM( 320000000, gpll0, 2.5, 0, 0), |
| 354 | F_END |
| 355 | }; |
| 356 | |
| 357 | static struct rcg_clk dsi_esc0_clk_src = { |
| 358 | .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR, |
| 359 | .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR, |
| 360 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 361 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
| 362 | |
| 363 | .c = { |
| 364 | .dbg_name = "dsi_esc0_clk_src", |
| 365 | .ops = &clk_ops_rcg, |
| 366 | }, |
| 367 | }; |
| 368 | |
| 369 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 370 | F_MM(19200000, cxo, 1, 0, 0), |
| 371 | F_END |
| 372 | }; |
| 373 | |
| 374 | static struct rcg_clk vsync_clk_src = { |
| 375 | .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR, |
| 376 | .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR, |
| 377 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 378 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 379 | |
| 380 | .c = { |
| 381 | .dbg_name = "vsync_clk_src", |
| 382 | .ops = &clk_ops_rcg, |
| 383 | }, |
| 384 | }; |
| 385 | |
| 386 | static struct branch_clk mdss_esc0_clk = { |
| 387 | .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR, |
| 388 | .parent = &dsi_esc0_clk_src.c, |
| 389 | .has_sibling = 0, |
| 390 | |
| 391 | .c = { |
| 392 | .dbg_name = "mdss_esc0_clk", |
| 393 | .ops = &clk_ops_branch, |
| 394 | }, |
| 395 | }; |
| 396 | |
| 397 | static struct branch_clk mdss_axi_clk = { |
| 398 | .cbcr_reg = (uint32_t *) MDP_AXI_CBCR, |
| 399 | .has_sibling = 1, |
| 400 | |
| 401 | .c = { |
| 402 | .dbg_name = "mdss_axi_clk", |
| 403 | .ops = &clk_ops_branch, |
| 404 | }, |
| 405 | }; |
| 406 | |
| 407 | static struct branch_clk mdp_ahb_clk = { |
| 408 | .cbcr_reg = (uint32_t *) MDP_AHB_CBCR, |
| 409 | .has_sibling = 1, |
| 410 | |
| 411 | .c = { |
| 412 | .dbg_name = "mdp_ahb_clk", |
| 413 | .ops = &clk_ops_branch, |
| 414 | }, |
| 415 | }; |
| 416 | |
| 417 | static struct rcg_clk mdss_mdp_clk_src = { |
| 418 | .cmd_reg = (uint32_t *) MDP_CMD_RCGR, |
| 419 | .cfg_reg = (uint32_t *) MDP_CFG_RCGR, |
| 420 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 421 | .freq_tbl = ftbl_mdp_clk, |
| 422 | .current_freq = &rcg_dummy_freq, |
| 423 | |
| 424 | .c = { |
| 425 | .dbg_name = "mdss_mdp_clk_src", |
| 426 | .ops = &clk_ops_rcg, |
| 427 | }, |
| 428 | }; |
| 429 | |
| 430 | static struct branch_clk mdss_mdp_clk = { |
| 431 | .cbcr_reg = (uint32_t *) MDP_CBCR, |
| 432 | .parent = &mdss_mdp_clk_src.c, |
| 433 | .has_sibling = 0, |
| 434 | |
| 435 | .c = { |
| 436 | .dbg_name = "mdss_mdp_clk", |
| 437 | .ops = &clk_ops_branch, |
| 438 | }, |
| 439 | }; |
| 440 | |
| 441 | static struct branch_clk mdss_vsync_clk = { |
| 442 | .cbcr_reg = (uint32_t *) MDSS_VSYNC_CBCR, |
| 443 | .parent = &vsync_clk_src.c, |
| 444 | .has_sibling = 0, |
| 445 | |
| 446 | .c = { |
| 447 | .dbg_name = "mdss_vsync_clk", |
| 448 | .ops = &clk_ops_branch, |
| 449 | }, |
| 450 | }; |
| 451 | |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 452 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 453 | F(160000000, gpll0, 5, 0, 0), |
| 454 | F_END |
| 455 | }; |
| 456 | |
| 457 | static struct rcg_clk ce1_clk_src = { |
| 458 | .cmd_reg = (uint32_t *) GCC_CRYPTO_CMD_RCGR, |
| 459 | .cfg_reg = (uint32_t *) GCC_CRYPTO_CFG_RCGR, |
| 460 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 461 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 462 | .current_freq = &rcg_dummy_freq, |
| 463 | |
| 464 | .c = { |
| 465 | .dbg_name = "ce1_clk_src", |
| 466 | .ops = &clk_ops_rcg, |
| 467 | }, |
| 468 | }; |
| 469 | |
| 470 | static struct vote_clk gcc_ce1_clk = { |
| 471 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_CBCR, |
| 472 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 473 | .en_mask = BIT(2), |
| 474 | |
| 475 | .c = { |
| 476 | .dbg_name = "gcc_ce1_clk", |
| 477 | .ops = &clk_ops_vote, |
| 478 | }, |
| 479 | }; |
| 480 | |
| 481 | static struct vote_clk gcc_ce1_ahb_clk = { |
| 482 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR, |
| 483 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 484 | .en_mask = BIT(0), |
| 485 | |
| 486 | .c = { |
| 487 | .dbg_name = "gcc_ce1_ahb_clk", |
| 488 | .ops = &clk_ops_vote, |
| 489 | }, |
| 490 | }; |
| 491 | |
| 492 | static struct vote_clk gcc_ce1_axi_clk = { |
| 493 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AXI_CBCR, |
| 494 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 495 | .en_mask = BIT(1), |
| 496 | |
| 497 | .c = { |
| 498 | .dbg_name = "gcc_ce1_axi_clk", |
| 499 | .ops = &clk_ops_vote, |
| 500 | }, |
| 501 | }; |
| 502 | |
| 503 | /* Clock lookup table */ |
| 504 | static struct clk_lookup msm_clocks_8952[] = |
| 505 | { |
| 506 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 507 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 508 | |
| 509 | CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c), |
| 510 | CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c), |
| 511 | |
| 512 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 513 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 514 | |
| 515 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 516 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
| 517 | |
Padmanabhan Komanduru | fba6632 | 2015-04-13 12:47:31 -0700 | [diff] [blame] | 518 | CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c), |
| 519 | CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c), |
| 520 | CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c), |
| 521 | CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c), |
| 522 | CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c), |
| 523 | CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c), |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 524 | |
| 525 | CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c), |
| 526 | CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c), |
| 527 | CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c), |
| 528 | CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), |
| 529 | }; |
| 530 | |
| 531 | void platform_clock_init(void) |
| 532 | { |
| 533 | clk_init(msm_clocks_8952, ARRAY_SIZE(msm_clocks_8952)); |
| 534 | } |