Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008, Google Inc. |
| 3 | * All rights reserved. |
Channagoud Kadabi | 3acfb74 | 2011-11-15 18:19:32 +0530 | [diff] [blame] | 4 | * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * * Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * * Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in |
| 13 | * the documentation and/or other materials provided with the |
| 14 | * distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <stdint.h> |
| 31 | #include <kernel/thread.h> |
| 32 | #include <platform/iomap.h> |
| 33 | #include <reg.h> |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 34 | #include <smem.h> |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 35 | #include <debug.h> |
| 36 | #include <mmc.h> |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 37 | |
| 38 | #define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0])) |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 39 | #define BIT(x) (1 << (x)) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 40 | |
| 41 | #define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) |
| 42 | #define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) |
| 43 | #define VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 44 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 45 | #define PLL2_MODE_ADDR (MSM_CLK_CTL_BASE + 0x338) |
| 46 | #define PLL4_MODE_ADDR (MSM_CLK_CTL_BASE + 0x374) |
| 47 | |
| 48 | #define PLL_RESET_N BIT(2) |
| 49 | #define PLL_BYPASSNL BIT(1) |
| 50 | #define PLL_OUTCTRL BIT(0) |
| 51 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 52 | #define SRC_SEL_TCX0 0 /* TCXO */ |
| 53 | #define SRC_SEL_PLL1 1 /* PLL1: modem_pll */ |
| 54 | #define SRC_SEL_PLL2 2 /* PLL2: backup_pll_0 */ |
| 55 | #define SRC_SEL_PLL3 3 /* PLL3: backup_pll_1 */ |
| 56 | #define SRC_SEL_PLL4 6 /* PLL4: sparrow_pll */ |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 57 | |
| 58 | #define DIV_1 0 |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 59 | #define DIV_2 1 |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 60 | #define DIV_3 2 |
| 61 | #define DIV_4 3 |
| 62 | #define DIV_5 4 |
| 63 | #define DIV_6 5 |
| 64 | #define DIV_7 6 |
| 65 | #define DIV_8 7 |
| 66 | #define DIV_9 8 |
| 67 | #define DIV_10 9 |
| 68 | #define DIV_11 10 |
| 69 | #define DIV_12 11 |
| 70 | #define DIV_13 12 |
| 71 | #define DIV_14 13 |
| 72 | #define DIV_15 14 |
| 73 | #define DIV_16 15 |
| 74 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 75 | #define WAIT_CNT 100 |
| 76 | #define VDD_LEVEL 7 |
| 77 | #define MIN_AXI_HZ 120000000 |
| 78 | #define ACPU_800MHZ 41 |
| 79 | |
Channagoud Kadabi | c0b0a36 | 2012-04-19 13:37:25 +0530 | [diff] [blame^] | 80 | #define A11S_CLK_SEL_MASK 0x1 /* bits 2:0 */ |
Shashank Mittal | 302a633 | 2011-05-04 10:32:48 -0700 | [diff] [blame] | 81 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 82 | /* The stepping frequencies have been choosen to make sure the step |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 83 | * is <= 256 MHz for both 7x27a and 7x25a targets. The |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 84 | * table also assumes the ACPU is running at TCXO freq and AHB div is |
| 85 | * set to DIV_1. |
| 86 | * |
| 87 | * To use the tables: |
| 88 | * - Start at location 0/1 depending on clock source sel bit. |
| 89 | * - Set values till end of table skipping every other entry. |
| 90 | * - When you reach the end of the table, you are done scaling. |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 91 | */ |
| 92 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 93 | uint32_t const clk_cntl_reg_val_7627A[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 94 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16, |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 95 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_8 << 8), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 96 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4, |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 97 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8), |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 98 | |
| 99 | /* TODO: Fix it for 800MHz */ |
| 100 | #if 0 |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 101 | (WAIT_CNT << 16) | (SRC_SEL_PLL4 << 4) | DIV_1, |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 102 | #endif |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 103 | }; |
| 104 | |
Channagoud Kadabi | 3acfb74 | 2011-11-15 18:19:32 +0530 | [diff] [blame] | 105 | /* |
| 106 | * Use PLL4 to run acpu @ 1.2 GHZ |
| 107 | */ |
| 108 | uint32_t const clk_cntl_reg_val_8X25[] = { |
| 109 | (WAIT_CNT << 16) | (SRC_SEL_PLL4 << 4) | DIV_2, |
| 110 | (WAIT_CNT << 16) | (SRC_SEL_PLL4 << 12) | (DIV_1 << 8), |
| 111 | }; |
| 112 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 113 | uint32_t const clk_cntl_reg_val_7625A[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 114 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16, |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 115 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_8 << 8), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 116 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4, |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 117 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8), |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 118 | }; |
| 119 | |
Shashank Mittal | 302a633 | 2011-05-04 10:32:48 -0700 | [diff] [blame] | 120 | /* Using DIV_1 for all cases to avoid worrying about turbo vs. normal |
| 121 | * mode. Able to use DIV_1 for all steps because it's the largest AND |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 122 | * the final value. */ |
| 123 | uint32_t const clk_sel_reg_val[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 124 | DIV_1 << 1 | 1, /* Switch to src1 */ |
| 125 | DIV_1 << 1 | 0, /* Switch to src0 */ |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | /* |
| 129 | * Mask to make sure current selected src frequency doesn't change. |
| 130 | */ |
| 131 | uint32_t const clk_cntl_mask[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 132 | 0x0000FF00, /* Mask to read src0 */ |
| 133 | 0x000000FF /* Mask to read src1 */ |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 134 | }; |
| 135 | |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 136 | /* enum for SDC CLK IDs */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 137 | enum { |
| 138 | SDC1_CLK = 19, |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 139 | SDC1_PCLK = 20, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 140 | SDC2_CLK = 21, |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 141 | SDC2_PCLK = 22, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 142 | SDC3_CLK = 23, |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 143 | SDC3_PCLK = 24, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 144 | SDC4_CLK = 25, |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 145 | SDC4_PCLK = 26 |
| 146 | }; |
| 147 | |
| 148 | /* Zero'th entry is dummy */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 149 | static uint8_t sdc_clk[] = { 0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK }; |
| 150 | static uint8_t sdc_pclk[] = { 0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK }; |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 151 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 152 | void mdelay(unsigned msecs); |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 153 | unsigned board_msm_id(void); |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 154 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 155 | void pll_enable(void *pll_mode_addr) |
| 156 | { |
| 157 | /* TODO: Need to add spin-lock to avoid race conditions */ |
| 158 | |
| 159 | uint32_t nVal; |
| 160 | /* Check status */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 161 | nVal = readl(pll_mode_addr); |
| 162 | if (nVal & PLL_OUTCTRL) |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 163 | return; |
| 164 | |
| 165 | /* Put the PLL in reset mode */ |
| 166 | nVal = 0; |
| 167 | nVal &= ~PLL_RESET_N; |
| 168 | nVal &= ~PLL_BYPASSNL; |
| 169 | nVal &= ~PLL_OUTCTRL; |
| 170 | writel(nVal, pll_mode_addr); |
| 171 | |
| 172 | /* Put the PLL in warm-up mode */ |
| 173 | nVal |= PLL_RESET_N; |
| 174 | nVal |= PLL_BYPASSNL; |
| 175 | writel(nVal, pll_mode_addr); |
| 176 | |
| 177 | /* Wait for the PLL warm-up time */ |
| 178 | udelay(50); |
| 179 | |
| 180 | /* Put the PLL in active mode */ |
| 181 | nVal |= PLL_RESET_N; |
| 182 | nVal |= PLL_BYPASSNL; |
| 183 | nVal |= PLL_OUTCTRL; |
| 184 | writel(nVal, pll_mode_addr); |
| 185 | } |
| 186 | |
| 187 | void pll_request(unsigned pll, unsigned enable) |
| 188 | { |
| 189 | int val = 0; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 190 | if (!enable) { |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 191 | /* Disable not supported */ |
| 192 | return; |
| 193 | } |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 194 | switch (pll) { |
| 195 | case 2: |
| 196 | pll_enable(PLL2_MODE_ADDR); |
| 197 | return; |
| 198 | case 4: |
| 199 | pll_enable(PLL4_MODE_ADDR); |
| 200 | return; |
| 201 | default: |
| 202 | return; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 203 | }; |
| 204 | } |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 205 | |
| 206 | void acpu_clock_init(void) |
| 207 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 208 | uint32_t i, clk; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 209 | uint32_t val; |
| 210 | uint32_t *clk_cntl_reg_val, size; |
| 211 | unsigned msm_id; |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 212 | |
| 213 | /* Increase VDD level to the final value. */ |
| 214 | writel((1 << 7) | (VDD_LEVEL << 3), VDD_SVS_PLEVEL_ADDR); |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 215 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 216 | #if (!ENABLE_NANDWRITE) |
| 217 | thread_sleep(1); |
| 218 | #else |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 219 | mdelay(1); |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 220 | #endif |
| 221 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 222 | msm_id = board_msm_id(); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 223 | switch (msm_id) { |
| 224 | case MSM7227A: |
| 225 | case MSM7627A: |
| 226 | case ESM7227A: |
| 227 | clk_cntl_reg_val = clk_cntl_reg_val_7627A; |
| 228 | size = ARRAY_SIZE(clk_cntl_reg_val_7627A); |
| 229 | pll_request(2, 1); |
Shashank Mittal | 5d564b6 | 2011-05-12 10:51:07 -0700 | [diff] [blame] | 230 | |
| 231 | /* TODO: Enable this PLL while switching to 800MHz */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 232 | #if 0 |
| 233 | pll_request(4, 1); |
| 234 | #endif |
| 235 | break; |
Channagoud Kadabi | 3acfb74 | 2011-11-15 18:19:32 +0530 | [diff] [blame] | 236 | case MSM8625: |
| 237 | /* Fix me: Will move to PLL4 later */ |
| 238 | clk_cntl_reg_val = clk_cntl_reg_val_7627A; |
| 239 | size = ARRAY_SIZE(clk_cntl_reg_val_7627A); |
| 240 | pll_request(2, 1); |
| 241 | break; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 242 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 243 | case MSM7225A: |
| 244 | case MSM7625A: |
| 245 | default: |
| 246 | clk_cntl_reg_val = clk_cntl_reg_val_7625A; |
| 247 | size = ARRAY_SIZE(clk_cntl_reg_val_7625A); |
| 248 | pll_request(2, 1); |
| 249 | break; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 250 | }; |
| 251 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 252 | /* Read clock source select bit. */ |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 253 | val = readl(A11S_CLK_SEL_ADDR); |
| 254 | i = val & 1; |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 255 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 256 | /* Jump into table and set every entry. */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 257 | for (; i < size; i++) { |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 258 | |
Channagoud Kadabi | c0b0a36 | 2012-04-19 13:37:25 +0530 | [diff] [blame^] | 259 | val = readl(A11S_CLK_SEL_ADDR); |
| 260 | val |= BIT(1) | BIT(2); |
| 261 | writel(val, A11S_CLK_SEL_ADDR); |
| 262 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 263 | val = readl(A11S_CLK_CNTL_ADDR); |
| 264 | |
| 265 | /* Make sure not to disturb already used src */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 266 | val &= clk_cntl_mask[i % 2]; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 267 | val += clk_cntl_reg_val[i]; |
| 268 | writel(val, A11S_CLK_CNTL_ADDR); |
| 269 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 270 | /* Would need a dmb() here but the whole address space is |
| 271 | * strongly ordered, so it should be fine. |
| 272 | */ |
Shashank Mittal | 302a633 | 2011-05-04 10:32:48 -0700 | [diff] [blame] | 273 | val = readl(A11S_CLK_SEL_ADDR); |
| 274 | val &= ~(A11S_CLK_SEL_MASK); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 275 | val |= (A11S_CLK_SEL_MASK & clk_sel_reg_val[i % 2]); |
Shashank Mittal | 302a633 | 2011-05-04 10:32:48 -0700 | [diff] [blame] | 276 | writel(val, A11S_CLK_SEL_ADDR); |
| 277 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 278 | #if (!ENABLE_NANDWRITE) |
| 279 | thread_sleep(1); |
| 280 | #else |
| 281 | mdelay(1); |
| 282 | #endif |
| 283 | } |
| 284 | } |
Shashank Mittal | ef32541 | 2011-04-01 13:48:26 -0700 | [diff] [blame] | 285 | |
| 286 | void hsusb_clock_init(void) |
| 287 | { |
| 288 | /* USB local clock control not enabled; use proc comm */ |
| 289 | usb_clock_init(); |
| 290 | } |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 291 | |
| 292 | /* Configure MMC clock */ |
| 293 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 294 | { |
| 295 | uint32_t reg = 0; |
| 296 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 297 | if (mmc_clock_set_rate(sdc_clk[interface], freq) < 0) { |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 298 | dprintf(CRITICAL, "Failure setting clock rate for MCLK - " |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 299 | "clk_rate: %d\n!", freq); |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 300 | ASSERT(0); |
| 301 | } |
| 302 | |
| 303 | /* enable clock */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 304 | if (mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0) { |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 305 | dprintf(CRITICAL, "Failure enabling MMC Clock!\n"); |
| 306 | ASSERT(0); |
| 307 | } |
| 308 | |
| 309 | reg |= MMC_BOOT_MCI_CLK_ENABLE; |
| 310 | reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 311 | reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 312 | writel(reg, MMC_BOOT_MCI_CLK); |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 313 | } |
| 314 | |
| 315 | /* Intialize MMC clock */ |
| 316 | void clock_init_mmc(uint32_t interface) |
| 317 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 318 | if (mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0) { |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 319 | dprintf(CRITICAL, "Failure enabling PCLK!\n"); |
| 320 | ASSERT(0); |
| 321 | } |
| 322 | } |