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Travis Geiselbrecht1d0df692008-09-01 02:26:09 -07001/*
2 * Copyright (c) 2008 Travis Geiselbrecht
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23.text
24.globl _start
25_start:
26 b reset
27 b arm_undefined
28 b arm_syscall
29 b arm_prefetch_abort
30 b arm_data_abort
31 b arm_reserved
32 b arm_irq
33 b arm_fiq
34
35reset:
36 /* do some cpu setup */
37#if ARM_WITH_CP15
38 mrc p15, 0, r0, c1, c0, 0
39 /* XXX this is currently for arm926, revist with armv6 cores */
40 /* new thumb behavior, low exception vectors, i/d cache disable, mmu disabled */
41 bic r0, r0, #(1<<15| 1<<13 | 1<<12)
42 bic r0, r0, #(1<<2 | 1<<0)
43 /* enable alignment faults */
44 orr r0, r0, #(1<<1)
45 mcr p15, 0, r0, c1, c0, 0
46#endif
47
Travis Geiselbrechtc3226112008-09-02 02:47:40 -070048#if PLATFORM_OMAP3
49 /* do an omap3 specific setup of the L2 */
50 mov r12, #1
51 .word 0xe1600070
52#endif
53
Travis Geiselbrecht1d0df692008-09-01 02:26:09 -070054 /* set up the stack for irq, fiq, abort, undefined, system/user, and lastly supervisor mode */
55 mrs r0, cpsr
56 bic r0, r0, #0x1f
57
58 ldr r2, =abort_stack_top
59 orr r1, r0, #0x12 // irq
60 msr cpsr_c, r1
61 ldr r13, =irq_save_spot /* save a pointer to a temporary dumping spot used during irq delivery */
62
63 orr r1, r0, #0x11 // fiq
64 msr cpsr_c, r1
65 mov sp, r2
66
67 orr r1, r0, #0x17 // abort
68 msr cpsr_c, r1
69 mov sp, r2
70
71 orr r1, r0, #0x1b // undefined
72 msr cpsr_c, r1
73 mov sp, r2
74
75 orr r1, r0, #0x1f // system
76 msr cpsr_c, r1
77 mov sp, r2
78
79 orr r1, r0, #0x13 // supervisor
80 msr cpsr_c, r1
81 mov sp, r2
82
83 /* copy the initialized data segment out of rom if necessary */
84 ldr r0, =__data_start_rom
85 ldr r1, =__data_start
86 ldr r2, =__data_end
87
88 cmp r0, r1
89 beq __do_bss
90
91__copy_loop:
92 cmp r1, r2
93 ldrlt r3, [r0], #4
94 strlt r3, [r1], #4
95 blt __copy_loop
96
97__do_bss:
98 /* clear out the bss */
99 ldr r0, =__bss_start
100 ldr r1, =_end
101 mov r2, #0
102__bss_loop:
103 cmp r0, r1
104 strlt r2, [r0], #4
105 blt __bss_loop
106
107 bl kmain
108 b .
109
110.ltorg
111
112.bss
113.align 2
114 /* the abort stack is for unrecoverable errors.
115 * also note the initial working stack is set to here.
116 * when the threading system starts up it'll switch to a new
117 * dynamically allocated stack, so we don't need it for very long
118 */
119abort_stack:
120 .skip 1024
121abort_stack_top: