Channagoud Kadabi | d091f70 | 2013-01-07 16:17:37 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 2 | |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation, Inc. nor the names of its |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 29 | #include <bits.h> |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <spmi.h> |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 33 | #include <string.h> |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 34 | #include <pm8x41_hw.h> |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 35 | #include <pm8x41.h> |
| 36 | #include <platform/timer.h> |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 37 | |
Channagoud Kadabi | d091f70 | 2013-01-07 16:17:37 -0800 | [diff] [blame] | 38 | /* SPMI helper functions */ |
| 39 | uint8_t pm8x41_reg_read(uint32_t addr) |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 40 | { |
| 41 | uint8_t val = 0; |
| 42 | struct pmic_arb_cmd cmd; |
| 43 | struct pmic_arb_param param; |
| 44 | |
| 45 | cmd.address = PERIPH_ID(addr); |
| 46 | cmd.offset = REG_OFFSET(addr); |
| 47 | cmd.slave_id = SLAVE_ID(addr); |
| 48 | cmd.priority = 0; |
| 49 | |
| 50 | param.buffer = &val; |
| 51 | param.size = 1; |
| 52 | |
| 53 | pmic_arb_read_cmd(&cmd, ¶m); |
| 54 | |
| 55 | return val; |
| 56 | } |
| 57 | |
Channagoud Kadabi | d091f70 | 2013-01-07 16:17:37 -0800 | [diff] [blame] | 58 | void pm8x41_reg_write(uint32_t addr, uint8_t val) |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 59 | { |
| 60 | struct pmic_arb_cmd cmd; |
| 61 | struct pmic_arb_param param; |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 62 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 63 | cmd.address = PERIPH_ID(addr); |
| 64 | cmd.offset = REG_OFFSET(addr); |
| 65 | cmd.slave_id = SLAVE_ID(addr); |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 66 | cmd.priority = 0; |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 67 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 68 | param.buffer = &val; |
| 69 | param.size = 1; |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 70 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 71 | pmic_arb_write_cmd(&cmd, ¶m); |
| 72 | } |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 73 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 74 | /* Exported functions */ |
| 75 | |
| 76 | /* Set the boot done flag */ |
| 77 | void pm8x41_set_boot_done() |
| 78 | { |
| 79 | uint8_t val; |
| 80 | |
| 81 | val = REG_READ(SMBB_MISC_BOOT_DONE); |
| 82 | val |= BIT(BOOT_DONE_BIT); |
| 83 | REG_WRITE(SMBB_MISC_BOOT_DONE, val); |
| 84 | } |
| 85 | |
| 86 | /* Configure GPIO */ |
| 87 | int pm8x41_gpio_config(uint8_t gpio, struct pm8x41_gpio *config) |
| 88 | { |
| 89 | uint8_t val; |
| 90 | uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio); |
| 91 | |
| 92 | /* Disable the GPIO */ |
| 93 | val = REG_READ(gpio_base + GPIO_EN_CTL); |
| 94 | val &= ~BIT(PERPH_EN_BIT); |
| 95 | REG_WRITE(gpio_base + GPIO_EN_CTL, val); |
| 96 | |
| 97 | /* Select the mode */ |
| 98 | val = config->function | (config->direction << 4); |
| 99 | REG_WRITE(gpio_base + GPIO_MODE_CTL, val); |
| 100 | |
| 101 | /* Set the right pull */ |
| 102 | val = config->pull; |
| 103 | REG_WRITE(gpio_base + GPIO_DIG_PULL_CTL, val); |
| 104 | |
| 105 | /* Select the VIN */ |
| 106 | val = config->vin_sel; |
| 107 | REG_WRITE(gpio_base + GPIO_DIG_VIN_CTL, val); |
| 108 | |
Siddhartha Agrawal | d61f81e | 2012-12-17 19:20:35 -0800 | [diff] [blame] | 109 | if (config->direction == PM_GPIO_DIR_OUT) { |
| 110 | /* Set the right dig out control */ |
| 111 | val = config->out_strength | (config->output_buffer << 4); |
| 112 | REG_WRITE(gpio_base + GPIO_DIG_OUT_CTL, val); |
| 113 | } |
| 114 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 115 | /* Enable the GPIO */ |
| 116 | val = REG_READ(gpio_base + GPIO_EN_CTL); |
| 117 | val |= BIT(PERPH_EN_BIT); |
| 118 | REG_WRITE(gpio_base + GPIO_EN_CTL, val); |
| 119 | |
Siddhartha Agrawal | d61f81e | 2012-12-17 19:20:35 -0800 | [diff] [blame] | 120 | return 0; |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | /* Reads the status of requested gpio */ |
| 124 | int pm8x41_gpio_get(uint8_t gpio, uint8_t *status) |
| 125 | { |
| 126 | uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio); |
| 127 | |
| 128 | *status = REG_READ(gpio_base + GPIO_STATUS); |
| 129 | |
| 130 | /* Return the value of the GPIO pin */ |
| 131 | *status &= BIT(GPIO_STATUS_VAL_BIT); |
| 132 | |
| 133 | dprintf(SPEW, "GPIO %d status is %d\n", gpio, *status); |
| 134 | |
Siddhartha Agrawal | d61f81e | 2012-12-17 19:20:35 -0800 | [diff] [blame] | 135 | return 0; |
| 136 | } |
| 137 | |
| 138 | /* Write the output value of the requested gpio */ |
| 139 | int pm8x41_gpio_set(uint8_t gpio, uint8_t value) |
| 140 | { |
| 141 | uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio); |
| 142 | uint8_t val; |
| 143 | |
| 144 | /* Set the output value of the gpio */ |
| 145 | val = REG_READ(gpio_base + GPIO_MODE_CTL); |
| 146 | val = (val & ~PM_GPIO_OUTPUT_MASK) | value; |
| 147 | REG_WRITE(gpio_base + GPIO_MODE_CTL, val); |
| 148 | |
| 149 | return 0; |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 150 | } |
| 151 | |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 152 | /* Prepare PON RESIN S2 reset (bite) */ |
| 153 | void pm8x41_resin_s2_reset_enable() |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 154 | { |
| 155 | uint8_t val; |
| 156 | |
| 157 | /* disable s2 reset */ |
| 158 | REG_WRITE(PON_RESIN_N_RESET_S2_CTL, 0x0); |
| 159 | |
Amol Jadi | 7ec52b4 | 2012-08-16 14:12:45 -0700 | [diff] [blame] | 160 | /* Delay needed for disable to kick in. */ |
| 161 | udelay(300); |
| 162 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 163 | /* configure s1 timer to 0 */ |
| 164 | REG_WRITE(PON_RESIN_N_RESET_S1_TIMER, 0x0); |
| 165 | |
| 166 | /* configure s2 timer to 2s */ |
| 167 | REG_WRITE(PON_RESIN_N_RESET_S2_TIMER, PON_RESIN_N_RESET_S2_TIMER_MAX_VALUE); |
| 168 | |
| 169 | /* configure reset type */ |
| 170 | REG_WRITE(PON_RESIN_N_RESET_S2_CTL, S2_RESET_TYPE_WARM); |
| 171 | |
| 172 | val = REG_READ(PON_RESIN_N_RESET_S2_CTL); |
| 173 | |
| 174 | /* enable s2 reset */ |
| 175 | val |= BIT(S2_RESET_EN_BIT); |
| 176 | REG_WRITE(PON_RESIN_N_RESET_S2_CTL, val); |
| 177 | } |
| 178 | |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 179 | /* Disable PON RESIN S2 reset. (bite)*/ |
| 180 | void pm8x41_resin_s2_reset_disable() |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 181 | { |
| 182 | /* disable s2 reset */ |
| 183 | REG_WRITE(PON_RESIN_N_RESET_S2_CTL, 0x0); |
Amol Jadi | 7ec52b4 | 2012-08-16 14:12:45 -0700 | [diff] [blame] | 184 | |
| 185 | /* Delay needed for disable to kick in. */ |
| 186 | udelay(300); |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 187 | } |
| 188 | |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 189 | /* Resin irq status for faulty pmic*/ |
Channagoud Kadabi | 36c19ea | 2013-07-05 16:28:44 -0700 | [diff] [blame] | 190 | uint32_t pm8x41_v2_resin_status() |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 191 | { |
| 192 | uint8_t rt_sts = 0; |
| 193 | |
| 194 | /* Enable S2 reset so we can detect the volume down key press */ |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 195 | pm8x41_resin_s2_reset_enable(); |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 196 | |
| 197 | /* Delay before interrupt triggering. |
| 198 | * See PON_DEBOUNCE_CTL reg. |
| 199 | */ |
| 200 | mdelay(100); |
| 201 | |
| 202 | rt_sts = REG_READ(PON_INT_RT_STS); |
| 203 | |
| 204 | /* Must disable S2 reset otherwise PMIC will reset if key |
| 205 | * is held longer than S2 timer. |
| 206 | */ |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 207 | pm8x41_resin_s2_reset_disable(); |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 208 | |
| 209 | return (rt_sts & BIT(RESIN_BARK_INT_BIT)); |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 210 | } |
Neeti Desai | 120b55d | 2012-08-20 17:15:56 -0700 | [diff] [blame] | 211 | |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 212 | /* Resin pin status */ |
| 213 | uint32_t pm8x41_resin_status() |
| 214 | { |
| 215 | uint8_t rt_sts = 0; |
| 216 | |
| 217 | rt_sts = REG_READ(PON_INT_RT_STS); |
| 218 | |
| 219 | return (rt_sts & BIT(RESIN_ON_INT_BIT)); |
| 220 | } |
| 221 | |
Deepa Dinamani | 3c9865d | 2013-03-08 14:03:19 -0800 | [diff] [blame] | 222 | void pm8x41_v2_reset_configure(uint8_t reset_type) |
Neeti Desai | 120b55d | 2012-08-20 17:15:56 -0700 | [diff] [blame] | 223 | { |
| 224 | uint8_t val; |
| 225 | |
| 226 | /* disable PS_HOLD_RESET */ |
| 227 | REG_WRITE(PON_PS_HOLD_RESET_CTL, 0x0); |
| 228 | |
| 229 | /* Delay needed for disable to kick in. */ |
| 230 | udelay(300); |
| 231 | |
| 232 | /* configure reset type */ |
| 233 | REG_WRITE(PON_PS_HOLD_RESET_CTL, reset_type); |
| 234 | |
| 235 | val = REG_READ(PON_PS_HOLD_RESET_CTL); |
| 236 | |
| 237 | /* enable PS_HOLD_RESET */ |
| 238 | val |= BIT(S2_RESET_EN_BIT); |
| 239 | REG_WRITE(PON_PS_HOLD_RESET_CTL, val); |
| 240 | } |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 241 | |
Deepa Dinamani | 3c9865d | 2013-03-08 14:03:19 -0800 | [diff] [blame] | 242 | void pm8x41_reset_configure(uint8_t reset_type) |
| 243 | { |
| 244 | /* disable PS_HOLD_RESET */ |
| 245 | REG_WRITE(PON_PS_HOLD_RESET_CTL2, 0x0); |
| 246 | |
| 247 | /* Delay needed for disable to kick in. */ |
| 248 | udelay(300); |
| 249 | |
| 250 | /* configure reset type */ |
| 251 | REG_WRITE(PON_PS_HOLD_RESET_CTL, reset_type); |
| 252 | |
| 253 | /* enable PS_HOLD_RESET */ |
| 254 | REG_WRITE(PON_PS_HOLD_RESET_CTL2, BIT(S2_RESET_EN_BIT)); |
| 255 | } |
| 256 | |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 257 | /* |
| 258 | * LDO set voltage, takes ldo name & voltage in UV as input |
| 259 | */ |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 260 | int pm8x41_ldo_set_voltage(struct pm8x41_ldo *ldo, uint32_t voltage) |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 261 | { |
| 262 | uint32_t range = 0; |
| 263 | uint32_t step = 0; |
| 264 | uint32_t mult = 0; |
| 265 | uint32_t val = 0; |
| 266 | uint32_t vmin = 0; |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 267 | |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 268 | if (!ldo) |
| 269 | { |
| 270 | dprintf(CRITICAL, "LDO pointer is invalid: %p\n", ldo); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 271 | return 1; |
| 272 | } |
| 273 | |
| 274 | /* Program Normal power mode */ |
| 275 | val = 0x0; |
| 276 | val = (1 << LDO_NORMAL_PWR_BIT); |
| 277 | REG_WRITE((ldo->base + LDO_POWER_MODE), val); |
| 278 | |
| 279 | /* |
| 280 | * Select range, step & vmin based on input voltage & type of LDO |
| 281 | * LDO can operate in low, mid, high power mode |
| 282 | */ |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 283 | if (ldo->type == PLDO_TYPE) |
| 284 | { |
| 285 | if (voltage < PLDO_UV_MIN) |
| 286 | { |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 287 | range = 2; |
| 288 | step = PLDO_UV_STEP_LOW; |
| 289 | vmin = PLDO_UV_VMIN_LOW; |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 290 | } |
| 291 | else if (voltage < PDLO_UV_MID) |
| 292 | { |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 293 | range = 3; |
| 294 | step = PLDO_UV_STEP_MID; |
| 295 | vmin = PLDO_UV_VMIN_MID; |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 296 | } |
| 297 | else |
| 298 | { |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 299 | range = 4; |
| 300 | step = PLDO_UV_STEP_HIGH; |
| 301 | vmin = PLDO_UV_VMIN_HIGH; |
| 302 | } |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 303 | } |
| 304 | else |
| 305 | { |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 306 | range = 2; |
| 307 | step = NLDO_UV_STEP; |
| 308 | vmin = NLDO_UV_VMIN_LOW; |
| 309 | } |
| 310 | |
| 311 | mult = (voltage - vmin) / step; |
| 312 | |
| 313 | /* Set Range in voltage ctrl register */ |
| 314 | val = 0x0; |
| 315 | val = range << LDO_RANGE_SEL_BIT; |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 316 | REG_WRITE((ldo->base + LDO_RANGE_CTRL), val); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 317 | |
| 318 | /* Set multiplier in voltage ctrl register */ |
| 319 | val = 0x0; |
| 320 | val = mult << LDO_VSET_SEL_BIT; |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 321 | REG_WRITE((ldo->base + LDO_STEP_CTRL), val); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | /* |
| 327 | * Enable or Disable LDO |
| 328 | */ |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 329 | int pm8x41_ldo_control(struct pm8x41_ldo *ldo, uint8_t enable) |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 330 | { |
| 331 | uint32_t val = 0; |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 332 | |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 333 | if (!ldo) |
| 334 | { |
| 335 | dprintf(CRITICAL, "LDO pointer is invalid: %p\n", ldo); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 336 | return 1; |
| 337 | } |
| 338 | |
| 339 | /* Enable LDO */ |
| 340 | if (enable) |
| 341 | val = (1 << LDO_VREG_ENABLE_BIT); |
| 342 | else |
| 343 | val = (0 << LDO_VREG_ENABLE_BIT); |
| 344 | |
Deepa Dinamani | e69ba61 | 2013-06-03 16:10:09 -0700 | [diff] [blame] | 345 | REG_WRITE((ldo->base + LDO_EN_CTL_REG), val); |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 346 | |
| 347 | return 0; |
| 348 | } |
Deepa Dinamani | 7564f2a | 2013-02-05 17:55:51 -0800 | [diff] [blame] | 349 | |
| 350 | uint8_t pm8x41_get_pmic_rev() |
| 351 | { |
| 352 | return REG_READ(REVID_REVISION4); |
| 353 | } |
| 354 | |
sundarajan srinivasan | d0f59e8 | 2013-02-12 19:17:02 -0800 | [diff] [blame] | 355 | uint8_t pm8x41_get_pon_reason() |
| 356 | { |
| 357 | return REG_READ(PON_PON_REASON1); |
| 358 | } |
Deepa Dinamani | c342f12 | 2013-06-12 15:41:31 -0700 | [diff] [blame] | 359 | |
| 360 | void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable) |
| 361 | { |
| 362 | ASSERT(mpp); |
| 363 | |
| 364 | REG_WRITE(mpp->base + MPP_EN_CTL, enable << MPP_EN_CTL_ENABLE_SHIFT); |
| 365 | } |
| 366 | |
| 367 | void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp) |
| 368 | { |
| 369 | ASSERT(mpp); |
| 370 | |
| 371 | REG_WRITE(mpp->base + MPP_DIG_VIN_CTL, mpp->vin); |
| 372 | |
| 373 | REG_WRITE(mpp->base + MPP_MODE_CTL, mpp->mode | (MPP_DIGITAL_OUTPUT << MPP_MODE_CTL_MODE_SHIFT)); |
| 374 | } |
Ameya Thakur | b0a62ab | 2013-06-25 13:43:10 -0700 | [diff] [blame] | 375 | |
| 376 | uint8_t pm8x41_get_is_cold_boot() |
| 377 | { |
| 378 | if (REG_READ(PON_WARMBOOT_STATUS1) || REG_READ(PON_WARMBOOT_STATUS2)) { |
| 379 | dprintf(INFO,"%s: Warm boot\n", __func__); |
| 380 | return 0; |
| 381 | } |
| 382 | dprintf(INFO,"%s: cold boot\n", __func__); |
| 383 | return 1; |
| 384 | } |
Amol Jadi | c3231ff | 2013-07-23 14:35:31 -0700 | [diff] [blame^] | 385 | |
| 386 | /* api to control diff clock */ |
| 387 | void pm8x41_diff_clock_ctrl(uint8_t enable) |
| 388 | { |
| 389 | uint8_t reg; |
| 390 | |
| 391 | reg = REG_READ(DIFF_CLK1_EN_CTL); |
| 392 | |
| 393 | if (enable) |
| 394 | { |
| 395 | reg |= BIT(DIFF_CLK1_EN_BIT); |
| 396 | } |
| 397 | else |
| 398 | { |
| 399 | reg &= ~BIT(DIFF_CLK1_EN_BIT); |
| 400 | } |
| 401 | |
| 402 | REG_WRITE(DIFF_CLK1_EN_CTL, reg); |
| 403 | } |