| Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 1 | /* |
| 2 | * * Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
| 13 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
| 29 | #ifndef __PLATFORM_MSM8X60_CLOCK_H |
| 30 | #define __PLATFORM_MSM8X60_CLOCK_H |
| 31 | |
| 32 | /* MMSS CLK CTR base address */ |
| 33 | #define MSM_MMSS_CLK_CTL 0x04000000 |
| 34 | #define REG_MM(off) (MSM_MMSS_CLK_CTL + (off)) |
| 35 | |
| 36 | #define AHB_NS_REG REG_MM(0x0004) |
| 37 | #define AXI_NS_REG REG_MM(0x0014) |
| 38 | #define MM_PLL0_CONFIG_REG REG_MM(0x0310) |
| 39 | #define MM_PLL0_L_VAL_REG REG_MM(0x0304) |
| 40 | #define MM_PLL0_M_VAL_REG REG_MM(0x0308) |
| 41 | #define MM_PLL0_MODE_REG REG_MM(0x0300) |
| 42 | #define MM_PLL0_N_VAL_REG REG_MM(0x030C) |
| 43 | #define MM_PLL0_STATUS_REG REG_MM(0x0318) |
| 44 | #define MM_PLL1_CONFIG_REG REG_MM(0x032C) |
| 45 | #define MM_PLL1_L_VAL_REG REG_MM(0x0320) |
| 46 | #define MM_PLL1_M_VAL_REG REG_MM(0x0324) |
| 47 | #define MM_PLL1_MODE_REG REG_MM(0x031C) |
| 48 | #define MM_PLL1_N_VAL_REG REG_MM(0x0328) |
| 49 | #define MM_PLL1_STATUS_REG REG_MM(0x0334) |
| 50 | #define MM_PLL2_CONFIG_REG REG_MM(0x0348) |
| 51 | #define MM_PLL2_L_VAL_REG REG_MM(0x033C) |
| 52 | #define MM_PLL2_M_VAL_REG REG_MM(0x0340) |
| 53 | #define MM_PLL2_MODE_REG REG_MM(0x0338) |
| 54 | #define MM_PLL2_N_VAL_REG REG_MM(0x0344) |
| 55 | #define MM_PLL2_STATUS_REG REG_MM(0x0350) |
| 56 | |
| 57 | /* LCD related clock defines */ |
| 58 | #define MMSS_AHB_NS_REG (MSM_MMSS_CLK_CTL + 0x04) |
| 59 | #define MMSS_AHB_EN_REG (MSM_MMSS_CLK_CTL + 0x08) |
| 60 | #define MMSS_AXI_NS_REG (MSM_MMSS_CLK_CTL + 0x14) |
| 61 | #define MMSS_MAXI_EN_REG (MSM_MMSS_CLK_CTL + 0x18) |
| 62 | #define MMSS_MAXI_EN2_REG (MSM_MMSS_CLK_CTL + 0x20) |
| 63 | #define MMSS_SAXI_EN_REG (MSM_MMSS_CLK_CTL + 0x30) |
| 64 | |
| 65 | #define MDP_CC_REG (MSM_MMSS_CLK_CTL + 0xC0) |
| 66 | #define MDP_MD_REG (MSM_MMSS_CLK_CTL + 0xC4) |
| 67 | #define MDP_NS_REG (MSM_MMSS_CLK_CTL + 0xD0) |
| 68 | #define LCD_PIXEL_CC_REG (MSM_MMSS_CLK_CTL + 0xD4) |
| 69 | #define LCD_PIXEL_NS_REG (MSM_MMSS_CLK_CTL + 0xDC) |
| 70 | #define LCD_PIXEL_MD_REG (MSM_MMSS_CLK_CTL + 0xD8) |
| 71 | |
| 72 | /* Configured at 200 MHz */ |
| 73 | #define MDP_NS_VAL 0x3F000008 |
| 74 | #define MDP_MD_VAL 0x000001FB |
| 75 | #define MDP_CC_VAL 0x00000400 |
| 76 | |
| 77 | /* Configured at 53.99 MHz */ |
| 78 | #define PIXEL_NS_VAL 0xFE4F4002 |
| 79 | #define PIXEL_MD_VAL 0x00A9FDA6 |
| 80 | #define PIXEL_CC_VAL 0x00000080 |
| 81 | |
| Shashank Mittal | c648e71 | 2010-10-06 18:37:42 -0700 | [diff] [blame^] | 82 | #define MSM_CLK_CTL_BASE 0x00900000 |
| 83 | #define BB_PLL8_L_VAL_REG (MSM_CLK_CTL_BASE + 0x3144) |
| 84 | #define BB_PLL8_M_VAL_REG (MSM_CLK_CTL_BASE + 0x3148) |
| 85 | #define BB_PLL8_MODE_REG (MSM_CLK_CTL_BASE + 0x3140) |
| 86 | #define BB_PLL8_N_VAL_REG (MSM_CLK_CTL_BASE + 0x314C) |
| 87 | |
| 88 | |
| Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 89 | enum clk_sources { |
| 90 | PLL_0 = 0, |
| 91 | PLL_1, |
| 92 | PLL_2, |
| 93 | PLL_3, |
| 94 | PLL_4, |
| 95 | PLL_5, |
| 96 | PLL_6, |
| 97 | PLL_7, |
| 98 | PLL_8, |
| 99 | MXO, |
| 100 | PXO, |
| 101 | CXO, |
| 102 | NUM_SRC |
| 103 | }; |
| 104 | |
| 105 | #endif |