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Bikas Gurungd1aa5902010-10-01 23:45:33 -07001/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __UART_DM_H__
30#define __UART_DM_H__
31
32#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
33 ((value << (32 - end_pos))\
34 >> (32 - (end_pos - start_pos)))
35
36/* GPIO pins - 2 wire using UART2 */
37#define MSM_BOOT_UART_DM_RX_GPIO 117
38#define MSM_BOOT_UART_DM_TX_GPIO 118
39
40
41/* UART Parity Mode */
42enum MSM_BOOT_UART_DM_PARITY_MODE
43{
44 MSM_BOOT_UART_DM_NO_PARITY,
45 MSM_BOOT_UART_DM_ODD_PARITY,
46 MSM_BOOT_UART_DM_EVEN_PARITY,
47 MSM_BOOT_UART_DM_SPACE_PARITY
48};
49
50/* UART Stop Bit Length */
51enum MSM_BOOT_UART_DM_STOP_BIT_LEN
52{
53 MSM_BOOT_UART_DM_SBL_9_16,
54 MSM_BOOT_UART_DM_SBL_1,
55 MSM_BOOT_UART_DM_SBL_1_9_16,
56 MSM_BOOT_UART_DM_SBL_2
57};
58
59/* UART Bits per Char */
60enum MSM_BOOT_UART_DM_BITS_PER_CHAR
61{
62 MSM_BOOT_UART_DM_5_BPS,
63 MSM_BOOT_UART_DM_6_BPS,
64 MSM_BOOT_UART_DM_7_BPS,
65 MSM_BOOT_UART_DM_8_BPS
66};
67
68/* 8-N-1 Configuration */
69#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
70 (MSM_BOOT_UART_DM_SBL_1 << 2) | \
71 (MSM_BOOT_UART_DM_8_BPS << 4))
72
73/* CSR is used to further divide fundamental frequency.
74 * Using EE we are dividing gsbi_uart_clk by 2 so as to get
75 * 115.2k bit rate for fundamental frequency of 3.6864 MHz */
76#define MSM_BOOT_UART_DM_RX_TX_BIT_RATE 0xEE
77
78/*
79 * Define Macros for GSBI and UARTDM Registers
80 */
81
82/* Clocks */
83
84#define MSM_BOOT_CLK_CTL_BASE 0x00900000
85
86#define MSM_BOOT_PLL_ENABLE_SC0 (MSM_BOOT_CLK_CTL_BASE + 0x34C0)
87
88#define MSM_BOOT_PLL8_STATUS (MSM_BOOT_CLK_CTL_BASE + 0x3158)
89
90#define MSM_BOOT_GSBIn_HCLK_CTL(n) (MSM_BOOT_CLK_CTL_BASE + 0x29A0 +\
91 ( 32 * n ))
92
93#define MSM_BOOT_GSBIn_UART_APPS_MD(n) (MSM_BOOT_CLK_CTL_BASE + 0x29B0 +\
94 ( 32 * n))
95
96#define MSM_BOOT_GSBIn_UART_APPS_NS(n) (MSM_BOOT_CLK_CTL_BASE + 0x29B4 +\
97 (32 * n))
98
99#define MSM_BOOT_UART_DM_GSBI_HCLK_CTL MSM_BOOT_GSBIn_HCLK_CTL(12)
100
101#define MSM_BOOT_UART_DM_APPS_MD MSM_BOOT_GSBIn_UART_APPS_MD(12)
102
103#define MSM_BOOT_UART_DM_APPS_NS MSM_BOOT_GSBIn_UART_APPS_NS(12)
104
105
Amol Jadicd43ea02011-02-15 20:56:04 -0800106/* Specify GSBI for UART */
Amol Jadica4f4c92011-01-13 20:19:34 -0800107#ifdef PLATFORM_MSM8960
Amol Jadicd43ea02011-02-15 20:56:04 -0800108 #if PLATFORM_MSM8960_RUMI3
109 /* GSBI5 */
110 #define MSM_BOOT_GSBI_BASE 0x16400000
111 #else
112 /* GSBI2 */
113 #define MSM_BOOT_GSBI_BASE 0x16100000
114 #endif
Amol Jadica4f4c92011-01-13 20:19:34 -0800115#else
Amol Jadicd43ea02011-02-15 20:56:04 -0800116 /* GSBI12 */
Amol Jadica4f4c92011-01-13 20:19:34 -0800117 #define MSM_BOOT_GSBI_BASE 0x19C00000
118#endif
Bikas Gurungd1aa5902010-10-01 23:45:33 -0700119
120#define MSM_BOOT_GSBI_CTRL_REG MSM_BOOT_GSBI_BASE
121
122#define MSM_BOOT_UART_DM_BASE (MSM_BOOT_GSBI_BASE+0x40000)
123
124#define MSM_BOOT_UART_DM_REG(offset) (MSM_BOOT_UART_DM_BASE + offset)
125
126/* UART Operational Mode Register */
127#define MSM_BOOT_UART_DM_MR1 MSM_BOOT_UART_DM_REG(0x0000)
128#define MSM_BOOT_UART_DM_MR2 MSM_BOOT_UART_DM_REG(0x0004)
129#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
130#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
131
132/* UART Clock Selection Register */
133#define MSM_BOOT_UART_DM_CSR MSM_BOOT_UART_DM_REG(0x0008)
134
135/* UART DM TX FIFO Registers - 4 */
136#define MSM_BOOT_UART_DM_TF(x) MSM_BOOT_UART_DM_REG(0x0070+(4*x))
137
138/* UART Command Register */
139#define MSM_BOOT_UART_DM_CR MSM_BOOT_UART_DM_REG(0x0010)
140#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
141#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
142#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
143#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
144
145/* UART Channel Command */
146#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
147#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 )
148#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | \
149 MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
150#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
151#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
152#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
153#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
154#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
155#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
156#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
157#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
158#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
159#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
160#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
161#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
162#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
163#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
164#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
165#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
166#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
167#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
168
169/*UART General Command */
170#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
171
172#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
173#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
174#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
175#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
176#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
177#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
178#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
179
180/* UART Interrupt Mask Register */
181#define MSM_BOOT_UART_DM_IMR MSM_BOOT_UART_DM_REG(0x0014)
182#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
183#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
184#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
185#define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
186#define MSM_BOOT_UART_DM_RXLEV (1 << 4)
187#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
188#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
189#define MSM_BOOT_UART_DM_TX_READY (1 << 7)
190#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
191#define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
192#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
193#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
194#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
195
196#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
197 MSM_BOOT_UART_DM_TXLEV | \
198 MSM_BOOT_UART_DM_RXLEV | \
199 MSM_BOOT_UART_DM_RXSTALE)
200
201/* UART Interrupt Programming Register */
202#define MSM_BOOT_UART_DM_IPR MSM_BOOT_UART_DM_REG(0x0018)
203#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
204#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
205
206/* UART Transmit/Receive FIFO Watermark Register */
207#define MSM_BOOT_UART_DM_TFWR MSM_BOOT_UART_DM_REG(0x001C)
208/* Interrupt is generated when FIFO level is less than or equal to this value */
209#define MSM_BOOT_UART_DM_TFW_VALUE 0
210
211#define MSM_BOOT_UART_DM_RFWR MSM_BOOT_UART_DM_REG(0x0020)
212/*Interrupt generated when no of words in RX FIFO is greater than this value */
213#define MSM_BOOT_UART_DM_RFW_VALUE 0
214
215/* UART Hunt Character Register */
216#define MSM_BOOT_UART_DM_HCR MSM_BOOT_UART_DM_REG(0x0024)
217
218/* Used for RX transfer initialization */
219#define MSM_BOOT_UART_DM_DMRX MSM_BOOT_UART_DM_REG(0x0034)
220
221/* Default DMRX value - any value bigger than FIFO size would be fine */
222#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
223
224/* Register to enable IRDA function */
225#define MSM_BOOT_UART_DM_IRDA MSM_BOOT_UART_DM_REG(0x0038)
226
227/* UART Data Mover Enable Register */
228#define MSM_BOOT_UART_DM_DMEN MSM_BOOT_UART_DM_REG(0x003C)
229
230/* Number of characters for Transmission */
231#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX MSM_BOOT_UART_DM_REG(0x0040)
232
233/* UART RX FIFO Base Address */
234#define MSM_BOOT_UART_DM_BADR MSM_BOOT_UART_DM_REG(0x0044)
235
236/* UART Status Register */
237#define MSM_BOOT_UART_DM_SR MSM_BOOT_UART_DM_REG(0x0008)
238#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
239#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
240#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
241#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
242#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
243#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
244#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
245#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
246#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
247
248/* UART Receive FIFO Registers - 4 in numbers */
249#define MSM_BOOT_UART_DM_RF(x) MSM_BOOT_UART_DM_REG(0x0070+(4*x))
250
251/* UART Masked Interrupt Status Register */
252#define MSM_BOOT_UART_DM_MISR MSM_BOOT_UART_DM_REG(0x0010)
253
254/* UART Interrupt Status Register */
255#define MSM_BOOT_UART_DM_ISR MSM_BOOT_UART_DM_REG(0x0014)
256
257/* Number of characters received since the end of last RX transfer */
258#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP MSM_BOOT_UART_DM_REG(0x0038)
259
260/* UART TX FIFO Status Register */
261#define MSM_BOOT_UART_DM_TXFS MSM_BOOT_UART_DM_REG(0x004C)
262#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
263#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
264#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
265#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
266
267/* UART RX FIFO Status Register */
268#define MSM_BOOT_UART_DM_RXFS MSM_BOOT_UART_DM_REG(0x0050)
269#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
270#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
271#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
272#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
273
274
275
276/* Macros for Common Errors */
277#define MSM_BOOT_UART_DM_E_SUCCESS 0
278#define MSM_BOOT_UART_DM_E_FAILURE 1
279#define MSM_BOOT_UART_DM_E_TIMEOUT 2
280#define MSM_BOOT_UART_DM_E_INVAL 3
281#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
282#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
283
284#endif /* __UART_DM_H__*/