Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 2 | |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
Channagoud Kadabi | 4517eb1 | 2015-09-02 18:43:13 -0700 | [diff] [blame] | 28 | #include <arch/defines.h> |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 29 | #include <platform/iomap.h> |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 30 | #include <qusb2_phy.h> |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 31 | #include <reg.h> |
| 32 | #include <bits.h> |
| 33 | #include <debug.h> |
Veera Sundaram Sankaran | 0018151 | 2014-12-09 11:23:39 -0800 | [diff] [blame] | 34 | #include <qtimer.h> |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 35 | #include <platform.h> |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 36 | |
Channagoud Kadabi | 12b9693 | 2014-09-23 15:18:11 -0700 | [diff] [blame] | 37 | __WEAK int platform_is_msm8994() |
| 38 | { |
| 39 | return 0; |
| 40 | } |
| 41 | |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 42 | __WEAK int platform_is_msm8996() |
| 43 | { |
| 44 | return 0; |
| 45 | } |
| 46 | |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 47 | __WEAK int platform_is_mdmcalifornium() |
| 48 | { |
| 49 | return 0; |
| 50 | } |
| 51 | |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 52 | void qusb2_phy_reset(void) |
| 53 | { |
| 54 | uint32_t val; |
Channagoud Kadabi | d1e2cc2 | 2015-08-13 12:48:37 -0700 | [diff] [blame] | 55 | /* Default tune value */ |
| 56 | uint8_t tune2 = 0xB3; |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 57 | int retry = 100; |
| 58 | int se_clock = 1; |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 59 | |
Channagoud Kadabi | d33824f | 2015-09-24 15:17:53 -0700 | [diff] [blame] | 60 | /* Disable the ref clock before phy reset */ |
| 61 | #if GCC_RX2_USB2_CLKREF_EN |
| 62 | writel((readl(GCC_RX2_USB2_CLKREF_EN) & ~0x1), GCC_RX2_USB2_CLKREF_EN); |
| 63 | dmb(); |
| 64 | #endif |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 65 | /* Block Reset */ |
| 66 | val = readl(GCC_QUSB2_PHY_BCR) | BIT(0); |
| 67 | writel(val, GCC_QUSB2_PHY_BCR); |
| 68 | udelay(10); |
| 69 | writel(val & ~BIT(0), GCC_QUSB2_PHY_BCR); |
| 70 | |
Channagoud Kadabi | 4517eb1 | 2015-09-02 18:43:13 -0700 | [diff] [blame] | 71 | /* configure the abh2 phy to wait state */ |
| 72 | writel(0x11, PERIPH_SS_AHB2PHY_TOP_CFG); |
| 73 | dmb(); |
| 74 | |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 75 | /* set CLAMP_N_EN and stay with disabled USB PHY */ |
| 76 | writel(0x23, QUSB2PHY_PORT_POWERDOWN); |
| 77 | |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 78 | if (platform_is_msm8996() || platform_is_mdmcalifornium()) |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 79 | { |
| 80 | writel(0xF8, QUSB2PHY_PORT_TUNE1); |
Channagoud Kadabi | d1e2cc2 | 2015-08-13 12:48:37 -0700 | [diff] [blame] | 81 | /* Upper nibble of tune2 register should be updated based on the fuse value. |
| 82 | * Read the bits 21..24 from fuse and update the upper nibble with this value |
| 83 | */ |
| 84 | #if QFPROM_CORR_CALIB_ROW12_MSB |
| 85 | uint8_t fuse_val = (readl(QFPROM_CORR_CALIB_ROW12_MSB) & 0x1E00000) >> 21; |
| 86 | /* If fuse value is non zero then update the upper nibble with the fuse value |
| 87 | * otherwise use the default value |
| 88 | */ |
| 89 | if (fuse_val) |
| 90 | tune2 = (tune2 & 0x0f) | (fuse_val << 4); |
| 91 | #endif |
| 92 | writel(tune2, QUSB2PHY_PORT_TUNE2); |
Channagoud Kadabi | f0d9ef0 | 2015-09-24 14:52:02 -0700 | [diff] [blame] | 93 | writel(0x83, QUSB2PHY_PORT_TUNE3); |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 94 | writel(0xC0, QUSB2PHY_PORT_TUNE4); |
| 95 | writel(0x30, QUSB2PHY_PLL_TUNE); |
| 96 | writel(0x79, QUSB2PHY_PLL_USER_CTL1); |
| 97 | writel(0x21, QUSB2PHY_PLL_USER_CTL2); |
| 98 | writel(0x14, QUSB2PHY_PORT_TEST2); |
Channagoud Kadabi | f0d9ef0 | 2015-09-24 14:52:02 -0700 | [diff] [blame] | 99 | writel(0x9F, QUSB2PHY_PLL_AUTOPGM_CTL1); |
| 100 | writel(0x00, QUSB2PHY_PLL_PWR_CTL); |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 101 | } |
| 102 | else |
| 103 | { |
| 104 | /* Set HS impedance to 42ohms */ |
| 105 | writel(0xA0, QUSB2PHY_PORT_TUNE1); |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 106 | |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 107 | /* Set TX current to 19mA, TX SR and TX bias current to 1, 1 */ |
| 108 | writel(0xA5, QUSB2PHY_PORT_TUNE2); |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 109 | |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 110 | /* Increase autocalibration bias circuit settling time |
| 111 | * and enable utocalibration */ |
| 112 | writel(0x81, QUSB2PHY_PORT_TUNE3); |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 113 | |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 114 | writel(0x85, QUSB2PHY_PORT_TUNE4); |
| 115 | } |
| 116 | |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 117 | /* Enable ULPI mode */ |
Channagoud Kadabi | 12b9693 | 2014-09-23 15:18:11 -0700 | [diff] [blame] | 118 | if (platform_is_msm8994()) |
| 119 | writel(0x0, QUSB2PHY_PORT_UTMI_CTRL2); |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 120 | /* set CLAMP_N_EN and USB PHY is enabled*/ |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 121 | writel(0x22, QUSB2PHY_PORT_POWERDOWN); |
Channagoud Kadabi | e80224a | 2015-10-15 21:55:07 -0700 | [diff] [blame] | 122 | udelay(150); |
Channagoud Kadabi | d33824f | 2015-09-24 15:17:53 -0700 | [diff] [blame] | 123 | |
Channagoud Kadabi | e80224a | 2015-10-15 21:55:07 -0700 | [diff] [blame] | 124 | /* TCSR register bit 0 indicates whether single ended clock |
| 125 | * or differential clock configuration is enabled. Based on the |
| 126 | * configuration set the PLL_TEST register. |
| 127 | */ |
| 128 | #if TCSR_PHY_CLK_SCHEME_SEL |
| 129 | se_clock = readl(TCSR_PHY_CLK_SCHEME_SEL) & 0x1; |
Channagoud Kadabi | d33824f | 2015-09-24 15:17:53 -0700 | [diff] [blame] | 130 | #endif |
Channagoud Kadabi | e80224a | 2015-10-15 21:55:07 -0700 | [diff] [blame] | 131 | /* By default consider differential clock configuration and if TCSR |
| 132 | * register bit 0 is not set then use single ended setting |
| 133 | */ |
| 134 | if (se_clock) |
| 135 | { |
| 136 | writel(0x80, QUSB2PHY_PLL_TEST); |
| 137 | } |
| 138 | else |
| 139 | { |
| 140 | /* turn the ref clock on for differential clocks */ |
| 141 | #if GCC_RX2_USB2_CLKREF_EN |
| 142 | writel((readl(GCC_RX2_USB2_CLKREF_EN) | 0x1), GCC_RX2_USB2_CLKREF_EN); |
| 143 | dmb(); |
| 144 | #endif |
| 145 | } |
| 146 | udelay(100); |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 147 | |
| 148 | /* Check PLL status */ |
| 149 | while (!(readl(QUSB2PHY_PLL_STATUS) & QUSB2PHY_PLL_LOCK)) |
| 150 | { |
| 151 | retry--; |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 152 | if (!retry) |
| 153 | { |
| 154 | dprintf(CRITICAL, "QUSB2PHY failed to lock: %d", readl(QUSB2PHY_PLL_STATUS)); |
| 155 | break; |
| 156 | } |
Channagoud Kadabi | e80224a | 2015-10-15 21:55:07 -0700 | [diff] [blame] | 157 | /* As per recommendation form hw team wait for 5 us before reading the status */ |
| 158 | udelay(5); |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 159 | } |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 160 | } |