blob: 072330b9707c8043496f2c53a7036bd0dfe25a39 [file] [log] [blame]
Amol Jadif3d5a892013-07-23 16:09:44 -07001/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/* This file implements the UDC (usb device controller) layer to be used with
30 * the new dwc controller.
31 * It exposes APIs to initialize UDC (and thus usb) and perform data transfer
32 * over usb.
33 */
34
35#include <reg.h>
36#include <debug.h>
37#include <string.h>
38#include <malloc.h>
39#include <stdlib.h>
40#include <arch/defines.h>
41#include <dev/udc.h>
42#include <platform/iomap.h>
43#include <usb30_dwc.h>
44#include <usb30_wrapper.h>
45#include <usb30_udc.h>
Amol Jadi5418da32013-10-11 14:14:47 -070046#include <smem.h>
47#include <board.h>
48#include <platform/timer.h>
Amol Jadif3d5a892013-07-23 16:09:44 -070049
50//#define DEBUG_USB
51
52#ifdef DEBUG_USB
53#define DBG(...) dprintf(ALWAYS, __VA_ARGS__)
54#else
55#define DBG(...)
56#endif
57
58#define ERR(...) dprintf(ALWAYS, __VA_ARGS__)
59
60/* control data transfer is max 512 bytes */
61#define UDC_CONTROL_RX_BUF_SIZE 512
62#define UDC_CONTROL_TX_BUF_SIZE 512
63
64/* Buffer used by dwc driver to process events.
65 * Must be multiple of 4: snps 6.2.7.2.
66 */
67#define UDC_DWC_EVENT_BUF_SIZE 4096
68
69/* macro to parse setup request */
70#define SETUP(type,request) (((type) << 8) | (request))
71
72/* macro to generate bit representation of an EP */
73#define EPT_TX(n) (1 << ((n) + 16))
74#define EPT_RX(n) (1 << (n))
75
76/* Local functions */
77static struct udc_descriptor *udc_descriptor_alloc(uint32_t type,
78 uint32_t num,
79 uint32_t len,
80 udc_desc_spec_t spec);
81static uint8_t udc_string_desc_alloc(udc_t *udc, const char *str);
82
83static void udc_descriptor_register(udc_t *udc, struct udc_descriptor *desc);
84static void udc_register_language_desc(udc_t *udc);
85static void udc_register_bos_desc(udc_t *udc);
86static void udc_register_device_desc_usb_20(udc_t *udc, struct udc_device *dev_info);
87static void udc_register_device_desc_usb_30(udc_t *udc, struct udc_device *dev_info);
88static void udc_register_config_desc_usb20(udc_t *udc, struct udc_gadget *gadget);
89static void udc_register_config_desc_usb30(udc_t *udc, struct udc_gadget *gadget);
90
91static void udc_ept_desc_fill(struct udc_endpoint *ept, uint8_t *data);
92static void udc_ept_comp_desc_fill(struct udc_endpoint *ept, uint8_t *data);
93
94static void udc_dwc_notify(void *context, dwc_notify_event_t event);
95static int udc_handle_setup(void *context, uint8_t *data);
96
97/* TODO: This must be the only global var in this file, for now.
98 * Ideally, all APIs should be sending
99 * this to us and this ptr should be kept outside of this code.
100 * This needs change in the common udc APIs and thus keeping it here until that
101 * is done.
102 */
103static udc_t *udc_dev = NULL;
104
105
Amol Jadi5418da32013-10-11 14:14:47 -0700106__WEAK int platform_is_8974()
Amol Jadif3d5a892013-07-23 16:09:44 -0700107{
Amol Jadi5418da32013-10-11 14:14:47 -0700108 return 0;
Amol Jadif3d5a892013-07-23 16:09:44 -0700109}
110
Amol Jadi5418da32013-10-11 14:14:47 -0700111__WEAK int platform_is_8974Pro()
Amol Jadif3d5a892013-07-23 16:09:44 -0700112{
Amol Jadi5418da32013-10-11 14:14:47 -0700113 return 0;
114}
115
Channagoud Kadabi16b23bc2013-10-17 19:00:10 -0700116__WEAK int platform_is_8x62()
117{
118 return 0;
119}
120
Amol Jadi5418da32013-10-11 14:14:47 -0700121static void phy_mux_configure(void)
122{
123 /* configuring of hs phy mux is different for some platforms. */
124 target_usb_phy_mux_configure();
125}
126
127static void phy_reset(usb_wrapper_dev_t *wrapper)
128{
129 /* phy reset is different for some platforms. */
Channagoud Kadabi16b23bc2013-10-17 19:00:10 -0700130 if (platform_is_8974() || platform_is_8974Pro() || platform_is_8x62())
Amol Jadi5418da32013-10-11 14:14:47 -0700131 {
132 /* SS PHY */
133 usb_wrapper_ss_phy_reset(wrapper);
134
135 /* For 8974: hs phy is reset as part of soft reset.
136 * No need for explicit reset.
137 */
138 }
139 else if (board_platform_id() == APQ8084)
140 {
141 target_usb_phy_reset();
Channagoud Kadabi685337e2013-11-13 13:53:24 -0800142
143 /* On some CDPs PHY_COMMON reset does not set
144 * reset values in the phy_ctrl_common register.
145 * Due to this USB does not get enumerated in fastboot
146 * Force write the reset value
147 */
148 usb_wrapper_hs_phy_ctrl_force_write(wrapper);
Amol Jadi5418da32013-10-11 14:14:47 -0700149 }
150}
151
152/* Initialize HS phy */
153void hs_phy_init(udc_t *dev)
154{
155 /* only for 8974 */
Channagoud Kadabi16b23bc2013-10-17 19:00:10 -0700156 if (platform_is_8974() || platform_is_8974Pro() || platform_is_8x62())
Amol Jadi5418da32013-10-11 14:14:47 -0700157 {
158 /* 5.a, 5.b */
159 usb_wrapper_hs_phy_init(dev->wrapper_dev);
160
161 /* 5.d */
162 dwc_usb2_phy_soft_reset(dev->dwc);
163 }
164}
165
166/* vbus override */
167void vbus_override(udc_t *dev)
168{
169 /* when vbus signal is not available directly to the controller,
170 * simulate vbus presense.
171 */
172 if (board_platform_id() == APQ8084)
173 {
174 usb_wrapper_vbus_override(dev->wrapper_dev);
175 }
Amol Jadif3d5a892013-07-23 16:09:44 -0700176}
177
178
179/* Initialize usb wrapper and dwc h/w blocks. */
180static void usb30_init(void)
181{
182 usb_wrapper_dev_t* wrapper;
183 usb_wrapper_config_t wrapper_config;
184
185 dwc_dev_t *dwc;
186 dwc_config_t dwc_config;
187
188 /* initialize the usb wrapper h/w block */
189 wrapper_config.qscratch_base = (void*) MSM_USB30_QSCRATCH_BASE;
190
191 wrapper = usb_wrapper_init(&wrapper_config);
192 ASSERT(wrapper);
193
194 /* save the wrapper ptr */
195 udc_dev->wrapper_dev = wrapper;
196
197 /* initialize the dwc device block */
198 dwc_config.base = (void*) MSM_USB30_BASE;
199
200 /* buffer must be aligned to buf size. snps 8.2.2 */
201 dwc_config.event_buf = memalign(lcm(CACHE_LINE, UDC_DWC_EVENT_BUF_SIZE),
202 ROUNDUP(UDC_DWC_EVENT_BUF_SIZE, CACHE_LINE));
203 ASSERT(dwc_config.event_buf);
204
205 dwc_config.event_buf_size = UDC_DWC_EVENT_BUF_SIZE;
206
207 /* notify handler */
208 dwc_config.notify_context = udc_dev;
209 dwc_config.notify = udc_dwc_notify;
210
211 /* setup handler */
212 dwc_config.setup_context = udc_dev;
213 dwc_config.setup_handler = udc_handle_setup;
214
215 dwc = dwc_init(&dwc_config);
216 ASSERT(dwc);
217
218 /* save the dwc dev ptr */
219 udc_dev->dwc = dwc;
220
221
222 /* USB3.0 core and phy initialization as described in HPG */
223
224 /* section 4.4.1 Control sequence */
225 usb_wrapper_dbm_mode(wrapper, DBM_MODE_BYPASS);
226
227 /* section 4.4.1: use config 0 - all of RAM1 */
228 usb_wrapper_ram_configure(wrapper);
229
230 /* section 4.4.2: Initialization and configuration sequences */
231
232 /* 1. UTMI Mux configuration */
Amol Jadi5418da32013-10-11 14:14:47 -0700233 phy_mux_configure();
Amol Jadif3d5a892013-07-23 16:09:44 -0700234
235 /* 2. Put controller in reset */
236 dwc_reset(dwc, 1);
237
Amol Jadi5418da32013-10-11 14:14:47 -0700238 /* Steps 3 - 7 must be done while dwc is in reset condition */
Amol Jadif3d5a892013-07-23 16:09:44 -0700239
Amol Jadi5418da32013-10-11 14:14:47 -0700240 /* 3. Reset PHY */
241 phy_reset(wrapper);
Amol Jadif3d5a892013-07-23 16:09:44 -0700242
243 /* 4. SS phy config */
244 usb_wrapper_ss_phy_configure(wrapper);
245
246 /* 5. HS phy init */
247 usb_wrapper_hs_phy_init(wrapper);
248
Amol Jadif3d5a892013-07-23 16:09:44 -0700249 /* 6. hs phy config */
250 usb_wrapper_hs_phy_configure(wrapper);
251
252 /* 7. Reset PHY digital interface */
253 dwc_phy_digital_reset(dwc);
254
255 /* 8. Bring dwc controller out of reset */
256 dwc_reset(dwc, 0);
257
258 /* 9. */
259 usb_wrapper_ss_phy_electrical_config(wrapper);
260
261 /* 10. */
262 usb_wrapper_workaround_10(wrapper);
263
264 /* 11. */
265 usb_wrapper_workaround_11(wrapper);
266
267 /* 12. */
268 dwc_ss_phy_workaround_12(dwc);
269
270 /* 13. */
271 usb_wrapper_workaround_13(wrapper);
272
273 /* 14. needed only for host mode. ignored. */
274
Amol Jadi5418da32013-10-11 14:14:47 -0700275 /* If the target does not support vbus detection in controller,
276 * simulate vbus presence.
277 */
278 vbus_override(udc_dev);
279
Amol Jadif3d5a892013-07-23 16:09:44 -0700280 /* 15 - 20 */
281 dwc_device_init(dwc);
282}
283
284/* udc_init: creates and registers various usb descriptor */
Amol Jadi151f2a52013-10-07 12:39:11 -0700285int usb30_udc_init(struct udc_device *dev_info)
Amol Jadif3d5a892013-07-23 16:09:44 -0700286{
287 /* create and initialize udc instance */
288 udc_dev = (udc_t*) malloc(sizeof(udc_t));
289 ASSERT(udc_dev);
290
291 /* initialize everything to 0 */
292 memset(udc_dev, 0 , sizeof(udc_t));
293
294 /* malloc control data buffers */
295 udc_dev->ctrl_rx_buf = memalign(CACHE_LINE, ROUNDUP(UDC_CONTROL_RX_BUF_SIZE, CACHE_LINE));
296 ASSERT(udc_dev->ctrl_rx_buf);
297
298 udc_dev->ctrl_tx_buf = memalign(CACHE_LINE, ROUNDUP(UDC_CONTROL_TX_BUF_SIZE, CACHE_LINE));
299 ASSERT(udc_dev->ctrl_tx_buf);
300
301 /* initialize string id */
302 udc_dev->next_string_id = 1;
303
304 /* Initialize ept data */
305 /* alloc table to assume EP0 In/OUT are already allocated.*/
306 udc_dev->ept_alloc_table = EPT_TX(0) | EPT_RX(0);
307 udc_dev->ept_list = NULL;
308
309 usb30_init();
310
311 /* register descriptors */
312 udc_register_language_desc(udc_dev);
313 udc_register_device_desc_usb_20(udc_dev, dev_info);
314 udc_register_device_desc_usb_30(udc_dev, dev_info);
315 udc_register_bos_desc(udc_dev);
316
317 return 0;
318}
319
320/* application registers its gadget by calling this func.
321 * gadget == interface descriptor
322 */
Amol Jadi151f2a52013-10-07 12:39:11 -0700323int usb30_udc_register_gadget(struct udc_gadget *gadget)
Amol Jadif3d5a892013-07-23 16:09:44 -0700324{
325 ASSERT(gadget);
326
327 /* check if already registered */
328 if (udc_dev->gadget)
329 {
330 ERR("\nonly one gadget supported\n");
331 return -1;
332 }
333
334 /* create our configuration descriptors based on this gadget data */
335 udc_register_config_desc_usb20(udc_dev, gadget);
336 udc_register_config_desc_usb30(udc_dev, gadget);
337
338 /* save the gadget */
339 udc_dev->gadget = gadget;
340
341 return 0;
342}
343
344/* udc_start: */
Amol Jadi151f2a52013-10-07 12:39:11 -0700345int usb30_udc_start(void)
Amol Jadif3d5a892013-07-23 16:09:44 -0700346{
347 /* 19. run
348 * enable device to receive SOF packets and
349 * respond to control transfers on EP0 and generate events.
350 */
351 dwc_device_run(udc_dev->dwc, 1);
352
353 return 0;
354}
355
356/* Control data rx callback. Called by DWC layer when it receives control
357 * data from host.
358 */
359void udc_control_rx_callback(void *context, unsigned actual, int status)
360{
361 udc_t *udc = (udc_t *) context;
362
363 /* Force reload of buffer update by controller from memory */
364 arch_invalidate_cache_range((addr_t) udc->ctrl_rx_buf, actual);
365
366 /* TODO: for now, there is only one 3-stage write during 3.0 enumeration
367 * (SET_SEL), which causes this callback. Ideally, set_periodic() must
368 * be based on which control rx just happened.
369 * Also, the value of 0x65 should depend on the data received for SET_SEL.
370 * For now, this value works just fine.
371 */
372 dwc_device_set_periodic_param(udc->dwc, 0x65);
373}
374
375/* lookup request name for debug purposes */
376static const char *reqname(uint32_t r)
377{
378 switch (r) {
379 case GET_STATUS:
380 return "GET_STATUS";
381 case CLEAR_FEATURE:
382 return "CLEAR_FEATURE";
383 case SET_FEATURE:
384 return "SET_FEATURE";
385 case SET_ADDRESS:
386 return "SET_ADDRESS";
387 case GET_DESCRIPTOR:
388 return "GET_DESCRIPTOR";
389 case SET_DESCRIPTOR:
390 return "SET_DESCRIPTOR";
391 case GET_CONFIGURATION:
392 return "GET_CONFIGURATION";
393 case SET_CONFIGURATION:
394 return "SET_CONFIGURATION";
395 case GET_INTERFACE:
396 return "GET_INTERFACE";
397 case SET_INTERFACE:
398 return "SET_INTERFACE";
399 case SET_SEL:
400 return "SET_SEL";
401 default:
402 return "*UNKNOWN*";
403 }
404}
405
406/* callback function called by DWC layer when a setup packed is received.
407 * the return value tells dwc layer whether this setup pkt results in
408 * a 2-stage or a 3-stage control transfer or stall.
409 */
410static int udc_handle_setup(void *context, uint8_t *data)
411{
412 udc_t *udc = (udc_t *) context;
413 uint32_t len;
414
415 ASSERT(udc);
416
417 dwc_dev_t *dwc = udc->dwc;
418 ASSERT(dwc);
419
420 struct setup_packet s = *((struct setup_packet*) data);
421
422 DBG("\n SETUP request: \n type = 0x%x \n request = 0x%x \n value = 0x%x"
423 " \n index = 0x%x \n length = 0x%x\n",
424 s.type, s.request, s.value, s.index, s.length);
425
426 switch (SETUP(s.type, s.request))
427 {
428 case SETUP(DEVICE_READ, GET_STATUS):
429 {
430 DBG("\n DEVICE_READ : GET_STATUS: value = %d index = %d"
431 " length = %d", s.value, s.index, s.length);
432
433 if (s.length == 2) {
434
435 uint16_t zero = 0;
436 len = 2;
437
438 /* copy to tx buffer */
439 memcpy(udc->ctrl_tx_buf, &zero, len);
440
441 /* flush buffer to main memory before queueing the request */
442 arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len);
443
444 dwc_transfer_request(udc->dwc,
445 0,
446 DWC_EP_DIRECTION_IN,
447 udc->ctrl_tx_buf,
448 len,
449 NULL,
450 NULL);
451
452 return DWC_SETUP_3_STAGE;
453 }
454 }
455 break;
456 case SETUP(DEVICE_READ, GET_DESCRIPTOR):
457 {
458 DBG("\n DEVICE_READ : GET_DESCRIPTOR: value = %d", s.value);
459
460 /* setup usb ep0-IN to send our device descriptor */
461 struct udc_descriptor *desc;
462
463 for (desc = udc->desc_list; desc; desc = desc->next)
464 {
465 /* tag must match the value AND
466 * if speed is SS, desc must comply with 30 spec OR
467 * if speed is not SS, desc must comply with 20 spec.
468 */
469 if ((desc->tag == s.value) &&
470 (((udc->speed == UDC_SPEED_SS) && (desc->spec & UDC_DESC_SPEC_30)) ||
471 ((udc->speed != UDC_SPEED_SS) && (desc->spec & UDC_DESC_SPEC_20)))
472 )
473 {
474 if (desc->len > s.length)
475 len = s.length;
476 else
477 len = desc->len;
478
479 /* copy to tx buffer */
480 memcpy(udc->ctrl_tx_buf, desc->data, len);
481
482 /* flush buffer to main memory before queueing the request */
483 arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len);
484
485 dwc_transfer_request(udc->dwc,
486 0,
487 DWC_EP_DIRECTION_IN,
488 udc->ctrl_tx_buf,
489 len,
490 NULL,
491 NULL);
492
493 return DWC_SETUP_3_STAGE;
494 }
495 }
496 DBG("\n Did not find matching descriptor: = 0x%x", s.value);
497 }
498 break;
499 case SETUP(DEVICE_READ, GET_CONFIGURATION):
500 {
501 DBG("\n DEVICE_READ : GET_CONFIGURATION");
502
503 if ((s.value == 0) && (s.index == 0) && (s.length == 1)) {
504
505 len = 1;
506
507 /* copy to tx buffer */
508 memcpy(udc->ctrl_tx_buf, &udc->config_selected, len);
509
510 /* flush buffer to main memory before queueing the request */
511 arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len);
512
513 dwc_transfer_request(udc->dwc,
514 0,
515 DWC_EP_DIRECTION_IN,
516 udc->ctrl_tx_buf,
517 len,
518 NULL,
519 NULL);
520
521 return DWC_SETUP_3_STAGE;
522 }
523 else
524 {
525 ASSERT(0);
526 }
527 }
528 break;
529 case SETUP(DEVICE_WRITE, SET_CONFIGURATION):
530 {
531 DBG("\n DEVICE_WRITE : SET_CONFIGURATION");
532
533 /* select configuration 1 */
534 if (s.value == 1) {
535 struct udc_endpoint *ept;
536 /* enable endpoints */
537 for (ept = udc->ept_list; ept; ept = ept->next) {
538 if (ept->num == 0)
539 continue;
540 else
541 {
542 /* add this ep to dwc ep list */
543 dwc_ep_t ep;
544
545 ep.number = ept->num;
546 ep.dir = ept->in;
547 ep.type = EP_TYPE_BULK; /* the only one supported */
548 ep.max_pkt_size = ept->maxpkt;
549 ep.burst_size = ept->maxburst;
550 ep.zlp = 0; /* TODO: zlp could be made part of ept */
551 ep.trb_count = ept->trb_count;
552 ep.trb = ept->trb;
553
554 dwc_device_add_ep(dwc, ep);
555 }
556 }
557
558 /* now that we have saved the non-control EP details, set config */
559 dwc_device_set_configuration(dwc);
560
561 /* inform client that we are configured. */
562 udc->gadget->notify(udc_dev->gadget, UDC_EVENT_ONLINE);
563
564 udc->config_selected = 1;
565
566 return DWC_SETUP_2_STAGE;
567 }
568 else if (s.value == 0)
569 {
570 /* 0 == de-configure. */
571 udc->config_selected = 0;
572 DBG("\n\n CONFIG = 0 !!!!!!!!!\n\n");
573 return DWC_SETUP_2_STAGE;
574 /* TODO: do proper handling for de-config */
575 }
576 else
577 {
578 ERR("\n CONFIG = %d not supported\n", s.value);
579 ASSERT(0);
580 }
581 }
582 break;
583 case SETUP(DEVICE_WRITE, SET_ADDRESS):
584 {
585 DBG("\n DEVICE_WRITE : SET_ADDRESS");
586
587 dwc_device_set_addr(dwc, s.value);
588 return DWC_SETUP_2_STAGE;
589 }
590 break;
591 case SETUP(INTERFACE_WRITE, SET_INTERFACE):
592 {
593 DBG("\n DEVICE_WRITE : SET_INTERFACE");
594 /* if we ack this everything hangs */
595 /* per spec, STALL is valid if there is not alt func */
596 goto stall;
597 }
598 break;
599 case SETUP(DEVICE_WRITE, SET_FEATURE):
600 {
601 DBG("\n DEVICE_WRITE : SET_FEATURE");
602 goto stall;
603 }
604 break;
605 case SETUP(DEVICE_WRITE, CLEAR_FEATURE):
606 {
607 DBG("\n DEVICE_WRITE : CLEAR_FEATURE");
608 goto stall;
609 }
610 break;
611 case SETUP(ENDPOINT_WRITE, CLEAR_FEATURE):
612 {
613 DBG("\n DEVICE_WRITE : CLEAR_FEATURE");
614 goto stall;
615 }
616 break;
617 case SETUP(DEVICE_WRITE, SET_SEL):
618 {
619 DBG("\n DEVICE_WRITE : SET_SEL");
620
621 /* this is 3-stage write. need to receive data of s.length size. */
622 if (s.length > 0) {
623 dwc_transfer_request(udc->dwc,
624 0,
625 DWC_EP_DIRECTION_OUT,
626 udc->ctrl_rx_buf,
627 UDC_CONTROL_RX_BUF_SIZE,
628 udc_control_rx_callback,
629 (void *) udc);
630 return DWC_SETUP_3_STAGE;
631 }
632 else
633 {
634 /* length must be non-zero */
635 ASSERT(0);
636 }
637 }
638 break;
639
640 default:
641 ERR("\n Unknown setup req.\n type = 0x%x value = %d index = %d"
642 " length = %d\n", s.type, s.value, s.index, s.length);
643 ASSERT(0);
644 }
645
646stall:
647 ERR("\nSTALL. Unsupported setup req: %s %d %d %d %d %d\n",
648 reqname(s.request), s.type, s.request, s.value, s.index, s.length);
649
650 return DWC_SETUP_ERROR;
651}
652
653/* Callback function called by DWC layer when a request to transfer data
654 * on non-control EP is completed.
655 */
656void udc_request_complete(void *context, uint32_t actual, int status)
657{
658 struct udc_request *req = ((udc_t *) context)->queued_req;
659
660 DBG("\n UDC: udc_request_callback: xferred %d bytes status = %d\n",
661 actual, status);
662
663 /* clear the queued request. */
664 ((udc_t *) context)->queued_req = NULL;
665
666 if (req->complete)
667 {
668 req->complete(req, actual, status);
669 }
670
671 DBG("\n UDC: udc_request_callback: done fastboot callback\n");
672}
673
674/* App interface to queue in data transfer requests for control and data ep */
Amol Jadi151f2a52013-10-07 12:39:11 -0700675int usb30_udc_request_queue(struct udc_endpoint *ept, struct udc_request *req)
Amol Jadif3d5a892013-07-23 16:09:44 -0700676{
677 int ret;
678 dwc_dev_t *dwc_dev = udc_dev->dwc;
679
680 /* ensure device is initialized before queuing request */
681 ASSERT(dwc_dev);
682
683 /* if device is not configured, return error */
684 if(udc_dev->config_selected == 0)
685 {
686 return -1;
687 }
688
689 /* only one request at a time is supported.
690 * check if a request is already queued.
691 */
692 if(udc_dev->queued_req)
693 {
694 return -1;
695 }
696
697 DBG("\n udc_request_queue: entry: ep_usb_num = %d", ept->num);
698
699 /* save the queued request. */
700 udc_dev->queued_req = req;
701
702 ret = dwc_transfer_request(dwc_dev,
703 ept->num,
704 ept->in ? DWC_EP_DIRECTION_IN : DWC_EP_DIRECTION_OUT,
705 req->buf,
706 req->length,
707 udc_request_complete,
708 (void *) udc_dev);
709
710 DBG("\n udc_request_queue: exit: ep_usb_num = %d", ept->num);
711
712 return ret;
713}
714
715/* callback function called by dwc layer if any dwc event occurs */
716void udc_dwc_notify(void *context, dwc_notify_event_t event)
717{
718 udc_t *udc = (udc_t *) context;
719
720 switch (event)
721 {
722 case DWC_NOTIFY_EVENT_CONNECTED_LS:
723 udc->speed = UDC_SPEED_LS;
724 break;
725 case DWC_NOTIFY_EVENT_CONNECTED_FS:
726 udc->speed = UDC_SPEED_FS;
727 break;
728 case DWC_NOTIFY_EVENT_CONNECTED_HS:
729 udc->speed = UDC_SPEED_HS;
730 break;
731 case DWC_NOTIFY_EVENT_CONNECTED_SS:
732 udc->speed = UDC_SPEED_SS;
733 break;
734 case DWC_NOTIFY_EVENT_DISCONNECTED:
735 case DWC_NOTIFY_EVENT_OFFLINE:
736 udc->config_selected = 0;
737 if (udc->gadget && udc->gadget->notify)
738 udc->gadget->notify(udc->gadget, UDC_EVENT_OFFLINE);
739 break;
740 default:
741 ASSERT(0);
742 }
743}
744
745
746/******************* Function related to descriptor allocation etc.************/
747
748static struct udc_endpoint *_udc_endpoint_alloc(uint8_t num,
749 uint8_t in,
750 uint16_t max_pkt)
751{
752 struct udc_endpoint *ept;
753 udc_t *udc = udc_dev;
754
755 ept = malloc(sizeof(*ept));
756 ASSERT(ept);
757
758 ept->maxpkt = max_pkt;
759 ept->num = num;
760 ept->in = !!in;
761 ept->maxburst = 4; /* no performance improvement is seen beyond burst size of 4 */
762 ept->trb_count = 66; /* each trb can transfer (16MB - 1). 65 for 1GB transfer + 1 for roundup/zero length pkt. */
763 ept->trb = memalign(lcm(CACHE_LINE, 16), ROUNDUP(ept->trb_count*sizeof(dwc_trb_t), CACHE_LINE)); /* TRB must be aligned to 16 */
764 ASSERT(ept->trb);
765
766 /* push it on top of ept_list */
767 ept->next = udc->ept_list;
768 udc->ept_list = ept;
769
770 return ept;
771}
772
773/* Called to create non-control in/out End Point structures by the APP */
Amol Jadi151f2a52013-10-07 12:39:11 -0700774struct udc_endpoint *usb30_udc_endpoint_alloc(unsigned type, unsigned maxpkt)
Amol Jadif3d5a892013-07-23 16:09:44 -0700775{
776 struct udc_endpoint *ept;
777 uint8_t in;
778 uint8_t n;
779 udc_t *udc = udc_dev;
780
781 if (type == UDC_TYPE_BULK_IN) {
782 in = 1;
783 } else if (type == UDC_TYPE_BULK_OUT) {
784 in = 0;
785 } else {
786 return 0;
787 }
788
789 for (n = 1; n < 16; n++) {
790 uint32_t bit = in ? EPT_TX(n) : EPT_RX(n);
791 if (udc->ept_alloc_table & bit)
792 continue;
793 ept = _udc_endpoint_alloc(n, in, maxpkt);
794 if (ept)
795 udc->ept_alloc_table |= bit;
796 return ept;
797 }
798 return 0;
799}
800
801
802/* create config + interface + ep desc for 2.0 */
803static void udc_register_config_desc_usb20(udc_t *udc,
804 struct udc_gadget *gadget)
805{
806 uint8_t *data;
807 uint16_t size;
808 struct udc_descriptor *desc;
809
810 ASSERT(udc);
811 ASSERT(gadget);
812
813 /* create our configuration descriptor */
814
815 /* size is the total size of (config + interface + all EPs) descriptor */
816 size = UDC_DESC_SIZE_CONFIGURATION +
817 UDC_DESC_SIZE_INTERFACE +
818 (gadget->ifc_endpoints*UDC_DESC_SIZE_ENDPOINT);
819
820 desc = udc_descriptor_alloc(TYPE_CONFIGURATION, 0, size, UDC_DESC_SPEC_20);
821
822 data = desc->data;
823
824 /* Config desc */
825 data[0] = 0x09;
826 data[1] = TYPE_CONFIGURATION;
827 data[2] = size;
828 data[3] = size >> 8;
829 data[4] = 0x01; /* number of interfaces */
830 data[5] = 0x01; /* configuration value */
831 data[6] = 0x00; /* configuration string */
832 data[7] = 0xC0; /* attributes: reserved and self-powered set */
833 data[8] = 0x00; /* max power: 0ma since we are self powered */
834 data += 9;
835
836 /* Interface desc */
837 data[0] = 0x09;
838 data[1] = TYPE_INTERFACE;
839 data[2] = 0x00; /* ifc number */
840 data[3] = 0x00; /* alt number */
841 data[4] = gadget->ifc_endpoints;
842 data[5] = gadget->ifc_class;
843 data[6] = gadget->ifc_subclass;
844 data[7] = gadget->ifc_protocol;
845 data[8] = udc_string_desc_alloc(udc, gadget->ifc_string);
846 data += 9;
847
848 for (uint8_t n = 0; n < gadget->ifc_endpoints; n++) {
849 udc_ept_desc_fill(gadget->ept[n], data);
850 data += UDC_DESC_SIZE_ENDPOINT;
851 }
852
853 udc_descriptor_register(udc, desc);
854}
855
856/* create config + interface + ep desc for 3.0 */
857static void udc_register_config_desc_usb30(udc_t *udc,
858 struct udc_gadget *gadget)
859{
860 uint8_t *data;
861 uint16_t size;
862 struct udc_descriptor *desc;
863
864 ASSERT(udc);
865 ASSERT(gadget);
866
867 /* create our configuration descriptor */
868
869 /* size is the total size of (config + interface + all EPs) descriptor */
870 size = UDC_DESC_SIZE_CONFIGURATION +
871 UDC_DESC_SIZE_INTERFACE +
872 (gadget->ifc_endpoints*(UDC_DESC_SIZE_ENDPOINT + UDC_DESC_SIZE_ENDPOINT_COMP));
873
874 desc = udc_descriptor_alloc(TYPE_CONFIGURATION, 0, size, UDC_DESC_SPEC_30);
875
876 data = desc->data;
877
878 /* Config desc */
879 data[0] = 0x09;
880 data[1] = TYPE_CONFIGURATION;
881 data[2] = size;
882 data[3] = size >> 8;
883 data[4] = 0x01; /* number of interfaces */
884 data[5] = 0x01; /* configuration value */
885 data[6] = 0x00; /* configuration string */
886 data[7] = 0xC0; /* attributes: reserved and self-powered set */
887 data[8] = 0x00; /* max power: 0ma since we are self powered */
888 data += 9;
889
890 /* Interface desc */
891 data[0] = 0x09;
892 data[1] = TYPE_INTERFACE;
893 data[2] = 0x00; /* ifc number */
894 data[3] = 0x00; /* alt number */
895 data[4] = gadget->ifc_endpoints;
896 data[5] = gadget->ifc_class;
897 data[6] = gadget->ifc_subclass;
898 data[7] = gadget->ifc_protocol;
899 data[8] = udc_string_desc_alloc(udc, gadget->ifc_string);
900 data += 9;
901
902 for (uint8_t n = 0; n < gadget->ifc_endpoints; n++)
903 {
904 /* fill EP desc */
905 udc_ept_desc_fill(gadget->ept[n], data);
906 data += UDC_DESC_SIZE_ENDPOINT;
907
908 /* fill EP companion desc */
909 udc_ept_comp_desc_fill(gadget->ept[n], data);
910 data += UDC_DESC_SIZE_ENDPOINT_COMP;
911 }
912
913 udc_descriptor_register(udc, desc);
914}
915
916
917static void udc_register_device_desc_usb_20(udc_t *udc,
918 struct udc_device *dev_info)
919{
920 uint8_t *data;
921 struct udc_descriptor *desc;
922
923 /* create our device descriptor */
924 desc = udc_descriptor_alloc(TYPE_DEVICE, 0, 18, UDC_DESC_SPEC_20);
925 data = desc->data;
926
927 /* data 0 and 1 is filled by descriptor alloc routine.
928 * fill in the remaining entries.
929 */
930 data[2] = 0x00; /* usb spec minor rev */
931 data[3] = 0x02; /* usb spec major rev */
932 data[4] = 0x00; /* class */
933 data[5] = 0x00; /* subclass */
934 data[6] = 0x00; /* protocol */
935 data[7] = 0x40; /* max packet size on ept 0 */
936
937 memcpy(data + 8, &dev_info->vendor_id, sizeof(short));
938 memcpy(data + 10, &dev_info->product_id, sizeof(short));
939 memcpy(data + 12, &dev_info->version_id, sizeof(short));
940
941 data[14] = udc_string_desc_alloc(udc, dev_info->manufacturer);
942 data[15] = udc_string_desc_alloc(udc, dev_info->product);
943 data[16] = udc_string_desc_alloc(udc, dev_info->serialno);
944 data[17] = 1; /* number of configurations */
945
946 udc_descriptor_register(udc, desc);
947}
948
949static void udc_register_device_desc_usb_30(udc_t *udc, struct udc_device *dev_info)
950{
951 uint8_t *data;
952 struct udc_descriptor *desc;
953
954 /* create our device descriptor */
955 desc = udc_descriptor_alloc(TYPE_DEVICE, 0, 18, UDC_DESC_SPEC_30);
956 data = desc->data;
957
958 /* data 0 and 1 is filled by descriptor alloc routine.
959 * fill in the remaining entries.
960 */
961 data[2] = 0x00; /* usb spec minor rev */
962 data[3] = 0x03; /* usb spec major rev */
963 data[4] = 0x00; /* class */
964 data[5] = 0x00; /* subclass */
965 data[6] = 0x00; /* protocol */
966 data[7] = 0x09; /* max packet size on ept 0 */
967 memcpy(data + 8, &dev_info->vendor_id, sizeof(short));
968 memcpy(data + 10, &dev_info->product_id, sizeof(short));
969 memcpy(data + 12, &dev_info->version_id, sizeof(short));
970 data[14] = udc_string_desc_alloc(udc, dev_info->manufacturer);
971 data[15] = udc_string_desc_alloc(udc, dev_info->product);
972 data[16] = udc_string_desc_alloc(udc, dev_info->serialno);
973 data[17] = 1; /* number of configurations */
974
975 udc_descriptor_register(udc, desc);
976}
977
978static void udc_register_bos_desc(udc_t *udc)
979{
980 uint8_t *data;
981 struct udc_descriptor *desc;
982
983 /* create our device descriptor */
984 desc = udc_descriptor_alloc(TYPE_BOS, 0, 15, UDC_DESC_SPEC_30); /* 15 is total length of bos + other descriptors inside it */
985 data = desc->data;
986
987 /* data 0 and 1 is filled by descriptor alloc routine.
988 * fill in the remaining entries.
989 */
990 data[0] = 0x05; /* BOS desc len */
991 data[1] = TYPE_BOS; /* BOS desc type */
992 data[2] = 0x0F; /* total len of bos desc and its sub desc */
993 data[3] = 0x00; /* total len of bos desc and its sub desc */
994 data[4] = 0x01; /* num of sub desc inside bos */
995
996 data[5] = 0x0A; /* desc len */
997 data[6] = 0x10; /* Device Capability desc */
998 data[7] = 0x03; /* 3 == SuperSpeed capable */
999 data[8] = 0x00; /* Attribute: latency tolerance msg: No */
1000 data[9] = 0x0F; /* Supported Speeds (bit mask): LS, FS, HS, SS */
1001 data[10] = 0x00; /* Reserved part of supported wSupportedSpeeds */
1002 data[11] = 0x01; /* lowest supported speed with full functionality: FS */
1003 data[12] = 0x00; /* U1 device exit latency */
1004 data[13] = 0x00; /* U2 device exit latency (lsb) */
1005 data[14] = 0x00; /* U2 device exit latency (msb) */
1006
1007 udc_descriptor_register(udc, desc);
1008}
1009
1010static void udc_register_language_desc(udc_t *udc)
1011{
1012 /* create and register a language table descriptor */
1013 /* language 0x0409 is US English */
1014 struct udc_descriptor *desc = udc_descriptor_alloc(TYPE_STRING,
1015 0,
1016 4,
1017 UDC_DESC_SPEC_20 | UDC_DESC_SPEC_30);
1018 desc->data[2] = 0x09;
1019 desc->data[3] = 0x04;
1020 udc_descriptor_register(udc, desc);
1021}
1022
1023static void udc_ept_desc_fill(struct udc_endpoint *ept, uint8_t *data)
1024{
1025 data[0] = 7;
1026 data[1] = TYPE_ENDPOINT;
1027 data[2] = ept->num | (ept->in ? 0x80 : 0x00);
1028 data[3] = 0x02; /* bulk -- the only kind we support */
1029 data[4] = ept->maxpkt;
1030 data[5] = ept->maxpkt >> 8;
1031 data[6] = 0; /* bInterval: must be 0 for bulk. */
1032}
1033
1034static void udc_ept_comp_desc_fill(struct udc_endpoint *ept, uint8_t *data)
1035{
1036 data[0] = 6; /* bLength */
1037 data[1] = TYPE_SS_EP_COMP; /* ep type */
1038 data[2] = ept->maxburst; /* maxBurst */
1039 data[3] = 0x0; /* maxStreams */
1040 data[4] = 0x0; /* wBytesPerInterval */
1041 data[5] = 0x0; /* wBytesPerInterval */
1042}
1043
1044static uint8_t udc_string_desc_alloc(udc_t *udc, const char *str)
1045{
1046 uint32_t len;
1047 struct udc_descriptor *desc;
1048 uint8_t *data;
1049
1050 if (udc->next_string_id > 255)
1051 return 0;
1052
1053 if (!str)
1054 return 0;
1055
1056 len = strlen(str);
1057 desc = udc_descriptor_alloc(TYPE_STRING,
1058 udc->next_string_id,
1059 len * 2 + 2,
1060 UDC_DESC_SPEC_20 | UDC_DESC_SPEC_30);
1061 if (!desc)
1062 return 0;
1063 udc->next_string_id++;
1064
1065 /* expand ascii string to utf16 */
1066 data = desc->data + 2;
1067 while (len-- > 0) {
1068 *data++ = *str++;
1069 *data++ = 0;
1070 }
1071
1072 udc_descriptor_register(udc, desc);
1073 return desc->tag & 0xff;
1074}
1075
1076
1077static struct udc_descriptor *udc_descriptor_alloc(uint32_t type,
1078 uint32_t num,
1079 uint32_t len,
1080 udc_desc_spec_t spec)
1081{
1082 struct udc_descriptor *desc;
1083 if ((len > 255) || (len < 2) || (num > 255) || (type > 255))
1084 return 0;
1085
1086 if (!(desc = malloc(sizeof(struct udc_descriptor) + len)))
1087 return 0;
1088
1089 desc->next = 0;
1090 desc->tag = (type << 8) | num;
1091 desc->len = len;
1092 desc->spec = spec;
1093
1094 /* descriptor data */
1095 desc->data[0] = len;
1096 desc->data[1] = type;
1097
1098 return desc;
1099}
1100
1101static void udc_descriptor_register(udc_t *udc, struct udc_descriptor *desc)
1102{
1103 desc->next = udc->desc_list;
1104 udc->desc_list = desc;
1105}
1106
1107
Amol Jadi151f2a52013-10-07 12:39:11 -07001108struct udc_request *usb30_udc_request_alloc(void)
Amol Jadif3d5a892013-07-23 16:09:44 -07001109{
1110 struct udc_request *req;
1111
1112 req = malloc(sizeof(*req));
1113 ASSERT(req);
1114
1115 req->buf = 0;
1116 req->length = 0;
1117 req->complete = NULL;
1118 req->context = 0;
1119
1120 return req;
1121}
1122
Amol Jadi151f2a52013-10-07 12:39:11 -07001123void usb30_udc_request_free(struct udc_request *req)
Amol Jadif3d5a892013-07-23 16:09:44 -07001124{
1125 free(req);
1126}
1127
Amol Jadi151f2a52013-10-07 12:39:11 -07001128void usb30_udc_endpoint_free(struct udc_endpoint *ept)
Amol Jadif3d5a892013-07-23 16:09:44 -07001129{
1130 /* TODO */
1131}
1132
Amol Jadi151f2a52013-10-07 12:39:11 -07001133int usb30_udc_stop(void)
Amol Jadif3d5a892013-07-23 16:09:44 -07001134{
1135 dwc_device_run(udc_dev->dwc, 0);
1136
1137 return 0;
1138}