Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <err.h> |
| 30 | #include <assert.h> |
| 31 | #include <debug.h> |
| 32 | #include <reg.h> |
| 33 | #include <platform/timer.h> |
| 34 | #include <platform/iomap.h> |
| 35 | #include <mmc.h> |
| 36 | #include <clock.h> |
| 37 | #include <platform/clock.h> |
| 38 | |
| 39 | void hsusb_clock_init(void) |
| 40 | { |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 41 | int ret; |
| 42 | struct clk *iclk, *cclk; |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 43 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 44 | ret = clk_get_set_enable("usb_iface_clk", 0, 1); |
| 45 | if(ret) |
| 46 | { |
| 47 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 48 | ASSERT(0); |
| 49 | } |
| 50 | |
| 51 | ret = clk_get_set_enable("usb_core_clk", 80000000, 1); |
| 52 | if(ret) |
| 53 | { |
| 54 | dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret); |
| 55 | ASSERT(0); |
| 56 | } |
| 57 | |
| 58 | mdelay(20); |
| 59 | |
| 60 | iclk = clk_get("usb_iface_clk"); |
| 61 | cclk = clk_get("usb_core_clk"); |
| 62 | |
| 63 | clk_disable(iclk); |
| 64 | clk_disable(cclk); |
| 65 | |
| 66 | mdelay(20); |
| 67 | |
| 68 | /* Start the block reset for usb */ |
| 69 | writel(1, USB_HS_BCR); |
| 70 | |
| 71 | mdelay(20); |
| 72 | |
| 73 | /* Take usb block out of reset */ |
| 74 | writel(0, USB_HS_BCR); |
| 75 | |
| 76 | mdelay(20); |
| 77 | |
| 78 | ret = clk_enable(iclk); |
| 79 | |
| 80 | if(ret) |
| 81 | { |
| 82 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 83 | ASSERT(0); |
| 84 | } |
| 85 | |
| 86 | ret = clk_enable(cclk); |
| 87 | |
| 88 | if(ret) |
| 89 | { |
| 90 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 91 | ASSERT(0); |
| 92 | } |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | void clock_init_mmc(uint32_t interface) |
| 96 | { |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 97 | char clk_name[64]; |
| 98 | int ret; |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 99 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 100 | snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface); |
| 101 | |
| 102 | /* enable interface clock */ |
| 103 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 104 | if(ret) |
| 105 | { |
| 106 | dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret); |
| 107 | ASSERT(0); |
| 108 | } |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | /* Configure MMC clock */ |
| 112 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 113 | { |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 114 | int ret; |
| 115 | uint32_t reg; |
| 116 | char clk_name[64]; |
| 117 | |
| 118 | snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface); |
| 119 | |
| 120 | if(freq == MMC_CLK_400KHZ) |
| 121 | { |
| 122 | ret = clk_get_set_enable(clk_name, 400000, 1); |
| 123 | } |
| 124 | else if(freq == MMC_CLK_50MHZ) |
| 125 | { |
| 126 | ret = clk_get_set_enable(clk_name, 50000000, 1); |
| 127 | } |
| 128 | else if(freq == MMC_CLK_200MHZ) |
| 129 | { |
| 130 | ret = clk_get_set_enable(clk_name, 200000000, 1); |
| 131 | } |
| 132 | else if(freq == MMC_CLK_177MHZ) |
| 133 | { |
| 134 | ret = clk_get_set_enable(clk_name, 177770000, 1); |
| 135 | } |
| 136 | else |
| 137 | { |
| 138 | dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq); |
| 139 | ASSERT(0); |
| 140 | } |
| 141 | |
| 142 | if(ret) |
| 143 | { |
| 144 | dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret); |
| 145 | ASSERT(0); |
| 146 | } |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | /* Configure UART clock based on the UART block id*/ |
| 150 | void clock_config_uart_dm(uint8_t id) |
| 151 | { |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 152 | int ret; |
| 153 | char iclk[64]; |
| 154 | char cclk[64]; |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 155 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 156 | snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id); |
| 157 | snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id); |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 158 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 159 | ret = clk_get_set_enable(iclk, 0, 1); |
| 160 | if(ret) |
| 161 | { |
| 162 | dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret); |
| 163 | ASSERT(0); |
| 164 | } |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 165 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 166 | ret = clk_get_set_enable(cclk, 7372800, 1); |
| 167 | if(ret) |
| 168 | { |
| 169 | dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret); |
| 170 | ASSERT(0); |
| 171 | } |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 172 | } |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame^] | 173 | |
| 174 | /* Control the MDSS GDSC */ |
| 175 | void mdp_gdsc_ctrl(uint8_t enable) |
| 176 | { |
| 177 | uint32_t reg = 0; |
| 178 | reg = readl(MDP_GDSCR); |
| 179 | if (enable) { |
| 180 | if (!(reg & GDSC_POWER_ON_BIT)) { |
| 181 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 182 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 183 | writel(reg, MDP_GDSCR); |
| 184 | while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 185 | } else { |
| 186 | dprintf(SPEW, "MDP GDSC already enabled\n"); |
| 187 | } |
| 188 | } else { |
| 189 | reg |= BIT(0); |
| 190 | writel(reg, MDP_GDSCR); |
| 191 | while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)); |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | /* Enable all the MDP branch clocks */ |
| 196 | void mdp_clock_enable(void) |
| 197 | { |
| 198 | int ret; |
| 199 | |
| 200 | ret = clk_get_set_enable("mdp_ahb_clk", 0, 1); |
| 201 | if(ret) |
| 202 | { |
| 203 | dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret); |
| 204 | ASSERT(0); |
| 205 | } |
| 206 | |
| 207 | /* Set MDP clock to 320MHz */ |
| 208 | ret = clk_get_set_enable("mdss_mdp_clk_src", 320000000, 1); |
| 209 | if(ret) |
| 210 | { |
| 211 | dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret); |
| 212 | ASSERT(0); |
| 213 | } |
| 214 | |
| 215 | ret = clk_get_set_enable("mdss_vsync_clk", 0, 1); |
| 216 | if(ret) |
| 217 | { |
| 218 | dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret); |
| 219 | ASSERT(0); |
| 220 | } |
| 221 | |
| 222 | ret = clk_get_set_enable("mdss_mdp_clk", 0, 1); |
| 223 | if(ret) |
| 224 | { |
| 225 | dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret); |
| 226 | ASSERT(0); |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | /* Disable all the MDP branch clocks */ |
| 231 | void mdp_clock_disable(void) |
| 232 | { |
| 233 | clk_disable(clk_get("mdss_vsync_clk")); |
| 234 | clk_disable(clk_get("mdss_mdp_clk")); |
| 235 | clk_disable(clk_get("mdss_mdp_clk_src")); |
| 236 | clk_disable(clk_get("mdp_ahb_clk")); |
| 237 | } |
| 238 | |
| 239 | /* Disable all the bus clocks needed by MDSS */ |
| 240 | void mdss_bus_clocks_disable(void) |
| 241 | { |
| 242 | /* Disable MDSS AXI clock */ |
| 243 | clk_disable(clk_get("mdss_axi_clk")); |
| 244 | } |
| 245 | |
| 246 | /* Enable all the bus clocks needed by MDSS */ |
| 247 | void mdss_bus_clocks_enable(void) |
| 248 | { |
| 249 | int ret; |
| 250 | |
| 251 | /* Configure AXI clock */ |
| 252 | ret = clk_get_set_enable("mdss_axi_clk", 0, 1); |
| 253 | if(ret) |
| 254 | { |
| 255 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 256 | ASSERT(0); |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | /* Disable all the branch clocks needed by the DSI controller */ |
| 261 | void gcc_dsi_clocks_disable(void) |
| 262 | { |
| 263 | clk_disable(clk_get("mdss_esc0_clk")); |
| 264 | writel(0x0, DSI_PIXEL0_CBCR); |
| 265 | writel(0x0, DSI_BYTE0_CBCR); |
| 266 | } |
| 267 | |
| 268 | /* Configure all the branch clocks needed by the DSI controller */ |
| 269 | void gcc_dsi_clocks_enable(uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d) |
| 270 | { |
| 271 | int ret; |
| 272 | |
| 273 | /* Configure Byte clock -autopll- This will not change becasue |
| 274 | byte clock does not need any divider*/ |
| 275 | writel(0x100, DSI_BYTE0_CFG_RCGR); |
| 276 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
| 277 | writel(0x1, DSI_BYTE0_CBCR); |
| 278 | |
| 279 | /* Configure Pixel clock */ |
| 280 | writel(0x100, DSI_PIXEL0_CFG_RCGR); |
| 281 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 282 | writel(0x1, DSI_PIXEL0_CBCR); |
| 283 | |
| 284 | writel(pclk0_m, DSI_PIXEL0_M); |
| 285 | writel(pclk0_n, DSI_PIXEL0_N); |
| 286 | writel(pclk0_d, DSI_PIXEL0_D); |
| 287 | |
| 288 | /* Configure ESC clock */ |
| 289 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 290 | if (ret) { |
| 291 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 292 | ASSERT(0); |
| 293 | } |
| 294 | } |