Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
Channagoud Kadabi | dd7cb38 | 2015-03-23 23:30:25 -0700 | [diff] [blame^] | 34 | #include <clock_alpha_pll.h> |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 35 | #include <clock_lib2.h> |
| 36 | #include <platform/clock.h> |
| 37 | #include <platform/iomap.h> |
| 38 | |
| 39 | |
| 40 | /* Mux source select values */ |
| 41 | #define cxo_source_val 0 |
| 42 | #define gpll0_source_val 1 |
| 43 | #define gpll4_source_val 5 |
| 44 | #define cxo_mm_source_val 0 |
| 45 | #define mmpll0_mm_source_val 1 |
| 46 | #define mmpll1_mm_source_val 2 |
| 47 | #define mmpll3_mm_source_val 3 |
| 48 | #define gpll0_mm_source_val 5 |
| 49 | |
| 50 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 51 | |
| 52 | |
| 53 | /* Clock Operations */ |
| 54 | static struct clk_ops clk_ops_rst = |
| 55 | { |
| 56 | .reset = clock_lib2_reset_clk_reset, |
| 57 | }; |
| 58 | |
| 59 | static struct clk_ops clk_ops_branch = |
| 60 | { |
| 61 | .enable = clock_lib2_branch_clk_enable, |
| 62 | .disable = clock_lib2_branch_clk_disable, |
| 63 | .set_rate = clock_lib2_branch_set_rate, |
| 64 | .reset = clock_lib2_branch_clk_reset, |
| 65 | }; |
| 66 | |
| 67 | static struct clk_ops clk_ops_rcg_mnd = |
| 68 | { |
| 69 | .enable = clock_lib2_rcg_enable, |
| 70 | .set_rate = clock_lib2_rcg_set_rate, |
| 71 | }; |
| 72 | |
| 73 | static struct clk_ops clk_ops_rcg = |
| 74 | { |
| 75 | .enable = clock_lib2_rcg_enable, |
| 76 | .set_rate = clock_lib2_rcg_set_rate, |
| 77 | }; |
| 78 | |
| 79 | static struct clk_ops clk_ops_cxo = |
| 80 | { |
| 81 | .enable = cxo_clk_enable, |
| 82 | .disable = cxo_clk_disable, |
| 83 | }; |
| 84 | |
| 85 | static struct clk_ops clk_ops_pll_vote = |
| 86 | { |
| 87 | .enable = pll_vote_clk_enable, |
| 88 | .disable = pll_vote_clk_disable, |
| 89 | .auto_off = pll_vote_clk_disable, |
| 90 | .is_enabled = pll_vote_clk_is_enabled, |
| 91 | }; |
| 92 | |
| 93 | static struct clk_ops clk_ops_vote = |
| 94 | { |
| 95 | .enable = clock_lib2_vote_clk_enable, |
| 96 | .disable = clock_lib2_vote_clk_disable, |
| 97 | }; |
| 98 | |
Channagoud Kadabi | dd7cb38 | 2015-03-23 23:30:25 -0700 | [diff] [blame^] | 99 | static struct clk_ops clk_ops_fixed_alpha_pll = |
| 100 | { |
| 101 | .enable = alpha_pll_enable, |
| 102 | .disable = alpha_pll_disable, |
| 103 | }; |
| 104 | |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 105 | /* Clock Sources */ |
| 106 | static struct fixed_clk cxo_clk_src = |
| 107 | { |
| 108 | .c = { |
| 109 | .rate = 19200000, |
| 110 | .dbg_name = "cxo_clk_src", |
| 111 | .ops = &clk_ops_cxo, |
| 112 | }, |
| 113 | }; |
| 114 | |
| 115 | static struct pll_vote_clk gpll0_clk_src = |
| 116 | { |
| 117 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 118 | .en_mask = BIT(0), |
| 119 | .status_reg = (void *) GPLL0_MODE, |
| 120 | .status_mask = BIT(30), |
| 121 | .parent = &cxo_clk_src.c, |
| 122 | |
| 123 | .c = { |
| 124 | .rate = 600000000, |
| 125 | .dbg_name = "gpll0_clk_src", |
| 126 | .ops = &clk_ops_pll_vote, |
| 127 | }, |
| 128 | }; |
| 129 | |
| 130 | static struct pll_vote_clk gpll4_clk_src = |
| 131 | { |
| 132 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 133 | .en_mask = BIT(4), |
| 134 | .status_reg = (void *) GPLL4_MODE, |
| 135 | .status_mask = BIT(30), |
| 136 | .parent = &cxo_clk_src.c, |
| 137 | |
| 138 | .c = { |
| 139 | .rate = 1600000000, |
| 140 | .dbg_name = "gpll4_clk_src", |
| 141 | .ops = &clk_ops_pll_vote, |
| 142 | }, |
| 143 | }; |
| 144 | |
| 145 | /* UART Clocks */ |
| 146 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 147 | { |
| 148 | F( 3686400, gpll0, 1, 96, 15625), |
| 149 | F( 7372800, gpll0, 1, 192, 15625), |
| 150 | F(14745600, gpll0, 1, 384, 15625), |
| 151 | F(16000000, gpll0, 5, 2, 15), |
| 152 | F(19200000, cxo, 1, 0, 0), |
| 153 | F(24000000, gpll0, 5, 1, 5), |
| 154 | F(32000000, gpll0, 1, 4, 75), |
| 155 | F(40000000, gpll0, 15, 0, 0), |
| 156 | F(46400000, gpll0, 1, 29, 375), |
| 157 | F(48000000, gpll0, 12.5, 0, 0), |
| 158 | F(51200000, gpll0, 1, 32, 375), |
| 159 | F(56000000, gpll0, 1, 7, 75), |
| 160 | F(58982400, gpll0, 1, 1536, 15625), |
| 161 | F(60000000, gpll0, 10, 0, 0), |
| 162 | F(63160000, gpll0, 9.5, 0, 0), |
| 163 | F_END |
| 164 | }; |
| 165 | |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 166 | static struct rcg_clk blsp2_uart2_apps_clk_src = |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 167 | { |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 168 | .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR, |
| 169 | .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR, |
| 170 | .m_reg = (uint32_t *) BLSP2_UART2_APPS_M, |
| 171 | .n_reg = (uint32_t *) BLSP2_UART2_APPS_N, |
| 172 | .d_reg = (uint32_t *) BLSP2_UART2_APPS_D, |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 173 | |
| 174 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 175 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 176 | .current_freq = &rcg_dummy_freq, |
| 177 | |
| 178 | .c = { |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 179 | .dbg_name = "blsp2_uart2_apps_clk", |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 180 | .ops = &clk_ops_rcg_mnd, |
| 181 | }, |
| 182 | }; |
| 183 | |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 184 | static struct branch_clk gcc_blsp2_uart2_apps_clk = |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 185 | { |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 186 | .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR, |
| 187 | .parent = &blsp2_uart2_apps_clk_src.c, |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 188 | |
| 189 | .c = { |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 190 | .dbg_name = "gcc_blsp2_uart2_apps_clk", |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 191 | .ops = &clk_ops_branch, |
| 192 | }, |
| 193 | }; |
| 194 | |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame] | 195 | static struct vote_clk gcc_blsp2_ahb_clk = { |
| 196 | .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR, |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 197 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame] | 198 | .en_mask = BIT(15), |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 199 | |
| 200 | .c = { |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame] | 201 | .dbg_name = "gcc_blsp2_ahb_clk", |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 202 | .ops = &clk_ops_vote, |
| 203 | }, |
| 204 | }; |
| 205 | |
| 206 | /* SDCC Clocks */ |
| 207 | static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = |
| 208 | { |
| 209 | F( 144000, cxo, 16, 3, 25), |
| 210 | F( 400000, cxo, 12, 1, 4), |
| 211 | F( 20000000, gpll0, 15, 1, 2), |
| 212 | F( 25000000, gpll0, 12, 1, 2), |
| 213 | F( 50000000, gpll0, 12, 0, 0), |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame] | 214 | F( 96000000, gpll4, 4, 0, 0), |
| 215 | F(192000000, gpll4, 2, 0, 0), |
| 216 | F(384000000, gpll4, 1, 0, 0), |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 217 | F_END |
| 218 | }; |
| 219 | |
| 220 | static struct rcg_clk sdcc1_apps_clk_src = |
| 221 | { |
| 222 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 223 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 224 | .m_reg = (uint32_t *) SDCC1_M, |
| 225 | .n_reg = (uint32_t *) SDCC1_N, |
| 226 | .d_reg = (uint32_t *) SDCC1_D, |
| 227 | |
| 228 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 229 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, |
| 230 | .current_freq = &rcg_dummy_freq, |
| 231 | |
| 232 | .c = { |
| 233 | .dbg_name = "sdc1_clk", |
| 234 | .ops = &clk_ops_rcg_mnd, |
| 235 | }, |
| 236 | }; |
| 237 | |
| 238 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 239 | { |
| 240 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 241 | .parent = &sdcc1_apps_clk_src.c, |
| 242 | |
| 243 | .c = { |
| 244 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 245 | .ops = &clk_ops_branch, |
| 246 | }, |
| 247 | }; |
| 248 | |
| 249 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 250 | { |
| 251 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 252 | .has_sibling = 1, |
| 253 | |
| 254 | .c = { |
| 255 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 256 | .ops = &clk_ops_branch, |
| 257 | }, |
| 258 | }; |
| 259 | |
| 260 | static struct branch_clk gcc_sys_noc_usb30_axi_clk = { |
| 261 | .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR, |
| 262 | .has_sibling = 1, |
| 263 | |
| 264 | .c = { |
| 265 | .dbg_name = "sys_noc_usb30_axi_clk", |
| 266 | .ops = &clk_ops_branch, |
| 267 | }, |
| 268 | }; |
| 269 | |
| 270 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = { |
Channagoud Kadabi | df233d2 | 2015-02-11 11:56:48 -0800 | [diff] [blame] | 271 | F( 19200000, cxo, 1, 0, 0), |
| 272 | F( 120000000, gpll0, 5, 0, 0), |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame] | 273 | F( 150000000, gpll0, 4, 0, 0), |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 274 | F_END |
| 275 | }; |
| 276 | |
| 277 | static struct rcg_clk usb30_master_clk_src = { |
| 278 | .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR, |
| 279 | .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR, |
| 280 | .m_reg = (uint32_t *) USB30_MASTER_M, |
| 281 | .n_reg = (uint32_t *) USB30_MASTER_N, |
| 282 | .d_reg = (uint32_t *) USB30_MASTER_D, |
| 283 | |
| 284 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 285 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
| 286 | .current_freq = &rcg_dummy_freq, |
| 287 | |
| 288 | .c = { |
| 289 | .dbg_name = "usb30_master_clk_src", |
| 290 | .ops = &clk_ops_rcg, |
| 291 | }, |
| 292 | }; |
| 293 | |
| 294 | static struct branch_clk gcc_usb30_master_clk = { |
| 295 | .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR, |
| 296 | .bcr_reg = (uint32_t *) USB_30_BCR, |
| 297 | .parent = &usb30_master_clk_src.c, |
| 298 | |
| 299 | .c = { |
| 300 | .dbg_name = "usb30_master_clk", |
| 301 | .ops = &clk_ops_branch, |
| 302 | }, |
| 303 | }; |
| 304 | |
Channagoud Kadabi | df233d2 | 2015-02-11 11:56:48 -0800 | [diff] [blame] | 305 | static struct branch_clk gcc_aggre2_usb3_axi_clk = { |
| 306 | .cbcr_reg = (uint32_t *) GCC_AGGRE2_USB3_AXI_CBCR, |
| 307 | .parent = &usb30_master_clk_src.c, |
| 308 | |
| 309 | .c = { |
| 310 | .dbg_name = "gcc_aggre2_usb3_axi_clk", |
| 311 | .ops = &clk_ops_branch, |
| 312 | }, |
| 313 | }; |
| 314 | |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 315 | static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { |
| 316 | F( 60000000, gpll0, 10, 0, 0), |
| 317 | F_END |
| 318 | }; |
| 319 | |
| 320 | static struct rcg_clk usb30_mock_utmi_clk_src = { |
| 321 | .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR, |
| 322 | .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR, |
| 323 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 324 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, |
| 325 | .current_freq = &rcg_dummy_freq, |
| 326 | |
| 327 | .c = { |
| 328 | .dbg_name = "usb30_mock_utmi_clk_src", |
| 329 | .ops = &clk_ops_rcg, |
| 330 | }, |
| 331 | }; |
| 332 | |
| 333 | static struct branch_clk gcc_usb30_mock_utmi_clk = { |
| 334 | .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR, |
| 335 | .has_sibling = 0, |
| 336 | .parent = &usb30_mock_utmi_clk_src.c, |
| 337 | |
| 338 | .c = { |
| 339 | .dbg_name = "usb30_mock_utmi_clk", |
| 340 | .ops = &clk_ops_branch, |
| 341 | }, |
| 342 | }; |
| 343 | |
| 344 | static struct branch_clk gcc_usb30_sleep_clk = { |
| 345 | .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR, |
| 346 | .has_sibling = 1, |
| 347 | |
| 348 | .c = { |
| 349 | .dbg_name = "usb30_sleep_clk", |
| 350 | .ops = &clk_ops_branch, |
| 351 | }, |
| 352 | }; |
| 353 | |
| 354 | static struct clk_freq_tbl ftbl_gcc_usb30_phy_aux_clk_src[] = { |
| 355 | F( 1200000, cxo, 16, 0, 0), |
| 356 | F_END |
| 357 | }; |
| 358 | |
| 359 | static struct rcg_clk usb30_phy_aux_clk_src = { |
| 360 | .cmd_reg = (uint32_t *) USB30_PHY_AUX_CMD_RCGR, |
| 361 | .cfg_reg = (uint32_t *) USB30_PHY_AUX_CFG_RCGR, |
| 362 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 363 | .freq_tbl = ftbl_gcc_usb30_phy_aux_clk_src, |
| 364 | .current_freq = &rcg_dummy_freq, |
| 365 | |
| 366 | .c = { |
| 367 | .dbg_name = "usb30_phy_aux_clk_src", |
| 368 | .ops = &clk_ops_rcg, |
| 369 | }, |
| 370 | }; |
| 371 | |
| 372 | static struct branch_clk gcc_usb30_phy_aux_clk = { |
| 373 | .cbcr_reg = (uint32_t *)USB30_PHY_AUX_CBCR, |
| 374 | .has_sibling = 0, |
| 375 | .parent = &usb30_phy_aux_clk_src.c, |
| 376 | |
| 377 | .c = { |
| 378 | .dbg_name = "usb30_phy_aux_clk", |
| 379 | .ops = &clk_ops_branch, |
| 380 | }, |
| 381 | }; |
| 382 | |
| 383 | static struct branch_clk gcc_usb30_pipe_clk = { |
| 384 | .bcr_reg = (uint32_t *) USB30PHY_PHY_BCR, |
| 385 | .cbcr_reg = (uint32_t *) USB30_PHY_PIPE_CBCR, |
| 386 | .has_sibling = 1, |
| 387 | |
| 388 | .c = { |
| 389 | .dbg_name = "usb30_pipe_clk", |
| 390 | .ops = &clk_ops_branch, |
| 391 | }, |
| 392 | }; |
| 393 | |
| 394 | static struct reset_clk gcc_usb30_phy_reset = { |
| 395 | .bcr_reg = (uint32_t )USB30_PHY_BCR, |
| 396 | |
| 397 | .c = { |
| 398 | .dbg_name = "usb30_phy_reset", |
| 399 | .ops = &clk_ops_rst, |
| 400 | }, |
| 401 | }; |
| 402 | |
| 403 | static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = { |
| 404 | .cbcr_reg = (uint32_t *)USB_PHY_CFG_AHB2PHY_CBCR, |
| 405 | .has_sibling = 1, |
| 406 | |
| 407 | .c = { |
| 408 | .dbg_name = "usb_phy_cfg_ahb2phy_clk", |
| 409 | .ops = &clk_ops_branch, |
| 410 | }, |
| 411 | }; |
| 412 | |
| 413 | |
| 414 | /* Clock lookup table */ |
Channagoud Kadabi | 0ffa786 | 2015-03-19 11:58:28 -0700 | [diff] [blame] | 415 | static struct clk_lookup msm_msm8996_clocks[] = |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 416 | { |
| 417 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 418 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 419 | |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame] | 420 | CLK_LOOKUP("uart8_iface_clk", gcc_blsp2_ahb_clk.c), |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 421 | CLK_LOOKUP("uart8_core_clk", gcc_blsp2_uart2_apps_clk.c), |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 422 | |
| 423 | /* USB30 clocks */ |
| 424 | CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c), |
Channagoud Kadabi | df233d2 | 2015-02-11 11:56:48 -0800 | [diff] [blame] | 425 | CLK_LOOKUP("gcc_aggre2_usb3_axi_clk", gcc_aggre2_usb3_axi_clk.c), |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 426 | CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c), |
| 427 | CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c), |
| 428 | CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c), |
| 429 | CLK_LOOKUP("usb30_phy_aux_clk", gcc_usb30_phy_aux_clk.c), |
| 430 | CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c), |
| 431 | CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c), |
| 432 | |
| 433 | CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c), |
| 434 | }; |
| 435 | |
| 436 | void platform_clock_init(void) |
| 437 | { |
Channagoud Kadabi | 0ffa786 | 2015-03-19 11:58:28 -0700 | [diff] [blame] | 438 | clk_init(msm_msm8996_clocks, ARRAY_SIZE(msm_msm8996_clocks)); |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 439 | } |