blob: 9271de317c2c6c79562b1b486fb5803f76a24bce [file] [log] [blame]
Channagoud Kadabi539ef722012-03-29 16:02:50 +05301/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +05302 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29#include <mdp3.h>
30#include <debug.h>
31#include <reg.h>
Channagoud Kadabi539ef722012-03-29 16:02:50 +053032#include <msm_panel.h>
33#include <err.h>
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053034#include <target/display.h>
35#include <platform/timer.h>
36#include <platform/iomap.h>
37
Shashank Mittal4bfb2e32012-04-16 10:56:27 -070038static int mdp_rev;
39
Channagoud Kadabi539ef722012-03-29 16:02:50 +053040int mdp_dsi_video_config(struct msm_panel_info *pinfo,
41 struct fbcon_config *fb)
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053042{
Ajay Dudanib01e5062011-12-03 23:23:42 -080043 unsigned long hsync_period;
44 unsigned long vsync_period;
45 unsigned long vsync_period_intmd;
Channagoud Kadabi539ef722012-03-29 16:02:50 +053046 struct lcdc_panel_info *lcdc = NULL;
47 int ystride = 3;
48
49 if (pinfo == NULL)
50 return ERR_INVALID_ARGS;
51
52 lcdc = &(pinfo->lcdc);
53 if (lcdc == NULL)
54 return ERR_INVALID_ARGS;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053055
Ajay Dudanib01e5062011-12-03 23:23:42 -080056 dprintf(SPEW, "MDP3.0.3 for DSI Video Mode\n");
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053057
Channagoud Kadabi539ef722012-03-29 16:02:50 +053058 hsync_period = pinfo->xres + lcdc->h_front_porch + \
59 lcdc->h_back_porch + 1;
60 vsync_period_intmd = pinfo->yres + lcdc->v_front_porch + \
61 lcdc->v_back_porch + 1;
Ajay Dudanib01e5062011-12-03 23:23:42 -080062 vsync_period = vsync_period_intmd * hsync_period;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053063
Ajay Dudanib01e5062011-12-03 23:23:42 -080064 // ------------- programming MDP_DMA_P_CONFIG ---------------------
65 writel(0x1800bf, MDP_DMA_P_CONFIG); // rgb888
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053066
Ajay Dudanib01e5062011-12-03 23:23:42 -080067 writel(0x00000000, MDP_DMA_P_OUT_XY);
Channagoud Kadabi539ef722012-03-29 16:02:50 +053068 writel(pinfo->yres << 16 | pinfo->xres, MDP_DMA_P_SIZE);
69 writel(MIPI_FB_ADDR, MDP_DMA_P_BUF_ADDR);
70 writel(pinfo->xres * ystride, MDP_DMA_P_BUF_Y_STRIDE);
71 writel(hsync_period << 16 | lcdc->h_pulse_width, \
72 MDP_DSI_VIDEO_HSYNC_CTL);
Ajay Dudanib01e5062011-12-03 23:23:42 -080073 writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
Channagoud Kadabi539ef722012-03-29 16:02:50 +053074 writel(lcdc->v_pulse_width * hsync_period, \
75 MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
76 writel((pinfo->xres + lcdc->h_back_porch - 1) << 16 | \
77 lcdc->h_back_porch, MDP_DSI_VIDEO_DISPLAY_HCTL);
78 writel(lcdc->v_back_porch * hsync_period, \
79 MDP_DSI_VIDEO_DISPLAY_V_START);
80 writel((pinfo->yres + lcdc->v_back_porch) * hsync_period,
Ajay Dudanib01e5062011-12-03 23:23:42 -080081 MDP_DSI_VIDEO_DISPLAY_V_END);
82 writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
83 writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
84 writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
85 // end of cmd mdp
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053086
Channagoud Kadabi539ef722012-03-29 16:02:50 +053087 return 0;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053088}
Ajay Dudanib01e5062011-12-03 23:23:42 -080089
Channagoud Kadabi10189fd2012-05-25 13:33:39 +053090int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
91 struct fbcon_config *fb)
92{
93 int ret = 0;
94 unsigned short pack_pattern = 0x21;
95 unsigned char ystride = 3;
96
97 writel(0x03ffffff, MDP_INTR_ENABLE);
98
99 // ------------- programming MDP_DMA_P_CONFIG ---------------------
100 writel(pack_pattern << 8 | 0x3f | (0 << 25)| (1 << 19) | (1 << 7) , MDP_DMA_P_CONFIG); // rgb888
101 writel(0x00000000, MDP_DMA_P_OUT_XY);
102 writel(pinfo->yres << 16 | pinfo->xres, MDP_DMA_P_SIZE);
103 writel(MIPI_FB_ADDR, MDP_DMA_P_BUF_ADDR);
104
105 writel(pinfo->xres * ystride, MDP_DMA_P_BUF_Y_STRIDE);
106
107 writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
108 writel(0x11, MDP_DSI_CMD_MODE_TRIGGER_EN);
109 mdelay(10);
110
111 return ret;
112}
113
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530114void mdp_disable(void)
115{
Channagoud Kadabif2488462012-06-12 15:22:48 +0530116 if (!target_cont_splash_screen())
117 writel(0x00000000, MDP_DSI_VIDEO_EN);
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530118}
119
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530120int mdp_dsi_video_off(void)
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530121{
Channagoud Kadabif2488462012-06-12 15:22:48 +0530122 if (!target_cont_splash_screen()) {
123 mdp_disable();
124 mdelay(60);
125 writel(0x00000000, MDP_INTR_ENABLE);
126 writel(0x01ffffff, MDP_INTR_CLEAR);
127 }
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530128 return NO_ERROR;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530129}
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700130
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530131int mdp_dsi_cmd_off(void)
132{
Channagoud Kadabif2488462012-06-12 15:22:48 +0530133 if (!target_cont_splash_screen()) {
134 mdp_dma_off();
135 /*
136 * Allow sometime for the DMA channel to
137 * stop the data transfer
138 */
139 mdelay(10);
140 writel(0x00000000, MDP_INTR_ENABLE);
141 writel(0x01ffffff, MDP_INTR_CLEAR);
142 }
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530143 return NO_ERROR;
144}
145
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700146void mdp_set_revision(int rev)
147{
148 mdp_rev = rev;
149}
150
151int mdp_get_revision(void)
152{
153 return mdp_rev;
154}
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530155
156int mdp_dsi_video_on()
157{
158 int ret = 0;
159
160 writel(0x00000001, MDP_DSI_VIDEO_EN);
161
162 return ret;
163}
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530164
165int mdp_dma_on()
166{
167 int ret = 0;
168
169 writel(0x00000001, MDP_DMA_P_START);
170
171 return ret;
172}
173
174int mdp_dma_off()
175{
176 int ret = 0;
177
Channagoud Kadabif2488462012-06-12 15:22:48 +0530178 if (!target_cont_splash_screen())
179 writel(0x00000000, MDP_DMA_P_START);
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530180
181 return ret;
182}