wangxl | 1ddbd09 | 2015-02-03 20:31:24 +0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Francesco Salvatore | 6c17a23 | 2018-12-11 17:30:22 +0100 | [diff] [blame] | 2 | * Copyright 2018 Fairphone B.V. |
wangxl | 1ddbd09 | 2015-02-03 20:31:24 +0800 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
| 13 | * * Neither the name of The Linux Foundation nor the names of its |
| 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <platform/iomap.h> |
| 32 | #include <platform/irqs.h> |
| 33 | #include <platform/gpio.h> |
| 34 | #include <reg.h> |
| 35 | #include <target.h> |
| 36 | #include <platform.h> |
| 37 | #include <dload_util.h> |
| 38 | #include <uart_dm.h> |
| 39 | #include <mmc.h> |
| 40 | #include <spmi.h> |
| 41 | #include <board.h> |
| 42 | #include <smem.h> |
| 43 | #include <baseband.h> |
| 44 | #include <dev/keys.h> |
| 45 | #include <pm8x41.h> |
Francesco Salvatore | 6c17a23 | 2018-12-11 17:30:22 +0100 | [diff] [blame] | 46 | #include <target/rgb_led.h> |
wangxl | 1ddbd09 | 2015-02-03 20:31:24 +0800 | [diff] [blame] | 47 | #include <crypto5_wrapper.h> |
| 48 | #include <hsusb.h> |
| 49 | #include <clock.h> |
| 50 | #include <partition_parser.h> |
| 51 | #include <scm.h> |
| 52 | #include <platform/clock.h> |
| 53 | #include <platform/gpio.h> |
| 54 | #include <stdlib.h> |
| 55 | |
| 56 | enum hw_platform_subtype |
| 57 | { |
| 58 | HW_PLATFORM_SUBTYPE_CDP_INTERPOSER = 8, |
| 59 | }; |
| 60 | |
| 61 | extern bool target_use_signed_kernel(void); |
| 62 | static void set_sdc_power_ctrl(); |
| 63 | |
| 64 | static unsigned int target_id; |
| 65 | static uint32_t pmic_ver; |
| 66 | |
| 67 | #if MMC_SDHCI_SUPPORT |
| 68 | struct mmc_device *dev; |
| 69 | #endif |
| 70 | |
| 71 | #define PMIC_ARB_CHANNEL_NUM 0 |
| 72 | #define PMIC_ARB_OWNER_ID 0 |
| 73 | |
| 74 | #define WDOG_DEBUG_DISABLE_BIT 17 |
| 75 | |
| 76 | #define CE_INSTANCE 2 |
| 77 | #define CE_EE 1 |
| 78 | #define CE_FIFO_SIZE 64 |
| 79 | #define CE_READ_PIPE 3 |
| 80 | #define CE_WRITE_PIPE 2 |
| 81 | #define CE_READ_PIPE_LOCK_GRP 0 |
| 82 | #define CE_WRITE_PIPE_LOCK_GRP 0 |
| 83 | #define CE_ARRAY_SIZE 20 |
| 84 | |
| 85 | #ifdef SSD_ENABLE |
| 86 | #define SSD_CE_INSTANCE_1 1 |
| 87 | #define SSD_PARTITION_SIZE 8192 |
| 88 | #endif |
| 89 | |
| 90 | #define FASTBOOT_MODE 0x77665500 |
| 91 | |
| 92 | #define BOARD_SOC_VERSION1(soc_rev) (soc_rev >= 0x10000 && soc_rev < 0x20000) |
| 93 | |
| 94 | #if MMC_SDHCI_SUPPORT |
| 95 | static uint32_t mmc_sdhci_base[] = |
| 96 | { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE, MSM_SDC3_SDHCI_BASE, MSM_SDC4_SDHCI_BASE }; |
| 97 | #endif |
| 98 | |
| 99 | static uint32_t mmc_sdc_base[] = |
| 100 | { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE }; |
| 101 | |
| 102 | static uint32_t mmc_sdc_pwrctl_irq[] = |
| 103 | { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ, SDCC3_PWRCTL_IRQ, SDCC4_PWRCTL_IRQ }; |
| 104 | |
| 105 | void target_early_init(void) |
| 106 | { |
| 107 | #if WITH_DEBUG_UART |
| 108 | uart_dm_init(1, 0, BLSP1_UART1_BASE); |
| 109 | #endif |
| 110 | } |
| 111 | |
| 112 | /* Check for 8974 chip */ |
| 113 | static int target_is_8974() |
| 114 | { |
| 115 | uint32_t platform = board_platform_id(); |
| 116 | int ret = 0; |
| 117 | |
| 118 | switch(platform) |
| 119 | { |
| 120 | case APQ8074: |
| 121 | case MSM8274: |
| 122 | case MSM8674: |
| 123 | case MSM8974: |
| 124 | ret = 1; |
| 125 | break; |
| 126 | default: |
| 127 | ret = 0; |
| 128 | }; |
| 129 | |
| 130 | return ret; |
| 131 | } |
| 132 | |
| 133 | /* Return 1 if vol_up pressed */ |
| 134 | static int target_volume_up() |
| 135 | { |
| 136 | uint8_t status = 0; |
| 137 | struct pm8x41_gpio gpio; |
| 138 | |
| 139 | /* CDP vol_up seems to be always grounded. So gpio status is read as 0, |
| 140 | * whether key is pressed or not. |
| 141 | * Ignore volume_up key on CDP for now. |
| 142 | */ |
| 143 | if (board_hardware_id() == HW_PLATFORM_SURF) |
| 144 | return 0; |
| 145 | |
| 146 | /* Configure the GPIO */ |
| 147 | gpio.direction = PM_GPIO_DIR_IN; |
| 148 | gpio.function = 0; |
| 149 | gpio.pull = PM_GPIO_PULL_UP_30; |
| 150 | gpio.vin_sel = 2; |
| 151 | |
| 152 | pm8x41_gpio_config(5, &gpio); |
| 153 | |
| 154 | /* Wait for the pmic gpio config to take effect */ |
| 155 | thread_sleep(1); |
| 156 | |
| 157 | /* Get status of P_GPIO_5 */ |
| 158 | pm8x41_gpio_get(5, &status); |
| 159 | |
| 160 | return !status; /* active low */ |
| 161 | } |
| 162 | |
| 163 | /* Return 1 if vol_down pressed */ |
| 164 | uint32_t target_volume_down() |
| 165 | { |
wangxl | 6843252 | 2015-02-04 11:04:42 +0800 | [diff] [blame] | 166 | uint8_t status = 0; |
| 167 | struct pm8x41_gpio gpio; |
| 168 | |
| 169 | if (board_hardware_id() == HW_PLATFORM_SURF) |
| 170 | return 0; |
| 171 | |
| 172 | /* Configure the GPIO */ |
| 173 | gpio.direction = PM_GPIO_DIR_IN; |
| 174 | gpio.function = 0; |
| 175 | gpio.pull = PM_GPIO_PULL_UP_30; |
| 176 | gpio.vin_sel = 2; |
| 177 | |
| 178 | pm8x41_gpio_config(2, &gpio); |
| 179 | |
| 180 | /* Wait for the pmic gpio config to take effect */ |
| 181 | thread_sleep(1); |
| 182 | |
| 183 | /* Get status of P_GPIO_2 */ |
| 184 | pm8x41_gpio_get(2, &status); |
| 185 | |
| 186 | return !status; /* active low */ |
wangxl | 1ddbd09 | 2015-02-03 20:31:24 +0800 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | static void target_keystatus() |
| 190 | { |
| 191 | keys_init(); |
| 192 | |
| 193 | if(target_volume_down()) |
| 194 | keys_post_event(KEY_VOLUMEDOWN, 1); |
| 195 | |
| 196 | if(target_volume_up()) |
| 197 | keys_post_event(KEY_VOLUMEUP, 1); |
| 198 | } |
| 199 | |
| 200 | /* Set up params for h/w CE. */ |
| 201 | void target_crypto_init_params() |
| 202 | { |
| 203 | struct crypto_init_params ce_params; |
| 204 | |
| 205 | /* Set up base addresses and instance. */ |
| 206 | ce_params.crypto_instance = CE_INSTANCE; |
| 207 | ce_params.crypto_base = MSM_CE2_BASE; |
| 208 | ce_params.bam_base = MSM_CE2_BAM_BASE; |
| 209 | |
| 210 | /* Set up BAM config. */ |
| 211 | ce_params.bam_ee = CE_EE; |
| 212 | ce_params.pipes.read_pipe = CE_READ_PIPE; |
| 213 | ce_params.pipes.write_pipe = CE_WRITE_PIPE; |
| 214 | ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP; |
| 215 | ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP; |
| 216 | |
| 217 | /* Assign buffer sizes. */ |
| 218 | ce_params.num_ce = CE_ARRAY_SIZE; |
| 219 | ce_params.read_fifo_size = CE_FIFO_SIZE; |
| 220 | ce_params.write_fifo_size = CE_FIFO_SIZE; |
| 221 | |
| 222 | /* BAM is initialized by TZ for this platform. |
| 223 | * Do not do it again as the initialization address space |
| 224 | * is locked. |
| 225 | */ |
| 226 | ce_params.do_bam_init = 0; |
| 227 | |
| 228 | crypto_init_params(&ce_params); |
| 229 | } |
| 230 | |
| 231 | crypto_engine_type board_ce_type(void) |
| 232 | { |
| 233 | return CRYPTO_ENGINE_TYPE_HW; |
| 234 | } |
| 235 | |
| 236 | #if MMC_SDHCI_SUPPORT |
| 237 | static void target_mmc_sdhci_init() |
| 238 | { |
| 239 | struct mmc_config_data config = {0}; |
| 240 | uint32_t soc_ver = 0; |
| 241 | |
| 242 | soc_ver = board_soc_version(); |
| 243 | |
| 244 | /* |
| 245 | * 8974 v1 fluid devices, have a hardware bug |
| 246 | * which limits the bus width to 4 bit. |
| 247 | */ |
| 248 | switch(board_hardware_id()) |
| 249 | { |
| 250 | case HW_PLATFORM_FLUID: |
| 251 | if (target_is_8974() && BOARD_SOC_VERSION1(soc_ver)) |
| 252 | config.bus_width = DATA_BUS_WIDTH_4BIT; |
| 253 | else |
| 254 | config.bus_width = DATA_BUS_WIDTH_8BIT; |
| 255 | break; |
| 256 | default: |
| 257 | config.bus_width = DATA_BUS_WIDTH_8BIT; |
| 258 | }; |
| 259 | |
| 260 | /* Trying Slot 1*/ |
| 261 | config.slot = 1; |
| 262 | /* |
| 263 | * For 8974 AC platform the software clock |
| 264 | * plan recommends to use the following frequencies: |
| 265 | * 200 MHz --> 192 MHZ |
| 266 | * 400 MHZ --> 384 MHZ |
| 267 | * only for emmc slot |
| 268 | */ |
| 269 | if (platform_is_8974ac()) |
| 270 | config.max_clk_rate = MMC_CLK_192MHZ; |
| 271 | else |
| 272 | config.max_clk_rate = MMC_CLK_200MHZ; |
| 273 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 274 | config.pwrctl_base = mmc_sdc_base[config.slot - 1]; |
| 275 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 276 | |
| 277 | if (!(dev = mmc_init(&config))) { |
| 278 | /* Trying Slot 2 next */ |
| 279 | config.slot = 2; |
| 280 | config.max_clk_rate = MMC_CLK_200MHZ; |
| 281 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 282 | config.pwrctl_base = mmc_sdc_base[config.slot - 1]; |
| 283 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 284 | |
| 285 | if (!(dev = mmc_init(&config))) { |
| 286 | dprintf(CRITICAL, "mmc init failed!"); |
| 287 | ASSERT(0); |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | /* |
| 292 | * MMC initialization is complete, read the partition table info |
| 293 | */ |
| 294 | if (partition_read_table()) { |
| 295 | dprintf(CRITICAL, "Error reading the partition table info\n"); |
| 296 | ASSERT(0); |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | struct mmc_device *target_mmc_device() |
| 301 | { |
| 302 | return dev; |
| 303 | } |
| 304 | |
| 305 | #else |
| 306 | static void target_mmc_mci_init() |
| 307 | { |
| 308 | uint32_t base_addr; |
| 309 | uint8_t slot; |
| 310 | |
| 311 | /* Trying Slot 1 */ |
| 312 | slot = 1; |
| 313 | base_addr = mmc_sdc_base[slot - 1]; |
| 314 | |
| 315 | if (mmc_boot_main(slot, base_addr)) |
| 316 | { |
| 317 | /* Trying Slot 2 next */ |
| 318 | slot = 2; |
| 319 | base_addr = mmc_sdc_base[slot - 1]; |
| 320 | if (mmc_boot_main(slot, base_addr)) { |
| 321 | dprintf(CRITICAL, "mmc init failed!"); |
| 322 | ASSERT(0); |
| 323 | } |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | /* |
| 328 | * Function to set the capabilities for the host |
| 329 | */ |
| 330 | void target_mmc_caps(struct mmc_host *host) |
| 331 | { |
| 332 | uint32_t soc_ver = 0; |
| 333 | |
| 334 | soc_ver = board_soc_version(); |
| 335 | |
| 336 | /* |
| 337 | * 8974 v1 fluid devices, have a hardware bug |
| 338 | * which limits the bus width to 4 bit. |
| 339 | */ |
| 340 | switch(board_hardware_id()) |
| 341 | { |
| 342 | case HW_PLATFORM_FLUID: |
| 343 | if (target_is_8974() && BOARD_SOC_VERSION1(soc_ver)) |
| 344 | host->caps.bus_width = MMC_BOOT_BUS_WIDTH_4_BIT; |
| 345 | else |
| 346 | host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT; |
| 347 | break; |
| 348 | default: |
| 349 | host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT; |
| 350 | }; |
| 351 | |
| 352 | host->caps.ddr_mode = 1; |
| 353 | host->caps.hs200_mode = 1; |
| 354 | host->caps.hs_clk_rate = MMC_CLK_96MHZ; |
| 355 | } |
| 356 | #endif |
| 357 | |
chenxl0723 | 48dc432 | 2015-05-11 13:48:24 +0800 | [diff] [blame] | 358 | #define DRV2603_VIBRATOR_EN 86 |
| 359 | #define DRV2603_VIBRATOR_PWM 85 |
| 360 | #define FUNC_GPIO 0 |
| 361 | |
| 362 | /* Vibrator enable */ |
| 363 | void vibrator_enable() |
| 364 | { |
| 365 | uint32_t pm8x41_ldo_base = 0x13F00; |
| 366 | struct pm8x41_ldo ldo18 = LDO(pm8x41_ldo_base + 0x100 * 18, 0); |
| 367 | /* Turn on LDO18 for Vibrator */ |
| 368 | pm8x41_ldo_set_voltage(&ldo18, 2850000); |
| 369 | pm8x41_ldo_control(&ldo18, 1); |
| 370 | dprintf(INFO,"%s \n",__func__); |
| 371 | udelay(200); |
| 372 | gpio_tlmm_config(DRV2603_VIBRATOR_PWM, FUNC_GPIO, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE); |
| 373 | gpio_set(85, 2); |
| 374 | udelay(200); |
| 375 | gpio_tlmm_config(DRV2603_VIBRATOR_EN, FUNC_GPIO, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE); |
| 376 | gpio_set(86, 2); |
| 377 | mdelay(200); |
| 378 | gpio_tlmm_config(DRV2603_VIBRATOR_EN, FUNC_GPIO, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE); |
| 379 | gpio_tlmm_config(DRV2603_VIBRATOR_PWM, FUNC_GPIO, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE); |
| 380 | pm8x41_ldo_control(&ldo18, 0); |
| 381 | } |
| 382 | /* Vibrator end */ |
wangxl | 1ddbd09 | 2015-02-03 20:31:24 +0800 | [diff] [blame] | 383 | |
| 384 | void target_init(void) |
| 385 | { |
| 386 | dprintf(INFO, "target_init()\n"); |
| 387 | |
| 388 | spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID); |
| 389 | |
| 390 | /* Save PM8941 version info. */ |
| 391 | pmic_ver = pm8x41_get_pmic_rev(); |
| 392 | |
| 393 | target_keystatus(); |
| 394 | |
| 395 | if (target_use_signed_kernel()) |
| 396 | target_crypto_init_params(); |
| 397 | |
chenxl0723 | 48dc432 | 2015-05-11 13:48:24 +0800 | [diff] [blame] | 398 | /* Vibrator start */ |
wangxl | 4b8e0d3 | 2016-01-05 17:14:27 +0800 | [diff] [blame] | 399 | if (!target_pause_for_battery_charge()){ |
| 400 | dprintf(INFO, "calling vibrator enable\n"); |
| 401 | vibrator_enable(); |
| 402 | } |
chenxl0723 | 48dc432 | 2015-05-11 13:48:24 +0800 | [diff] [blame] | 403 | /* Vibrator end */ |
| 404 | |
wangxl | 1ddbd09 | 2015-02-03 20:31:24 +0800 | [diff] [blame] | 405 | /* |
| 406 | * Set drive strength & pull ctrl for |
| 407 | * emmc |
| 408 | */ |
| 409 | set_sdc_power_ctrl(); |
| 410 | |
| 411 | #if MMC_SDHCI_SUPPORT |
| 412 | target_mmc_sdhci_init(); |
| 413 | #else |
| 414 | target_mmc_mci_init(); |
| 415 | #endif |
| 416 | } |
| 417 | |
| 418 | unsigned board_machtype(void) |
| 419 | { |
| 420 | return target_id; |
| 421 | } |
| 422 | |
| 423 | /* Do any target specific intialization needed before entering fastboot mode */ |
| 424 | #ifdef SSD_ENABLE |
| 425 | static void ssd_load_keystore_from_emmc() |
| 426 | { |
| 427 | uint64_t ptn = 0; |
| 428 | int index = -1; |
| 429 | uint32_t size = SSD_PARTITION_SIZE; |
| 430 | int ret = -1; |
| 431 | |
| 432 | uint32_t *buffer = (uint32_t *)memalign(CACHE_LINE, |
| 433 | ROUNDUP(SSD_PARTITION_SIZE, CACHE_LINE)); |
| 434 | |
| 435 | if (!buffer) { |
| 436 | dprintf(CRITICAL, "Error Allocating memory for SSD buffer\n"); |
| 437 | ASSERT(0); |
| 438 | } |
| 439 | |
| 440 | index = partition_get_index("ssd"); |
| 441 | |
| 442 | ptn = partition_get_offset(index); |
| 443 | if(ptn == 0){ |
| 444 | dprintf(CRITICAL,"ERROR: ssd parition not found"); |
| 445 | return; |
| 446 | } |
| 447 | |
| 448 | if(mmc_read(ptn, buffer, size)){ |
| 449 | dprintf(CRITICAL,"ERROR:Cannot read data\n"); |
| 450 | return; |
| 451 | } |
| 452 | |
| 453 | ret = scm_protect_keystore((uint32_t *)&buffer[0],size); |
| 454 | if(ret != 0) |
| 455 | dprintf(CRITICAL,"ERROR: scm_protect_keystore Failed"); |
| 456 | |
| 457 | free(buffer); |
| 458 | } |
| 459 | #endif |
| 460 | |
| 461 | void target_fastboot_init(void) |
| 462 | { |
| 463 | /* Set the BOOT_DONE flag in PM8921 */ |
| 464 | pm8x41_set_boot_done(); |
| 465 | |
| 466 | #ifdef SSD_ENABLE |
| 467 | clock_ce_enable(SSD_CE_INSTANCE_1); |
| 468 | ssd_load_keystore_from_emmc(); |
| 469 | #endif |
Francesco Salvatore | 6c17a23 | 2018-12-11 17:30:22 +0100 | [diff] [blame] | 470 | |
| 471 | /* Vibration pattern, 3 fast vibes in a row */ |
| 472 | vibrator_enable(); |
| 473 | thread_sleep(150); |
| 474 | vibrator_enable(); |
| 475 | thread_sleep(150); |
| 476 | vibrator_enable(); |
| 477 | thread_sleep(150); |
| 478 | /* Enable blinking of Blue LED */ |
| 479 | led_init(); |
| 480 | led_blink_enable(RGB_LED_VALUE_BLUE, 0x06, 0x2C); // 0x06 means 0.25 KHz PWM frequency (4 secs duty cycle duration), 0x2C means about 70% of the duty cycle |
wangxl | 1ddbd09 | 2015-02-03 20:31:24 +0800 | [diff] [blame] | 481 | } |
| 482 | |
| 483 | /* Detect the target type */ |
| 484 | void target_detect(struct board_data *board) |
| 485 | { |
| 486 | board->target = LINUX_MACHTYPE_UNKNOWN; |
| 487 | } |
| 488 | |
| 489 | /* Detect the modem type */ |
| 490 | void target_baseband_detect(struct board_data *board) |
| 491 | { |
| 492 | uint32_t platform; |
| 493 | uint32_t platform_subtype; |
| 494 | |
| 495 | platform = board->platform; |
| 496 | |
| 497 | switch(platform) { |
| 498 | case MSM8974: |
| 499 | case MSM8274: |
| 500 | case MSM8674: |
| 501 | case MSM8274AA: |
| 502 | case MSM8274AB: |
| 503 | case MSM8274AC: |
| 504 | case MSM8674AA: |
| 505 | case MSM8674AB: |
| 506 | case MSM8674AC: |
| 507 | case MSM8974AA: |
| 508 | case MSM8974AB: |
| 509 | case MSM8974AC: |
| 510 | case MSMSAMARIUM2: |
| 511 | case MSMSAMARIUM9: |
| 512 | board->baseband = BASEBAND_MSM; |
| 513 | break; |
| 514 | case APQ8074: |
| 515 | case APQ8074AA: |
| 516 | case APQ8074AB: |
| 517 | case APQ8074AC: |
| 518 | case MSMSAMARIUM0: |
| 519 | board->baseband = BASEBAND_APQ; |
| 520 | break; |
| 521 | default: |
| 522 | dprintf(CRITICAL, "Platform type: %u is not supported\n",platform); |
| 523 | ASSERT(0); |
| 524 | }; |
| 525 | } |
| 526 | |
| 527 | unsigned target_baseband() |
| 528 | { |
| 529 | return board_baseband(); |
| 530 | } |
| 531 | |
| 532 | void target_serialno(unsigned char *buf) |
| 533 | { |
| 534 | unsigned int serialno; |
| 535 | if (target_is_emmc_boot()) { |
| 536 | serialno = mmc_get_psn(); |
| 537 | snprintf((char *)buf, 13, "%x", serialno); |
| 538 | } |
| 539 | } |
| 540 | |
| 541 | unsigned check_reboot_mode(void) |
| 542 | { |
| 543 | uint32_t restart_reason = 0; |
| 544 | uint32_t soc_ver = 0; |
| 545 | uint32_t restart_reason_addr; |
| 546 | |
| 547 | soc_ver = board_soc_version(); |
| 548 | |
| 549 | if (target_is_8974() && BOARD_SOC_VERSION1(soc_ver)) |
| 550 | restart_reason_addr = RESTART_REASON_ADDR; |
| 551 | else |
| 552 | restart_reason_addr = RESTART_REASON_ADDR_V2; |
| 553 | |
| 554 | /* Read reboot reason and scrub it */ |
| 555 | restart_reason = readl(restart_reason_addr); |
| 556 | writel(0x00, restart_reason_addr); |
| 557 | |
| 558 | return restart_reason; |
| 559 | } |
| 560 | |
| 561 | void reboot_device(unsigned reboot_reason) |
| 562 | { |
| 563 | uint32_t soc_ver = 0; |
| 564 | uint8_t reset_type = 0; |
| 565 | |
| 566 | soc_ver = board_soc_version(); |
| 567 | |
| 568 | /* Write the reboot reason */ |
| 569 | if (target_is_8974() && BOARD_SOC_VERSION1(soc_ver)) |
| 570 | writel(reboot_reason, RESTART_REASON_ADDR); |
| 571 | else |
| 572 | writel(reboot_reason, RESTART_REASON_ADDR_V2); |
| 573 | |
| 574 | if(reboot_reason == FASTBOOT_MODE) |
| 575 | reset_type = PON_PSHOLD_WARM_RESET; |
| 576 | else |
| 577 | reset_type = PON_PSHOLD_HARD_RESET; |
| 578 | |
| 579 | /* Configure PMIC for warm reset */ |
| 580 | if (target_is_8974() && (pmic_ver == PM8X41_VERSION_V2)) |
| 581 | pm8x41_v2_reset_configure(reset_type); |
| 582 | else |
| 583 | pm8x41_reset_configure(reset_type); |
| 584 | |
| 585 | /* Drop PS_HOLD for MSM */ |
| 586 | writel(0x00, MPM2_MPM_PS_HOLD); |
| 587 | |
| 588 | mdelay(5000); |
| 589 | |
| 590 | dprintf(CRITICAL, "Rebooting failed\n"); |
| 591 | } |
| 592 | |
| 593 | int set_download_mode(enum dload_mode mode) |
| 594 | { |
| 595 | dload_util_write_cookie(mode == NORMAL_DLOAD ? |
| 596 | DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode); |
| 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | /* Check if MSM needs VBUS mimic for USB */ |
| 602 | static int target_needs_vbus_mimic() |
| 603 | { |
| 604 | if (target_is_8974()) |
| 605 | return 0; |
| 606 | |
| 607 | return 1; |
| 608 | } |
| 609 | |
| 610 | /* Do target specific usb initialization */ |
| 611 | void target_usb_init(void) |
| 612 | { |
| 613 | uint32_t val; |
| 614 | |
| 615 | /* Enable secondary USB PHY on DragonBoard8074 */ |
| 616 | if (board_hardware_id() == HW_PLATFORM_DRAGON) { |
| 617 | /* Route ChipIDea to use secondary USB HS port2 */ |
| 618 | writel_relaxed(1, USB2_PHY_SEL); |
| 619 | |
| 620 | /* Enable access to secondary PHY by clamping the low |
| 621 | * voltage interface between DVDD of the PHY and Vddcx |
| 622 | * (set bit16 (USB2_PHY_HS2_DIG_CLAMP_N_2) = 1) */ |
| 623 | writel_relaxed(readl_relaxed(USB_OTG_HS_PHY_SEC_CTRL) |
| 624 | | 0x00010000, USB_OTG_HS_PHY_SEC_CTRL); |
| 625 | |
| 626 | /* Perform power-on-reset of the PHY. |
| 627 | * Delay values are arbitrary */ |
| 628 | writel_relaxed(readl_relaxed(USB_OTG_HS_PHY_CTRL)|1, |
| 629 | USB_OTG_HS_PHY_CTRL); |
| 630 | thread_sleep(10); |
| 631 | writel_relaxed(readl_relaxed(USB_OTG_HS_PHY_CTRL) & 0xFFFFFFFE, |
| 632 | USB_OTG_HS_PHY_CTRL); |
| 633 | thread_sleep(10); |
| 634 | |
| 635 | /* Enable HSUSB PHY port for ULPI interface, |
| 636 | * then configure related parameters within the PHY */ |
| 637 | writel_relaxed(((readl_relaxed(USB_PORTSC) & 0xC0000000) |
| 638 | | 0x8c000004), USB_PORTSC); |
| 639 | } |
| 640 | |
| 641 | if (target_needs_vbus_mimic()) |
| 642 | { |
| 643 | /* Select and enable external configuration with USB PHY */ |
| 644 | ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET); |
| 645 | |
| 646 | /* Enable sess_vld */ |
| 647 | val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN; |
| 648 | writel(val, USB_GENCONFIG_2); |
| 649 | |
| 650 | /* Enable external vbus configuration in the LINK */ |
| 651 | val = readl(USB_USBCMD); |
| 652 | val |= SESS_VLD_CTRL; |
| 653 | writel(val, USB_USBCMD); |
| 654 | } |
| 655 | } |
| 656 | |
| 657 | uint8_t target_panel_auto_detect_enabled() |
| 658 | { |
| 659 | switch(board_hardware_id()) |
| 660 | { |
| 661 | case HW_PLATFORM_SURF: |
| 662 | case HW_PLATFORM_MTP: |
| 663 | case HW_PLATFORM_FLUID: |
| 664 | return 1; |
| 665 | break; |
| 666 | default: |
| 667 | return 0; |
| 668 | break; |
| 669 | } |
| 670 | return 0; |
| 671 | } |
| 672 | |
| 673 | uint8_t target_is_edp() |
| 674 | { |
| 675 | switch(board_hardware_id()) |
| 676 | { |
| 677 | case HW_PLATFORM_LIQUID: |
| 678 | return 1; |
| 679 | break; |
| 680 | default: |
| 681 | return 0; |
| 682 | break; |
| 683 | } |
| 684 | return 0; |
| 685 | } |
| 686 | |
| 687 | static uint8_t splash_override; |
| 688 | /* Returns 1 if target supports continuous splash screen. */ |
| 689 | int target_cont_splash_screen() |
| 690 | { |
| 691 | uint8_t splash_screen = 0; |
| 692 | if(!splash_override) { |
| 693 | switch(board_hardware_id()) |
| 694 | { |
| 695 | case HW_PLATFORM_SURF: |
| 696 | case HW_PLATFORM_MTP: |
| 697 | case HW_PLATFORM_FLUID: |
| 698 | case HW_PLATFORM_DRAGON: |
| 699 | case HW_PLATFORM_LIQUID: |
| 700 | dprintf(SPEW, "Target_cont_splash=1\n"); |
| 701 | splash_screen = 1; |
| 702 | break; |
| 703 | default: |
| 704 | dprintf(SPEW, "Target_cont_splash=0\n"); |
| 705 | splash_screen = 0; |
| 706 | } |
| 707 | } |
| 708 | return splash_screen; |
| 709 | } |
| 710 | |
| 711 | void target_force_cont_splash_disable(uint8_t override) |
| 712 | { |
| 713 | splash_override = override; |
| 714 | } |
| 715 | |
| 716 | unsigned target_pause_for_battery_charge(void) |
| 717 | { |
| 718 | uint8_t pon_reason = pm8x41_get_pon_reason(); |
Ameya Thakur | 5969c9a | 2013-06-25 13:46:21 -0700 | [diff] [blame] | 719 | uint8_t is_cold_boot = pm8x41_get_is_cold_boot(); |
Ameya Thakur | fe7e8d3 | 2013-07-17 16:53:53 -0700 | [diff] [blame] | 720 | dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__, |
| 721 | pon_reason, is_cold_boot); |
Ameya Thakur | 0ed4bb2 | 2013-07-19 17:52:51 -0700 | [diff] [blame] | 722 | /* In case of fastboot reboot,adb reboot or if we see the power key |
| 723 | * pressed we do not want go into charger mode. |
Ameya Thakur | fe7e8d3 | 2013-07-17 16:53:53 -0700 | [diff] [blame] | 724 | * fastboot reboot is warm boot with PON hard reset bit not set |
| 725 | * adb reboot is a cold boot with PON hard reset bit set |
| 726 | */ |
Ameya Thakur | 0ed4bb2 | 2013-07-19 17:52:51 -0700 | [diff] [blame] | 727 | if (is_cold_boot && |
| 728 | (!(pon_reason & HARD_RST)) && |
| 729 | (!(pon_reason & KPDPWR_N)) && |
Ameya Thakur | fe7e8d3 | 2013-07-17 16:53:53 -0700 | [diff] [blame] | 730 | ((pon_reason & USB_CHG) || (pon_reason & DC_CHG))) |
| 731 | return 1; |
| 732 | else |
| 733 | return 0; |
wangxl | 1ddbd09 | 2015-02-03 20:31:24 +0800 | [diff] [blame] | 734 | } |
| 735 | |
| 736 | void target_uninit(void) |
| 737 | { |
| 738 | #if MMC_SDHCI_SUPPORT |
| 739 | mmc_put_card_to_sleep(dev); |
| 740 | #else |
| 741 | mmc_put_card_to_sleep(); |
| 742 | #endif |
| 743 | #ifdef SSD_ENABLE |
| 744 | clock_ce_disable(SSD_CE_INSTANCE_1); |
| 745 | #endif |
| 746 | if (crypto_initialized()) |
| 747 | crypto_eng_cleanup(); |
| 748 | |
| 749 | /* Disable HC mode before jumping to kernel */ |
| 750 | sdhci_mode_disable(&dev->host); |
| 751 | } |
| 752 | |
| 753 | void shutdown_device() |
| 754 | { |
| 755 | dprintf(CRITICAL, "Going down for shutdown.\n"); |
| 756 | |
| 757 | /* Configure PMIC for shutdown. */ |
| 758 | if (target_is_8974() && (pmic_ver == PM8X41_VERSION_V2)) |
| 759 | pm8x41_v2_reset_configure(PON_PSHOLD_SHUTDOWN); |
| 760 | else |
| 761 | pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN); |
| 762 | |
| 763 | /* Drop PS_HOLD for MSM */ |
| 764 | writel(0x00, MPM2_MPM_PS_HOLD); |
| 765 | |
| 766 | mdelay(5000); |
| 767 | |
| 768 | dprintf(CRITICAL, "Shutdown failed\n"); |
| 769 | } |
| 770 | |
| 771 | static void set_sdc_power_ctrl() |
| 772 | { |
| 773 | uint8_t tlmm_hdrv_clk = 0; |
| 774 | uint32_t platform_id = 0; |
| 775 | |
| 776 | platform_id = board_platform_id(); |
| 777 | |
| 778 | switch(platform_id) |
| 779 | { |
| 780 | case MSM8274AA: |
| 781 | case MSM8274AB: |
| 782 | case MSM8674AA: |
| 783 | case MSM8674AB: |
| 784 | case MSM8974AA: |
| 785 | case MSM8974AB: |
| 786 | if (board_hardware_id() == HW_PLATFORM_MTP) |
| 787 | tlmm_hdrv_clk = TLMM_CUR_VAL_10MA; |
| 788 | else |
| 789 | tlmm_hdrv_clk = TLMM_CUR_VAL_16MA; |
| 790 | break; |
| 791 | default: |
| 792 | tlmm_hdrv_clk = TLMM_CUR_VAL_16MA; |
| 793 | }; |
| 794 | |
| 795 | /* Drive strength configs for sdc pins */ |
| 796 | struct tlmm_cfgs sdc1_hdrv_cfg[] = |
| 797 | { |
| 798 | { SDC1_CLK_HDRV_CTL_OFF, tlmm_hdrv_clk, TLMM_HDRV_MASK }, |
| 799 | { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK }, |
| 800 | { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK }, |
| 801 | }; |
| 802 | |
| 803 | /* Pull configs for sdc pins */ |
| 804 | struct tlmm_cfgs sdc1_pull_cfg[] = |
| 805 | { |
| 806 | { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK }, |
| 807 | { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK }, |
| 808 | { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK }, |
| 809 | }; |
| 810 | |
| 811 | struct tlmm_cfgs sdc1_rclk_cfg[] = |
| 812 | { |
| 813 | { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK }, |
| 814 | }; |
| 815 | |
| 816 | /* Set the drive strength & pull control values */ |
| 817 | tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg)); |
| 818 | tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg)); |
| 819 | |
| 820 | /* RCLK is supported only with 8974 pro, set rclk to pull down |
| 821 | * only for 8974 pro targets |
| 822 | */ |
| 823 | if (!platform_is_8974()) |
| 824 | tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg)); |
| 825 | } |
| 826 | |
| 827 | int emmc_recovery_init(void) |
| 828 | { |
| 829 | return _emmc_recovery_init(); |
| 830 | } |
| 831 | |
| 832 | void target_usb_stop(void) |
| 833 | { |
| 834 | uint32_t platform = board_platform_id(); |
| 835 | |
| 836 | /* Disable VBUS mimicing in the controller. */ |
| 837 | if (target_needs_vbus_mimic()) |
| 838 | ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR); |
| 839 | } |