| Channagoud Kadabi | c14b2a5 | 2015-01-06 15:05:12 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013,2015 The Linux Foundation. All rights reserved. |
| Amol Jadi | f3d5a89 | 2013-07-23 16:09:44 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | #ifndef __DWC_USB30_QSCRATCH_HWIO_H__ |
| 29 | #define __DWC_USB30_QSCRATCH_HWIO_H__ |
| 30 | |
| 31 | |
| 32 | /* Macros to simplify wrapper reg read */ |
| 33 | #define REG_READ(_dev, _reg) readl(HWIO_##_reg##_ADDR(_dev->base)) |
| 34 | #define REG_READI(_dev, _reg, _index) readl(HWIO_##_reg##_ADDR(_dev->base, _index)) |
| 35 | |
| 36 | /* Macros to simplify wrapper reg write */ |
| 37 | #define REG_WRITE(_dev, _reg, _value) writel(_value, HWIO_##_reg##_ADDR(_dev->base)) |
| 38 | #define REG_WRITEI(_dev, _reg, _index, _value) writel(_value, HWIO_##_reg##_ADDR(_dev->base, _index)) |
| 39 | |
| 40 | #define REG_BMSK(_reg, _field) HWIO_##_reg##_##_field##_BMSK |
| 41 | #define REG_SHFT(_reg, _field) HWIO_##_reg##_##_field##_SHFT |
| 42 | |
| 43 | /* Macros to simplify wrapper reg field read */ |
| 44 | #define REG_READ_FIELD(_dev, _reg, _field) ((REG_READ(_dev,_reg) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field)) |
| 45 | #define REG_READ_FIELDI(_dev, _reg, _index, _field) ((REG_READI(_dev,_reg, _index) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field)) |
| 46 | |
| 47 | /* Macros to simplify wrapper reg field write: implementes read/modify/write */ |
| 48 | #define REG_WRITE_FIELD(_dev, _reg, _field, _value) REG_WRITE(_dev, _reg, ((REG_READ(_dev, _reg) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field)))) |
| 49 | #define REG_WRITE_FIELDI(_dev, _reg, _index, _field, _value) REG_WRITEI(_dev, _reg, _index, ((REG_READI(_dev, _reg, _index) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field)))) |
| 50 | |
| 51 | |
| 52 | /* The following defines are auto generated. */ |
| 53 | |
| 54 | /** |
| 55 | @brief Auto-generated HWIO interface include file. |
| 56 | |
| 57 | This file contains HWIO register definitions for the following modules: |
| 58 | USB30_QSCRATCH |
| 59 | */ |
| 60 | /*---------------------------------------------------------------------------- |
| 61 | * MODULE: USB30_QSCRATCH |
| 62 | *--------------------------------------------------------------------------*/ |
| 63 | |
| 64 | #define USB30_QSCRATCH_REG_BASE (USB30_WRAPPER_BASE + 0x000f8800) |
| 65 | |
| 66 | #define HWIO_IPCAT_REG_ADDR(x) ((x) + 0x00000000) |
| 67 | #define HWIO_IPCAT_REG_RMSK 0xffffffff |
| 68 | #define HWIO_IPCAT_REG_POR 0x10010001 |
| 69 | #define HWIO_IPCAT_REG_IN(x) \ |
| 70 | in_dword_masked(HWIO_IPCAT_REG_ADDR(x), HWIO_IPCAT_REG_RMSK) |
| 71 | #define HWIO_IPCAT_REG_INM(x, m) \ |
| 72 | in_dword_masked(HWIO_IPCAT_REG_ADDR(x), m) |
| 73 | #define HWIO_IPCAT_REG_IPCAT_BMSK 0xffffffff |
| 74 | #define HWIO_IPCAT_REG_IPCAT_SHFT 0x0 |
| 75 | |
| 76 | #define HWIO_CTRL_REG_ADDR(x) ((x) + 0x00000004) |
| 77 | #define HWIO_CTRL_REG_RMSK 0x33ff |
| 78 | #define HWIO_CTRL_REG_POR 0x00000190 |
| 79 | #define HWIO_CTRL_REG_IN(x) \ |
| 80 | in_dword_masked(HWIO_CTRL_REG_ADDR(x), HWIO_CTRL_REG_RMSK) |
| 81 | #define HWIO_CTRL_REG_INM(x, m) \ |
| 82 | in_dword_masked(HWIO_CTRL_REG_ADDR(x), m) |
| 83 | #define HWIO_CTRL_REG_OUT(x, v) \ |
| 84 | out_dword(HWIO_CTRL_REG_ADDR(x),v) |
| 85 | #define HWIO_CTRL_REG_OUTM(x,m,v) \ |
| 86 | out_dword_masked_ns(HWIO_CTRL_REG_ADDR(x),m,v,HWIO_CTRL_REG_IN(x)) |
| 87 | #define HWIO_CTRL_REG_HSIC_PLL_CTRL_SUSPEND_BMSK 0x2000 |
| 88 | #define HWIO_CTRL_REG_HSIC_PLL_CTRL_SUSPEND_SHFT 0xd |
| 89 | #define HWIO_CTRL_REG_HSIC_PLL_CTRL_SLEEP_BMSK 0x1000 |
| 90 | #define HWIO_CTRL_REG_HSIC_PLL_CTRL_SLEEP_SHFT 0xc |
| 91 | #define HWIO_CTRL_REG_BC_XCVR_SELECT_BMSK 0x300 |
| 92 | #define HWIO_CTRL_REG_BC_XCVR_SELECT_SHFT 0x8 |
| 93 | #define HWIO_CTRL_REG_BC_TERM_SELECT_BMSK 0x80 |
| 94 | #define HWIO_CTRL_REG_BC_TERM_SELECT_SHFT 0x7 |
| 95 | #define HWIO_CTRL_REG_BC_TX_VALID_BMSK 0x40 |
| 96 | #define HWIO_CTRL_REG_BC_TX_VALID_SHFT 0x6 |
| 97 | #define HWIO_CTRL_REG_BC_OPMODE_BMSK 0x30 |
| 98 | #define HWIO_CTRL_REG_BC_OPMODE_SHFT 0x4 |
| 99 | #define HWIO_CTRL_REG_BC_DMPULLDOWN_BMSK 0x8 |
| 100 | #define HWIO_CTRL_REG_BC_DMPULLDOWN_SHFT 0x3 |
| 101 | #define HWIO_CTRL_REG_BC_DPPULLDOWN_BMSK 0x4 |
| 102 | #define HWIO_CTRL_REG_BC_DPPULLDOWN_SHFT 0x2 |
| 103 | #define HWIO_CTRL_REG_BC_IDPULLUP_BMSK 0x2 |
| 104 | #define HWIO_CTRL_REG_BC_IDPULLUP_SHFT 0x1 |
| 105 | #define HWIO_CTRL_REG_BC_SEL_BMSK 0x1 |
| 106 | #define HWIO_CTRL_REG_BC_SEL_SHFT 0x0 |
| 107 | |
| 108 | #define HWIO_GENERAL_CFG_ADDR(x) ((x) + 0x00000008) |
| 109 | #define HWIO_GENERAL_CFG_RMSK 0x6 |
| 110 | #define HWIO_GENERAL_CFG_POR 0x00000000 |
| 111 | #define HWIO_GENERAL_CFG_IN(x) \ |
| 112 | in_dword_masked(HWIO_GENERAL_CFG_ADDR(x), HWIO_GENERAL_CFG_RMSK) |
| 113 | #define HWIO_GENERAL_CFG_INM(x, m) \ |
| 114 | in_dword_masked(HWIO_GENERAL_CFG_ADDR(x), m) |
| 115 | #define HWIO_GENERAL_CFG_OUT(x, v) \ |
| 116 | out_dword(HWIO_GENERAL_CFG_ADDR(x),v) |
| 117 | #define HWIO_GENERAL_CFG_OUTM(x,m,v) \ |
| 118 | out_dword_masked_ns(HWIO_GENERAL_CFG_ADDR(x),m,v,HWIO_GENERAL_CFG_IN(x)) |
| 119 | #define HWIO_GENERAL_CFG_XHCI_REV_BMSK 0x4 |
| 120 | #define HWIO_GENERAL_CFG_XHCI_REV_SHFT 0x2 |
| 121 | #define HWIO_GENERAL_CFG_DBM_EN_BMSK 0x2 |
| 122 | #define HWIO_GENERAL_CFG_DBM_EN_SHFT 0x1 |
| Channagoud Kadabi | c14b2a5 | 2015-01-06 15:05:12 -0800 | [diff] [blame] | 123 | #define HWIO_GENERAL_CFG_PIPE_UTMI_CLK_DIS_BMSK 0x100 |
| 124 | #define HWIO_GENERAL_CFG_PIPE_UTMI_CLK_DIS_SHFT 0x8 |
| 125 | #define HWIO_GENERAL_CFG_PIPE_UTMI_CLK_SEL_BMSK 0x1 |
| 126 | #define HWIO_GENERAL_CFG_PIPE_UTMI_CLK_SEL_SHFT 0x0 |
| 127 | #define HWIO_GENERAL_CFG_PIPE3_PHYSTATUS_SW_BMSK 0x8 |
| 128 | #define HWIO_GENERAL_CFG_PIPE3_PHYSTATUS_SW_SHFT 0x3 |
| Amol Jadi | f3d5a89 | 2013-07-23 16:09:44 -0700 | [diff] [blame] | 129 | |
| 130 | #define HWIO_RAM1_REG_ADDR(x) ((x) + 0x0000000c) |
| 131 | #define HWIO_RAM1_REG_RMSK 0x7 |
| 132 | #define HWIO_RAM1_REG_POR 0x00000000 |
| 133 | #define HWIO_RAM1_REG_IN(x) \ |
| 134 | in_dword_masked(HWIO_RAM1_REG_ADDR(x), HWIO_RAM1_REG_RMSK) |
| 135 | #define HWIO_RAM1_REG_INM(x, m) \ |
| 136 | in_dword_masked(HWIO_RAM1_REG_ADDR(x), m) |
| 137 | #define HWIO_RAM1_REG_OUT(x, v) \ |
| 138 | out_dword(HWIO_RAM1_REG_ADDR(x),v) |
| 139 | #define HWIO_RAM1_REG_OUTM(x,m,v) \ |
| 140 | out_dword_masked_ns(HWIO_RAM1_REG_ADDR(x),m,v,HWIO_RAM1_REG_IN(x)) |
| 141 | #define HWIO_RAM1_REG_RAM13_EN_BMSK 0x4 |
| 142 | #define HWIO_RAM1_REG_RAM13_EN_SHFT 0x2 |
| 143 | #define HWIO_RAM1_REG_RAM12_EN_BMSK 0x2 |
| 144 | #define HWIO_RAM1_REG_RAM12_EN_SHFT 0x1 |
| 145 | #define HWIO_RAM1_REG_RAM11_EN_BMSK 0x1 |
| 146 | #define HWIO_RAM1_REG_RAM11_EN_SHFT 0x0 |
| 147 | |
| Amol Jadi | 5418da3 | 2013-10-11 14:14:47 -0700 | [diff] [blame] | 148 | /* Note: HS_PHYCTRL_COMMON register is added only from 8084 and onwards. */ |
| 149 | #define HWIO_HS_PHY_CTRL_COMMON_ADDR(x) ((x) + 0x000000ec) |
| 150 | #define HWIO_HS_PHY_CTRL_COMMON_RMSK 0x7fff |
| 151 | #define HWIO_HS_PHY_CTRL_COMMON_IN(x) \ |
| 152 | in_dword_masked(HWIO_HS_PHY_CTRL_COMMON_ADDR(x), HWIO_HS_PHY_CTRL_COMMON_RMSK) |
| 153 | #define HWIO_HS_PHY_CTRL_COMMON_INM(x, m) \ |
| 154 | in_dword_masked(HWIO_HS_PHY_CTRL_COMMON_ADDR(x), m) |
| 155 | #define HWIO_HS_PHY_CTRL_COMMON_OUT(x, v) \ |
| 156 | out_dword(HWIO_HS_PHY_CTRL_COMMON_ADDR(x),v) |
| 157 | #define HWIO_HS_PHY_CTRL_COMMON_OUTM(x,m,v) \ |
| 158 | out_dword_masked_ns(HWIO_HS_PHY_CTRL_COMMON_ADDR(x),m,v,HWIO_HS_PHY_CTRL_COMMON_IN(x)) |
| 159 | #define HWIO_HS_PHY_CTRL_COMMON_USE_CLKCORE_BMSK 0x4000 |
| 160 | #define HWIO_HS_PHY_CTRL_COMMON_USE_CLKCORE_SHFT 0xe |
| 161 | #define HWIO_HS_PHY_CTRL_COMMON_ACAENB0_BMSK 0x2000 |
| 162 | #define HWIO_HS_PHY_CTRL_COMMON_ACAENB0_SHFT 0xd |
| 163 | #define HWIO_HS_PHY_CTRL_COMMON_VBUSVLDEXTSEL0_BMSK 0x1000 |
| 164 | #define HWIO_HS_PHY_CTRL_COMMON_VBUSVLDEXTSEL0_SHFT 0xc |
| 165 | #define HWIO_HS_PHY_CTRL_COMMON_OTGDISABLE0_BMSK 0x800 |
| 166 | #define HWIO_HS_PHY_CTRL_COMMON_OTGDISABLE0_SHFT 0xb |
| 167 | #define HWIO_HS_PHY_CTRL_COMMON_OTGTUNE0_BMSK 0x700 |
| 168 | #define HWIO_HS_PHY_CTRL_COMMON_OTGTUNE0_SHFT 0x8 |
| 169 | #define HWIO_HS_PHY_CTRL_COMMON_COMMONONN_BMSK 0x80 |
| 170 | #define HWIO_HS_PHY_CTRL_COMMON_COMMONONN_SHFT 0x7 |
| 171 | #define HWIO_HS_PHY_CTRL_COMMON_FSEL_BMSK 0x70 |
| 172 | #define HWIO_HS_PHY_CTRL_COMMON_FSEL_SHFT 0x4 |
| 173 | #define HWIO_HS_PHY_CTRL_COMMON_RETENABLEN_BMSK 0x8 |
| 174 | #define HWIO_HS_PHY_CTRL_COMMON_RETENABLEN_SHFT 0x3 |
| 175 | #define HWIO_HS_PHY_CTRL_COMMON_SIDDQ_BMSK 0x4 |
| 176 | #define HWIO_HS_PHY_CTRL_COMMON_SIDDQ_SHFT 0x2 |
| 177 | #define HWIO_HS_PHY_CTRL_COMMON_VATESTENB_BMSK 0x3 |
| 178 | #define HWIO_HS_PHY_CTRL_COMMON_VATESTENB_SHFT 0x0 |
| 179 | |
| 180 | |
| Amol Jadi | f3d5a89 | 2013-07-23 16:09:44 -0700 | [diff] [blame] | 181 | #define HWIO_HS_PHY_CTRL_ADDR(x) ((x) + 0x00000010) |
| 182 | #define HWIO_HS_PHY_CTRL_RMSK 0x7ffffff |
| 183 | #define HWIO_HS_PHY_CTRL_POR 0x072203b2 |
| 184 | #define HWIO_HS_PHY_CTRL_IN(x) \ |
| 185 | in_dword_masked(HWIO_HS_PHY_CTRL_ADDR(x), HWIO_HS_PHY_CTRL_RMSK) |
| 186 | #define HWIO_HS_PHY_CTRL_INM(x, m) \ |
| 187 | in_dword_masked(HWIO_HS_PHY_CTRL_ADDR(x), m) |
| 188 | #define HWIO_HS_PHY_CTRL_OUT(x, v) \ |
| 189 | out_dword(HWIO_HS_PHY_CTRL_ADDR(x),v) |
| 190 | #define HWIO_HS_PHY_CTRL_OUTM(x,m,v) \ |
| 191 | out_dword_masked_ns(HWIO_HS_PHY_CTRL_ADDR(x),m,v,HWIO_HS_PHY_CTRL_IN(x)) |
| Amol Jadi | 5418da3 | 2013-10-11 14:14:47 -0700 | [diff] [blame] | 192 | |
| 193 | /* Note: This field is introduced only in 8084 and onwards. */ |
| 194 | #define HWIO_HS_PHY_CTRL_SW_SESSVLD_SEL_BMSK 0x10000000 |
| 195 | #define HWIO_HS_PHY_CTRL_SW_SESSVLD_SEL_SHFT 0x1c |
| 196 | |
| Amol Jadi | f3d5a89 | 2013-07-23 16:09:44 -0700 | [diff] [blame] | 197 | #define HWIO_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_BMSK 0x4000000 |
| 198 | #define HWIO_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_SHFT 0x1a |
| 199 | #define HWIO_HS_PHY_CTRL_FREECLK_SEL_BMSK 0x2000000 |
| 200 | #define HWIO_HS_PHY_CTRL_FREECLK_SEL_SHFT 0x19 |
| 201 | #define HWIO_HS_PHY_CTRL_DMSEHV_CLAMP_EN_N_BMSK 0x1000000 |
| 202 | #define HWIO_HS_PHY_CTRL_DMSEHV_CLAMP_EN_N_SHFT 0x18 |
| 203 | #define HWIO_HS_PHY_CTRL_USB2_SUSPEND_N_SEL_BMSK 0x800000 |
| 204 | #define HWIO_HS_PHY_CTRL_USB2_SUSPEND_N_SEL_SHFT 0x17 |
| 205 | #define HWIO_HS_PHY_CTRL_USB2_SUSPEND_N_BMSK 0x400000 |
| 206 | #define HWIO_HS_PHY_CTRL_USB2_SUSPEND_N_SHFT 0x16 |
| 207 | #define HWIO_HS_PHY_CTRL_USB2_UTMI_CLK_EN_BMSK 0x200000 |
| 208 | #define HWIO_HS_PHY_CTRL_USB2_UTMI_CLK_EN_SHFT 0x15 |
| 209 | #define HWIO_HS_PHY_CTRL_UTMI_OTG_VBUS_VALID_BMSK 0x100000 |
| 210 | #define HWIO_HS_PHY_CTRL_UTMI_OTG_VBUS_VALID_SHFT 0x14 |
| 211 | #define HWIO_HS_PHY_CTRL_AUTORESUME_BMSK 0x80000 |
| 212 | #define HWIO_HS_PHY_CTRL_AUTORESUME_SHFT 0x13 |
| 213 | #define HWIO_HS_PHY_CTRL_USE_CLKCORE_BMSK 0x40000 |
| 214 | #define HWIO_HS_PHY_CTRL_USE_CLKCORE_SHFT 0x12 |
| 215 | #define HWIO_HS_PHY_CTRL_DPSEHV_CLAMP_EN_N_BMSK 0x20000 |
| 216 | #define HWIO_HS_PHY_CTRL_DPSEHV_CLAMP_EN_N_SHFT 0x11 |
| 217 | #define HWIO_HS_PHY_CTRL_IDHV_INTEN_BMSK 0x10000 |
| 218 | #define HWIO_HS_PHY_CTRL_IDHV_INTEN_SHFT 0x10 |
| 219 | #define HWIO_HS_PHY_CTRL_OTGSESSVLDHV_INTEN_BMSK 0x8000 |
| 220 | #define HWIO_HS_PHY_CTRL_OTGSESSVLDHV_INTEN_SHFT 0xf |
| 221 | #define HWIO_HS_PHY_CTRL_VBUSVLDEXTSEL0_BMSK 0x4000 |
| 222 | #define HWIO_HS_PHY_CTRL_VBUSVLDEXTSEL0_SHFT 0xe |
| 223 | #define HWIO_HS_PHY_CTRL_VBUSVLDEXT0_BMSK 0x2000 |
| 224 | #define HWIO_HS_PHY_CTRL_VBUSVLDEXT0_SHFT 0xd |
| 225 | #define HWIO_HS_PHY_CTRL_OTGDISABLE0_BMSK 0x1000 |
| 226 | #define HWIO_HS_PHY_CTRL_OTGDISABLE0_SHFT 0xc |
| 227 | #define HWIO_HS_PHY_CTRL_COMMONONN_BMSK 0x800 |
| 228 | #define HWIO_HS_PHY_CTRL_COMMONONN_SHFT 0xb |
| 229 | #define HWIO_HS_PHY_CTRL_ULPIPOR_BMSK 0x400 |
| 230 | #define HWIO_HS_PHY_CTRL_ULPIPOR_SHFT 0xa |
| 231 | #define HWIO_HS_PHY_CTRL_ID_HV_CLAMP_EN_N_BMSK 0x200 |
| 232 | #define HWIO_HS_PHY_CTRL_ID_HV_CLAMP_EN_N_SHFT 0x9 |
| 233 | #define HWIO_HS_PHY_CTRL_OTGSESSVLD_HV_CLAMP_EN_N_BMSK 0x100 |
| 234 | #define HWIO_HS_PHY_CTRL_OTGSESSVLD_HV_CLAMP_EN_N_SHFT 0x8 |
| 235 | #define HWIO_HS_PHY_CTRL_CLAMP_EN_N_BMSK 0x80 |
| 236 | #define HWIO_HS_PHY_CTRL_CLAMP_EN_N_SHFT 0x7 |
| 237 | #define HWIO_HS_PHY_CTRL_FSEL_BMSK 0x70 |
| 238 | #define HWIO_HS_PHY_CTRL_FSEL_SHFT 0x4 |
| 239 | #define HWIO_HS_PHY_CTRL_REFCLKOUT_EN_BMSK 0x8 |
| 240 | #define HWIO_HS_PHY_CTRL_REFCLKOUT_EN_SHFT 0x3 |
| 241 | #define HWIO_HS_PHY_CTRL_SIDDQ_BMSK 0x4 |
| 242 | #define HWIO_HS_PHY_CTRL_SIDDQ_SHFT 0x2 |
| 243 | #define HWIO_HS_PHY_CTRL_RETENABLEN_BMSK 0x2 |
| 244 | #define HWIO_HS_PHY_CTRL_RETENABLEN_SHFT 0x1 |
| 245 | #define HWIO_HS_PHY_CTRL_POR_BMSK 0x1 |
| 246 | #define HWIO_HS_PHY_CTRL_POR_SHFT 0x0 |
| 247 | |
| 248 | #define HWIO_PARAMETER_OVERRIDE_X_ADDR(x) ((x) + 0x00000014) |
| 249 | #define HWIO_PARAMETER_OVERRIDE_X_RMSK 0x3ffffff |
| 250 | #define HWIO_PARAMETER_OVERRIDE_X_POR 0x00de06e4 |
| 251 | #define HWIO_PARAMETER_OVERRIDE_X_IN(x) \ |
| 252 | in_dword_masked(HWIO_PARAMETER_OVERRIDE_X_ADDR(x), HWIO_PARAMETER_OVERRIDE_X_RMSK) |
| 253 | #define HWIO_PARAMETER_OVERRIDE_X_INM(x, m) \ |
| 254 | in_dword_masked(HWIO_PARAMETER_OVERRIDE_X_ADDR(x), m) |
| 255 | #define HWIO_PARAMETER_OVERRIDE_X_OUT(x, v) \ |
| 256 | out_dword(HWIO_PARAMETER_OVERRIDE_X_ADDR(x),v) |
| 257 | #define HWIO_PARAMETER_OVERRIDE_X_OUTM(x,m,v) \ |
| 258 | out_dword_masked_ns(HWIO_PARAMETER_OVERRIDE_X_ADDR(x),m,v,HWIO_PARAMETER_OVERRIDE_X_IN(x)) |
| 259 | #define HWIO_PARAMETER_OVERRIDE_X_TXFSLSTUNE0_BMSK 0x3c00000 |
| 260 | #define HWIO_PARAMETER_OVERRIDE_X_TXFSLSTUNE0_SHFT 0x16 |
| 261 | #define HWIO_PARAMETER_OVERRIDE_X_TXRESTUNE0_BMSK 0x300000 |
| 262 | #define HWIO_PARAMETER_OVERRIDE_X_TXRESTUNE0_SHFT 0x14 |
| 263 | #define HWIO_PARAMETER_OVERRIDE_X_TXHSXVTUNE0_BMSK 0xc0000 |
| 264 | #define HWIO_PARAMETER_OVERRIDE_X_TXHSXVTUNE0_SHFT 0x12 |
| 265 | #define HWIO_PARAMETER_OVERRIDE_X_TXRISETUNE0_BMSK 0x30000 |
| 266 | #define HWIO_PARAMETER_OVERRIDE_X_TXRISETUNE0_SHFT 0x10 |
| 267 | #define HWIO_PARAMETER_OVERRIDE_X_TXPREEMPAMPTUNE0_BMSK 0xc000 |
| 268 | #define HWIO_PARAMETER_OVERRIDE_X_TXPREEMPAMPTUNE0_SHFT 0xe |
| 269 | #define HWIO_PARAMETER_OVERRIDE_X_TXPREEMPPULSETUNE0_BMSK 0x2000 |
| 270 | #define HWIO_PARAMETER_OVERRIDE_X_TXPREEMPPULSETUNE0_SHFT 0xd |
| 271 | #define HWIO_PARAMETER_OVERRIDE_X_TXVREFTUNE0_BMSK 0x1e00 |
| 272 | #define HWIO_PARAMETER_OVERRIDE_X_TXVREFTUNE0_SHFT 0x9 |
| 273 | #define HWIO_PARAMETER_OVERRIDE_X_SQRXTUNE0_BMSK 0x1c0 |
| 274 | #define HWIO_PARAMETER_OVERRIDE_X_SQRXTUNE0_SHFT 0x6 |
| 275 | #define HWIO_PARAMETER_OVERRIDE_X_OTGTUNE0_BMSK 0x38 |
| 276 | #define HWIO_PARAMETER_OVERRIDE_X_OTGTUNE0_SHFT 0x3 |
| 277 | #define HWIO_PARAMETER_OVERRIDE_X_COMPDISTUNE0_BMSK 0x7 |
| 278 | #define HWIO_PARAMETER_OVERRIDE_X_COMPDISTUNE0_SHFT 0x0 |
| 279 | |
| 280 | #define HWIO_CHARGING_DET_CTRL_ADDR(x) ((x) + 0x00000018) |
| 281 | #define HWIO_CHARGING_DET_CTRL_RMSK 0x3f |
| 282 | #define HWIO_CHARGING_DET_CTRL_POR 0x00000000 |
| 283 | #define HWIO_CHARGING_DET_CTRL_IN(x) \ |
| 284 | in_dword_masked(HWIO_CHARGING_DET_CTRL_ADDR(x), HWIO_CHARGING_DET_CTRL_RMSK) |
| 285 | #define HWIO_CHARGING_DET_CTRL_INM(x, m) \ |
| 286 | in_dword_masked(HWIO_CHARGING_DET_CTRL_ADDR(x), m) |
| 287 | #define HWIO_CHARGING_DET_CTRL_OUT(x, v) \ |
| 288 | out_dword(HWIO_CHARGING_DET_CTRL_ADDR(x),v) |
| 289 | #define HWIO_CHARGING_DET_CTRL_OUTM(x,m,v) \ |
| 290 | out_dword_masked_ns(HWIO_CHARGING_DET_CTRL_ADDR(x),m,v,HWIO_CHARGING_DET_CTRL_IN(x)) |
| 291 | #define HWIO_CHARGING_DET_CTRL_VDATDETENB0_BMSK 0x20 |
| 292 | #define HWIO_CHARGING_DET_CTRL_VDATDETENB0_SHFT 0x5 |
| 293 | #define HWIO_CHARGING_DET_CTRL_VDATSRCENB0_BMSK 0x10 |
| 294 | #define HWIO_CHARGING_DET_CTRL_VDATSRCENB0_SHFT 0x4 |
| 295 | #define HWIO_CHARGING_DET_CTRL_VDMSRCAUTO_BMSK 0x8 |
| 296 | #define HWIO_CHARGING_DET_CTRL_VDMSRCAUTO_SHFT 0x3 |
| 297 | #define HWIO_CHARGING_DET_CTRL_CHRGSEL0_BMSK 0x4 |
| 298 | #define HWIO_CHARGING_DET_CTRL_CHRGSEL0_SHFT 0x2 |
| 299 | #define HWIO_CHARGING_DET_CTRL_DCDENB0_BMSK 0x2 |
| 300 | #define HWIO_CHARGING_DET_CTRL_DCDENB0_SHFT 0x1 |
| 301 | #define HWIO_CHARGING_DET_CTRL_ACAENB0_BMSK 0x1 |
| 302 | #define HWIO_CHARGING_DET_CTRL_ACAENB0_SHFT 0x0 |
| 303 | |
| 304 | #define HWIO_CHARGING_DET_OUTPUT_ADDR(x) ((x) + 0x0000001c) |
| 305 | #define HWIO_CHARGING_DET_OUTPUT_RMSK 0xfff |
| 306 | #define HWIO_CHARGING_DET_OUTPUT_POR 0x00000000 |
| 307 | #define HWIO_CHARGING_DET_OUTPUT_IN(x) \ |
| 308 | in_dword_masked(HWIO_CHARGING_DET_OUTPUT_ADDR(x), HWIO_CHARGING_DET_OUTPUT_RMSK) |
| 309 | #define HWIO_CHARGING_DET_OUTPUT_INM(x, m) \ |
| 310 | in_dword_masked(HWIO_CHARGING_DET_OUTPUT_ADDR(x), m) |
| 311 | #define HWIO_CHARGING_DET_OUTPUT_DMSEHV_BMSK 0x800 |
| 312 | #define HWIO_CHARGING_DET_OUTPUT_DMSEHV_SHFT 0xb |
| 313 | #define HWIO_CHARGING_DET_OUTPUT_DPSEHV_BMSK 0x400 |
| 314 | #define HWIO_CHARGING_DET_OUTPUT_DPSEHV_SHFT 0xa |
| 315 | #define HWIO_CHARGING_DET_OUTPUT_LINESTATE_BMSK 0x300 |
| 316 | #define HWIO_CHARGING_DET_OUTPUT_LINESTATE_SHFT 0x8 |
| 317 | #define HWIO_CHARGING_DET_OUTPUT_RIDFLOAT_N_BMSK 0x80 |
| 318 | #define HWIO_CHARGING_DET_OUTPUT_RIDFLOAT_N_SHFT 0x7 |
| 319 | #define HWIO_CHARGING_DET_OUTPUT_RIDFLOAT_BMSK 0x40 |
| 320 | #define HWIO_CHARGING_DET_OUTPUT_RIDFLOAT_SHFT 0x6 |
| 321 | #define HWIO_CHARGING_DET_OUTPUT_RIDGND_BMSK 0x20 |
| 322 | #define HWIO_CHARGING_DET_OUTPUT_RIDGND_SHFT 0x5 |
| 323 | #define HWIO_CHARGING_DET_OUTPUT_RIDC_BMSK 0x10 |
| 324 | #define HWIO_CHARGING_DET_OUTPUT_RIDC_SHFT 0x4 |
| 325 | #define HWIO_CHARGING_DET_OUTPUT_RIDB_BMSK 0x8 |
| 326 | #define HWIO_CHARGING_DET_OUTPUT_RIDB_SHFT 0x3 |
| 327 | #define HWIO_CHARGING_DET_OUTPUT_RIDA_BMSK 0x4 |
| 328 | #define HWIO_CHARGING_DET_OUTPUT_RIDA_SHFT 0x2 |
| 329 | #define HWIO_CHARGING_DET_OUTPUT_DCDOUT_BMSK 0x2 |
| 330 | #define HWIO_CHARGING_DET_OUTPUT_DCDOUT_SHFT 0x1 |
| 331 | #define HWIO_CHARGING_DET_OUTPUT_CHGDET_BMSK 0x1 |
| 332 | #define HWIO_CHARGING_DET_OUTPUT_CHGDET_SHFT 0x0 |
| 333 | |
| 334 | #define HWIO_ALT_INTERRUPT_EN_ADDR(x) ((x) + 0x00000020) |
| 335 | #define HWIO_ALT_INTERRUPT_EN_RMSK 0xfff |
| 336 | #define HWIO_ALT_INTERRUPT_EN_POR 0x00000000 |
| 337 | #define HWIO_ALT_INTERRUPT_EN_IN(x) \ |
| 338 | in_dword_masked(HWIO_ALT_INTERRUPT_EN_ADDR(x), HWIO_ALT_INTERRUPT_EN_RMSK) |
| 339 | #define HWIO_ALT_INTERRUPT_EN_INM(x, m) \ |
| 340 | in_dword_masked(HWIO_ALT_INTERRUPT_EN_ADDR(x), m) |
| 341 | #define HWIO_ALT_INTERRUPT_EN_OUT(x, v) \ |
| 342 | out_dword(HWIO_ALT_INTERRUPT_EN_ADDR(x),v) |
| 343 | #define HWIO_ALT_INTERRUPT_EN_OUTM(x,m,v) \ |
| 344 | out_dword_masked_ns(HWIO_ALT_INTERRUPT_EN_ADDR(x),m,v,HWIO_ALT_INTERRUPT_EN_IN(x)) |
| 345 | #define HWIO_ALT_INTERRUPT_EN_DMSEHV_LO_INTEN_BMSK 0x800 |
| 346 | #define HWIO_ALT_INTERRUPT_EN_DMSEHV_LO_INTEN_SHFT 0xb |
| 347 | #define HWIO_ALT_INTERRUPT_EN_DMSEHV_HI_INTEN_BMSK 0x400 |
| 348 | #define HWIO_ALT_INTERRUPT_EN_DMSEHV_HI_INTEN_SHFT 0xa |
| 349 | #define HWIO_ALT_INTERRUPT_EN_DPSEHV_LO_INTEN_BMSK 0x200 |
| 350 | #define HWIO_ALT_INTERRUPT_EN_DPSEHV_LO_INTEN_SHFT 0x9 |
| 351 | #define HWIO_ALT_INTERRUPT_EN_DPSEHV_HI_INTEN_BMSK 0x100 |
| 352 | #define HWIO_ALT_INTERRUPT_EN_DPSEHV_HI_INTEN_SHFT 0x8 |
| 353 | #define HWIO_ALT_INTERRUPT_EN_DMSEHV_INTEN_BMSK 0x80 |
| 354 | #define HWIO_ALT_INTERRUPT_EN_DMSEHV_INTEN_SHFT 0x7 |
| 355 | #define HWIO_ALT_INTERRUPT_EN_DPSEHV_INTEN_BMSK 0x40 |
| 356 | #define HWIO_ALT_INTERRUPT_EN_DPSEHV_INTEN_SHFT 0x6 |
| 357 | #define HWIO_ALT_INTERRUPT_EN_RIDFLOATNINTEN_BMSK 0x20 |
| 358 | #define HWIO_ALT_INTERRUPT_EN_RIDFLOATNINTEN_SHFT 0x5 |
| 359 | #define HWIO_ALT_INTERRUPT_EN_CHGDETINTEN_BMSK 0x10 |
| 360 | #define HWIO_ALT_INTERRUPT_EN_CHGDETINTEN_SHFT 0x4 |
| 361 | #define HWIO_ALT_INTERRUPT_EN_DPINTEN_BMSK 0x8 |
| 362 | #define HWIO_ALT_INTERRUPT_EN_DPINTEN_SHFT 0x3 |
| 363 | #define HWIO_ALT_INTERRUPT_EN_DCDINTEN_BMSK 0x4 |
| 364 | #define HWIO_ALT_INTERRUPT_EN_DCDINTEN_SHFT 0x2 |
| 365 | #define HWIO_ALT_INTERRUPT_EN_DMINTEN_BMSK 0x2 |
| 366 | #define HWIO_ALT_INTERRUPT_EN_DMINTEN_SHFT 0x1 |
| 367 | #define HWIO_ALT_INTERRUPT_EN_ACAINTEN_BMSK 0x1 |
| 368 | #define HWIO_ALT_INTERRUPT_EN_ACAINTEN_SHFT 0x0 |
| 369 | |
| 370 | #define HWIO_HS_PHY_IRQ_STAT_ADDR(x) ((x) + 0x00000024) |
| 371 | #define HWIO_HS_PHY_IRQ_STAT_RMSK 0xfff |
| 372 | #define HWIO_HS_PHY_IRQ_STAT_POR 0x00000000 |
| 373 | #define HWIO_HS_PHY_IRQ_STAT_IN(x) \ |
| 374 | in_dword_masked(HWIO_HS_PHY_IRQ_STAT_ADDR(x), HWIO_HS_PHY_IRQ_STAT_RMSK) |
| 375 | #define HWIO_HS_PHY_IRQ_STAT_INM(x, m) \ |
| 376 | in_dword_masked(HWIO_HS_PHY_IRQ_STAT_ADDR(x), m) |
| 377 | #define HWIO_HS_PHY_IRQ_STAT_OUT(x, v) \ |
| 378 | out_dword(HWIO_HS_PHY_IRQ_STAT_ADDR(x),v) |
| 379 | #define HWIO_HS_PHY_IRQ_STAT_OUTM(x,m,v) \ |
| 380 | out_dword_masked_ns(HWIO_HS_PHY_IRQ_STAT_ADDR(x),m,v,HWIO_HS_PHY_IRQ_STAT_IN(x)) |
| 381 | #define HWIO_HS_PHY_IRQ_STAT_DMSEHV_LO_INTLCH_BMSK 0x800 |
| 382 | #define HWIO_HS_PHY_IRQ_STAT_DMSEHV_LO_INTLCH_SHFT 0xb |
| 383 | #define HWIO_HS_PHY_IRQ_STAT_DMSEHV_HI_INTLCH_BMSK 0x400 |
| 384 | #define HWIO_HS_PHY_IRQ_STAT_DMSEHV_HI_INTLCH_SHFT 0xa |
| 385 | #define HWIO_HS_PHY_IRQ_STAT_DPSEHV_LO_INTLCH_BMSK 0x200 |
| 386 | #define HWIO_HS_PHY_IRQ_STAT_DPSEHV_LO_INTLCH_SHFT 0x9 |
| 387 | #define HWIO_HS_PHY_IRQ_STAT_DPSEHV_HI_INTLCH_BMSK 0x100 |
| 388 | #define HWIO_HS_PHY_IRQ_STAT_DPSEHV_HI_INTLCH_SHFT 0x8 |
| 389 | #define HWIO_HS_PHY_IRQ_STAT_DMSEHV_INTLCH_BMSK 0x80 |
| 390 | #define HWIO_HS_PHY_IRQ_STAT_DMSEHV_INTLCH_SHFT 0x7 |
| 391 | #define HWIO_HS_PHY_IRQ_STAT_DPSEHV_INTLCH_BMSK 0x40 |
| 392 | #define HWIO_HS_PHY_IRQ_STAT_DPSEHV_INTLCH_SHFT 0x6 |
| 393 | #define HWIO_HS_PHY_IRQ_STAT_RIDFLOATNINTLCH_BMSK 0x20 |
| 394 | #define HWIO_HS_PHY_IRQ_STAT_RIDFLOATNINTLCH_SHFT 0x5 |
| 395 | #define HWIO_HS_PHY_IRQ_STAT_CHGDETINTLCH_BMSK 0x10 |
| 396 | #define HWIO_HS_PHY_IRQ_STAT_CHGDETINTLCH_SHFT 0x4 |
| 397 | #define HWIO_HS_PHY_IRQ_STAT_DPINTLCH_BMSK 0x8 |
| 398 | #define HWIO_HS_PHY_IRQ_STAT_DPINTLCH_SHFT 0x3 |
| 399 | #define HWIO_HS_PHY_IRQ_STAT_DCDINTLCH_BMSK 0x4 |
| 400 | #define HWIO_HS_PHY_IRQ_STAT_DCDINTLCH_SHFT 0x2 |
| 401 | #define HWIO_HS_PHY_IRQ_STAT_DMINTLCH_BMSK 0x2 |
| 402 | #define HWIO_HS_PHY_IRQ_STAT_DMINTLCH_SHFT 0x1 |
| 403 | #define HWIO_HS_PHY_IRQ_STAT_ACAINTLCH_BMSK 0x1 |
| 404 | #define HWIO_HS_PHY_IRQ_STAT_ACAINTLCH_SHFT 0x0 |
| 405 | |
| 406 | #define HWIO_CGCTL_REG_ADDR(x) ((x) + 0x00000028) |
| 407 | #define HWIO_CGCTL_REG_RMSK 0x1f |
| 408 | #define HWIO_CGCTL_REG_POR 0x00000000 |
| 409 | #define HWIO_CGCTL_REG_IN(x) \ |
| 410 | in_dword_masked(HWIO_CGCTL_REG_ADDR(x), HWIO_CGCTL_REG_RMSK) |
| 411 | #define HWIO_CGCTL_REG_INM(x, m) \ |
| 412 | in_dword_masked(HWIO_CGCTL_REG_ADDR(x), m) |
| 413 | #define HWIO_CGCTL_REG_OUT(x, v) \ |
| 414 | out_dword(HWIO_CGCTL_REG_ADDR(x),v) |
| 415 | #define HWIO_CGCTL_REG_OUTM(x,m,v) \ |
| 416 | out_dword_masked_ns(HWIO_CGCTL_REG_ADDR(x),m,v,HWIO_CGCTL_REG_IN(x)) |
| 417 | #define HWIO_CGCTL_REG_RAM13_EN_BMSK 0x10 |
| 418 | #define HWIO_CGCTL_REG_RAM13_EN_SHFT 0x4 |
| 419 | #define HWIO_CGCTL_REG_RAM1112_EN_BMSK 0x8 |
| 420 | #define HWIO_CGCTL_REG_RAM1112_EN_SHFT 0x3 |
| 421 | #define HWIO_CGCTL_REG_BAM_NDP_EN_BMSK 0x4 |
| 422 | #define HWIO_CGCTL_REG_BAM_NDP_EN_SHFT 0x2 |
| 423 | #define HWIO_CGCTL_REG_DBM_FSM_EN_BMSK 0x2 |
| 424 | #define HWIO_CGCTL_REG_DBM_FSM_EN_SHFT 0x1 |
| 425 | #define HWIO_CGCTL_REG_DBM_REG_EN_BMSK 0x1 |
| 426 | #define HWIO_CGCTL_REG_DBM_REG_EN_SHFT 0x0 |
| 427 | |
| 428 | #define HWIO_DBG_BUS_REG_ADDR(x) ((x) + 0x0000002c) |
| 429 | #define HWIO_DBG_BUS_REG_RMSK 0xf1ff001 |
| 430 | #define HWIO_DBG_BUS_REG_POR 0x00000000 |
| 431 | #define HWIO_DBG_BUS_REG_IN(x) \ |
| 432 | in_dword_masked(HWIO_DBG_BUS_REG_ADDR(x), HWIO_DBG_BUS_REG_RMSK) |
| 433 | #define HWIO_DBG_BUS_REG_INM(x, m) \ |
| 434 | in_dword_masked(HWIO_DBG_BUS_REG_ADDR(x), m) |
| 435 | #define HWIO_DBG_BUS_REG_OUT(x, v) \ |
| 436 | out_dword(HWIO_DBG_BUS_REG_ADDR(x),v) |
| 437 | #define HWIO_DBG_BUS_REG_OUTM(x,m,v) \ |
| 438 | out_dword_masked_ns(HWIO_DBG_BUS_REG_ADDR(x),m,v,HWIO_DBG_BUS_REG_IN(x)) |
| 439 | #define HWIO_DBG_BUS_REG_GENERAL_DBG_SEL_BMSK 0xf000000 |
| 440 | #define HWIO_DBG_BUS_REG_GENERAL_DBG_SEL_SHFT 0x18 |
| 441 | #define HWIO_DBG_BUS_REG_DBM_DBG_EN_BMSK 0x100000 |
| 442 | #define HWIO_DBG_BUS_REG_DBM_DBG_EN_SHFT 0x14 |
| 443 | #define HWIO_DBG_BUS_REG_DBM_DBG_SEL_BMSK 0xff000 |
| 444 | #define HWIO_DBG_BUS_REG_DBM_DBG_SEL_SHFT 0xc |
| 445 | #define HWIO_DBG_BUS_REG_CTRL_DBG_SEL_BMSK 0x1 |
| 446 | #define HWIO_DBG_BUS_REG_CTRL_DBG_SEL_SHFT 0x0 |
| 447 | |
| 448 | #define HWIO_SS_PHY_CTRL_ADDR(x) ((x) + 0x00000030) |
| 449 | #define HWIO_SS_PHY_CTRL_RMSK 0x1fffffff |
| 450 | #define HWIO_SS_PHY_CTRL_POR 0x10210002 |
| 451 | #define HWIO_SS_PHY_CTRL_IN(x) \ |
| 452 | in_dword_masked(HWIO_SS_PHY_CTRL_ADDR(x), HWIO_SS_PHY_CTRL_RMSK) |
| 453 | #define HWIO_SS_PHY_CTRL_INM(x, m) \ |
| 454 | in_dword_masked(HWIO_SS_PHY_CTRL_ADDR(x), m) |
| 455 | #define HWIO_SS_PHY_CTRL_OUT(x, v) \ |
| 456 | out_dword(HWIO_SS_PHY_CTRL_ADDR(x),v) |
| 457 | #define HWIO_SS_PHY_CTRL_OUTM(x,m,v) \ |
| 458 | out_dword_masked_ns(HWIO_SS_PHY_CTRL_ADDR(x),m,v,HWIO_SS_PHY_CTRL_IN(x)) |
| 459 | #define HWIO_SS_PHY_CTRL_REF_USE_PAD_BMSK 0x10000000 |
| 460 | #define HWIO_SS_PHY_CTRL_REF_USE_PAD_SHFT 0x1c |
| 461 | #define HWIO_SS_PHY_CTRL_TEST_BURNIN_BMSK 0x8000000 |
| 462 | #define HWIO_SS_PHY_CTRL_TEST_BURNIN_SHFT 0x1b |
| 463 | #define HWIO_SS_PHY_CTRL_TEST_POWERDOWN_BMSK 0x4000000 |
| 464 | #define HWIO_SS_PHY_CTRL_TEST_POWERDOWN_SHFT 0x1a |
| 465 | #define HWIO_SS_PHY_CTRL_RTUNE_REQ_BMSK 0x2000000 |
| 466 | #define HWIO_SS_PHY_CTRL_RTUNE_REQ_SHFT 0x19 |
| 467 | #define HWIO_SS_PHY_CTRL_LANE0_PWR_PRESENT_BMSK 0x1000000 |
| 468 | #define HWIO_SS_PHY_CTRL_LANE0_PWR_PRESENT_SHFT 0x18 |
| 469 | #define HWIO_SS_PHY_CTRL_USB2_REF_CLK_EN_BMSK 0x800000 |
| 470 | #define HWIO_SS_PHY_CTRL_USB2_REF_CLK_EN_SHFT 0x17 |
| 471 | #define HWIO_SS_PHY_CTRL_USB2_REF_CLK_SEL_BMSK 0x400000 |
| 472 | #define HWIO_SS_PHY_CTRL_USB2_REF_CLK_SEL_SHFT 0x16 |
| 473 | #define HWIO_SS_PHY_CTRL_SSC_REF_CLK_SEL_BMSK 0x3fe000 |
| 474 | #define HWIO_SS_PHY_CTRL_SSC_REF_CLK_SEL_SHFT 0xd |
| 475 | #define HWIO_SS_PHY_CTRL_SSC_RANGE_BMSK 0x1c00 |
| 476 | #define HWIO_SS_PHY_CTRL_SSC_RANGE_SHFT 0xa |
| 477 | #define HWIO_SS_PHY_CTRL_REF_USB2_EN_BMSK 0x200 |
| 478 | #define HWIO_SS_PHY_CTRL_REF_USB2_EN_SHFT 0x9 |
| 479 | #define HWIO_SS_PHY_CTRL_REF_SS_PHY_EN_BMSK 0x100 |
| 480 | #define HWIO_SS_PHY_CTRL_REF_SS_PHY_EN_SHFT 0x8 |
| 481 | #define HWIO_SS_PHY_CTRL_SS_PHY_RESET_BMSK 0x80 |
| 482 | #define HWIO_SS_PHY_CTRL_SS_PHY_RESET_SHFT 0x7 |
| 483 | #define HWIO_SS_PHY_CTRL_MPLL_MULTI_BMSK 0x7f |
| 484 | #define HWIO_SS_PHY_CTRL_MPLL_MULTI_SHFT 0x0 |
| 485 | |
| 486 | #define HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x) ((x) + 0x00000034) |
| 487 | #define HWIO_SS_PHY_PARAM_CTRL_1_RMSK 0xffffffff |
| 488 | #define HWIO_SS_PHY_PARAM_CTRL_1_POR 0x0718154a |
| 489 | #define HWIO_SS_PHY_PARAM_CTRL_1_IN(x) \ |
| 490 | in_dword_masked(HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x), HWIO_SS_PHY_PARAM_CTRL_1_RMSK) |
| 491 | #define HWIO_SS_PHY_PARAM_CTRL_1_INM(x, m) \ |
| 492 | in_dword_masked(HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x), m) |
| 493 | #define HWIO_SS_PHY_PARAM_CTRL_1_OUT(x, v) \ |
| 494 | out_dword(HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x),v) |
| 495 | #define HWIO_SS_PHY_PARAM_CTRL_1_OUTM(x,m,v) \ |
| 496 | out_dword_masked_ns(HWIO_SS_PHY_PARAM_CTRL_1_ADDR(x),m,v,HWIO_SS_PHY_PARAM_CTRL_1_IN(x)) |
| 497 | #define HWIO_SS_PHY_PARAM_CTRL_1_LANE0_TX_TERM_OFFSET_BMSK 0xf8000000 |
| 498 | #define HWIO_SS_PHY_PARAM_CTRL_1_LANE0_TX_TERM_OFFSET_SHFT 0x1b |
| 499 | #define HWIO_SS_PHY_PARAM_CTRL_1_TX_SWING_FULL_BMSK 0x7f00000 |
| 500 | #define HWIO_SS_PHY_PARAM_CTRL_1_TX_SWING_FULL_SHFT 0x14 |
| 501 | #define HWIO_SS_PHY_PARAM_CTRL_1_TX_DEEMPH_6DB_BMSK 0xfc000 |
| 502 | #define HWIO_SS_PHY_PARAM_CTRL_1_TX_DEEMPH_6DB_SHFT 0xe |
| 503 | #define HWIO_SS_PHY_PARAM_CTRL_1_TX_DEEMPH_3_5DB_BMSK 0x3f00 |
| 504 | #define HWIO_SS_PHY_PARAM_CTRL_1_TX_DEEMPH_3_5DB_SHFT 0x8 |
| 505 | #define HWIO_SS_PHY_PARAM_CTRL_1_LOS_LEVEL_BMSK 0xf8 |
| 506 | #define HWIO_SS_PHY_PARAM_CTRL_1_LOS_LEVEL_SHFT 0x3 |
| 507 | #define HWIO_SS_PHY_PARAM_CTRL_1_LOS_BIAS_BMSK 0x7 |
| 508 | #define HWIO_SS_PHY_PARAM_CTRL_1_LOS_BIAS_SHFT 0x0 |
| 509 | |
| 510 | #define HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x) ((x) + 0x00000038) |
| 511 | #define HWIO_SS_PHY_PARAM_CTRL_2_RMSK 0x37 |
| 512 | #define HWIO_SS_PHY_PARAM_CTRL_2_POR 0x00000004 |
| 513 | #define HWIO_SS_PHY_PARAM_CTRL_2_IN(x) \ |
| 514 | in_dword_masked(HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x), HWIO_SS_PHY_PARAM_CTRL_2_RMSK) |
| 515 | #define HWIO_SS_PHY_PARAM_CTRL_2_INM(x, m) \ |
| 516 | in_dword_masked(HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x), m) |
| 517 | #define HWIO_SS_PHY_PARAM_CTRL_2_OUT(x, v) \ |
| 518 | out_dword(HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x),v) |
| 519 | #define HWIO_SS_PHY_PARAM_CTRL_2_OUTM(x,m,v) \ |
| 520 | out_dword_masked_ns(HWIO_SS_PHY_PARAM_CTRL_2_ADDR(x),m,v,HWIO_SS_PHY_PARAM_CTRL_2_IN(x)) |
| 521 | #define HWIO_SS_PHY_PARAM_CTRL_2_LANE0_TX2RX_LOOPBACK_BMSK 0x20 |
| 522 | #define HWIO_SS_PHY_PARAM_CTRL_2_LANE0_TX2RX_LOOPBACK_SHFT 0x5 |
| 523 | #define HWIO_SS_PHY_PARAM_CTRL_2_LANE0_EXT_PCLK_REQ_BMSK 0x10 |
| 524 | #define HWIO_SS_PHY_PARAM_CTRL_2_LANE0_EXT_PCLK_REQ_SHFT 0x4 |
| 525 | #define HWIO_SS_PHY_PARAM_CTRL_2_TX_VBOOST_LEVEL_BMSK 0x7 |
| 526 | #define HWIO_SS_PHY_PARAM_CTRL_2_TX_VBOOST_LEVEL_SHFT 0x0 |
| 527 | |
| 528 | #define HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x) ((x) + 0x0000003c) |
| 529 | #define HWIO_SS_CR_PROTOCOL_DATA_IN_RMSK 0xffff |
| 530 | #define HWIO_SS_CR_PROTOCOL_DATA_IN_POR 0x00000000 |
| 531 | #define HWIO_SS_CR_PROTOCOL_DATA_IN_IN(x) \ |
| 532 | in_dword_masked(HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x), HWIO_SS_CR_PROTOCOL_DATA_IN_RMSK) |
| 533 | #define HWIO_SS_CR_PROTOCOL_DATA_IN_INM(x, m) \ |
| 534 | in_dword_masked(HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x), m) |
| 535 | #define HWIO_SS_CR_PROTOCOL_DATA_IN_OUT(x, v) \ |
| 536 | out_dword(HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x),v) |
| 537 | #define HWIO_SS_CR_PROTOCOL_DATA_IN_OUTM(x,m,v) \ |
| 538 | out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_DATA_IN_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_DATA_IN_IN(x)) |
| 539 | #define HWIO_SS_CR_PROTOCOL_DATA_IN_SS_CR_DATA_IN_REG_BMSK 0xffff |
| 540 | #define HWIO_SS_CR_PROTOCOL_DATA_IN_SS_CR_DATA_IN_REG_SHFT 0x0 |
| 541 | |
| 542 | #define HWIO_SS_CR_PROTOCOL_DATA_OUT_ADDR(x) ((x) + 0x00000040) |
| 543 | #define HWIO_SS_CR_PROTOCOL_DATA_OUT_RMSK 0xffff |
| 544 | #define HWIO_SS_CR_PROTOCOL_DATA_OUT_POR 0x00000000 |
| 545 | #define HWIO_SS_CR_PROTOCOL_DATA_OUT_IN(x) \ |
| 546 | in_dword_masked(HWIO_SS_CR_PROTOCOL_DATA_OUT_ADDR(x), HWIO_SS_CR_PROTOCOL_DATA_OUT_RMSK) |
| 547 | #define HWIO_SS_CR_PROTOCOL_DATA_OUT_INM(x, m) \ |
| 548 | in_dword_masked(HWIO_SS_CR_PROTOCOL_DATA_OUT_ADDR(x), m) |
| 549 | #define HWIO_SS_CR_PROTOCOL_DATA_OUT_SS_CR_DATA_OUT_REG_BMSK 0xffff |
| 550 | #define HWIO_SS_CR_PROTOCOL_DATA_OUT_SS_CR_DATA_OUT_REG_SHFT 0x0 |
| 551 | |
| 552 | #define HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x) ((x) + 0x00000044) |
| 553 | #define HWIO_SS_CR_PROTOCOL_CAP_ADDR_RMSK 0x1 |
| 554 | #define HWIO_SS_CR_PROTOCOL_CAP_ADDR_POR 0x00000000 |
| 555 | #define HWIO_SS_CR_PROTOCOL_CAP_ADDR_IN(x) \ |
| 556 | in_dword_masked(HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x), HWIO_SS_CR_PROTOCOL_CAP_ADDR_RMSK) |
| 557 | #define HWIO_SS_CR_PROTOCOL_CAP_ADDR_INM(x, m) \ |
| 558 | in_dword_masked(HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x), m) |
| 559 | #define HWIO_SS_CR_PROTOCOL_CAP_ADDR_OUT(x, v) \ |
| 560 | out_dword(HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x),v) |
| 561 | #define HWIO_SS_CR_PROTOCOL_CAP_ADDR_OUTM(x,m,v) \ |
| 562 | out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_CAP_ADDR_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_CAP_ADDR_IN(x)) |
| 563 | #define HWIO_SS_CR_PROTOCOL_CAP_ADDR_SS_CR_CAP_ADDR_REG_BMSK 0x1 |
| 564 | #define HWIO_SS_CR_PROTOCOL_CAP_ADDR_SS_CR_CAP_ADDR_REG_SHFT 0x0 |
| 565 | |
| 566 | #define HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x) ((x) + 0x00000048) |
| 567 | #define HWIO_SS_CR_PROTOCOL_CAP_DATA_RMSK 0x1 |
| 568 | #define HWIO_SS_CR_PROTOCOL_CAP_DATA_POR 0x00000000 |
| 569 | #define HWIO_SS_CR_PROTOCOL_CAP_DATA_IN(x) \ |
| 570 | in_dword_masked(HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x), HWIO_SS_CR_PROTOCOL_CAP_DATA_RMSK) |
| 571 | #define HWIO_SS_CR_PROTOCOL_CAP_DATA_INM(x, m) \ |
| 572 | in_dword_masked(HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x), m) |
| 573 | #define HWIO_SS_CR_PROTOCOL_CAP_DATA_OUT(x, v) \ |
| 574 | out_dword(HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x),v) |
| 575 | #define HWIO_SS_CR_PROTOCOL_CAP_DATA_OUTM(x,m,v) \ |
| 576 | out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_CAP_DATA_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_CAP_DATA_IN(x)) |
| 577 | #define HWIO_SS_CR_PROTOCOL_CAP_DATA_SS_CR_CAP_DATA_REG_BMSK 0x1 |
| 578 | #define HWIO_SS_CR_PROTOCOL_CAP_DATA_SS_CR_CAP_DATA_REG_SHFT 0x0 |
| 579 | |
| 580 | #define HWIO_SS_CR_PROTOCOL_READ_ADDR(x) ((x) + 0x0000004c) |
| 581 | #define HWIO_SS_CR_PROTOCOL_READ_RMSK 0x1 |
| 582 | #define HWIO_SS_CR_PROTOCOL_READ_POR 0x00000000 |
| 583 | #define HWIO_SS_CR_PROTOCOL_READ_IN(x) \ |
| 584 | in_dword_masked(HWIO_SS_CR_PROTOCOL_READ_ADDR(x), HWIO_SS_CR_PROTOCOL_READ_RMSK) |
| 585 | #define HWIO_SS_CR_PROTOCOL_READ_INM(x, m) \ |
| 586 | in_dword_masked(HWIO_SS_CR_PROTOCOL_READ_ADDR(x), m) |
| 587 | #define HWIO_SS_CR_PROTOCOL_READ_OUT(x, v) \ |
| 588 | out_dword(HWIO_SS_CR_PROTOCOL_READ_ADDR(x),v) |
| 589 | #define HWIO_SS_CR_PROTOCOL_READ_OUTM(x,m,v) \ |
| 590 | out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_READ_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_READ_IN(x)) |
| 591 | #define HWIO_SS_CR_PROTOCOL_READ_SS_CR_READ_REG_BMSK 0x1 |
| 592 | #define HWIO_SS_CR_PROTOCOL_READ_SS_CR_READ_REG_SHFT 0x0 |
| 593 | |
| 594 | #define HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x) ((x) + 0x00000050) |
| 595 | #define HWIO_SS_CR_PROTOCOL_WRITE_RMSK 0x1 |
| 596 | #define HWIO_SS_CR_PROTOCOL_WRITE_POR 0x00000000 |
| 597 | #define HWIO_SS_CR_PROTOCOL_WRITE_IN(x) \ |
| 598 | in_dword_masked(HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x), HWIO_SS_CR_PROTOCOL_WRITE_RMSK) |
| 599 | #define HWIO_SS_CR_PROTOCOL_WRITE_INM(x, m) \ |
| 600 | in_dword_masked(HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x), m) |
| 601 | #define HWIO_SS_CR_PROTOCOL_WRITE_OUT(x, v) \ |
| 602 | out_dword(HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x),v) |
| 603 | #define HWIO_SS_CR_PROTOCOL_WRITE_OUTM(x,m,v) \ |
| 604 | out_dword_masked_ns(HWIO_SS_CR_PROTOCOL_WRITE_ADDR(x),m,v,HWIO_SS_CR_PROTOCOL_WRITE_IN(x)) |
| 605 | #define HWIO_SS_CR_PROTOCOL_WRITE_SS_CR_WRITE_REG_BMSK 0x1 |
| 606 | #define HWIO_SS_CR_PROTOCOL_WRITE_SS_CR_WRITE_REG_SHFT 0x0 |
| 607 | |
| 608 | #define HWIO_SS_STATUS_READ_ONLY_ADDR(x) ((x) + 0x00000054) |
| 609 | #define HWIO_SS_STATUS_READ_ONLY_RMSK 0x3 |
| 610 | #define HWIO_SS_STATUS_READ_ONLY_POR 0x00000000 |
| 611 | #define HWIO_SS_STATUS_READ_ONLY_IN(x) \ |
| 612 | in_dword_masked(HWIO_SS_STATUS_READ_ONLY_ADDR(x), HWIO_SS_STATUS_READ_ONLY_RMSK) |
| 613 | #define HWIO_SS_STATUS_READ_ONLY_INM(x, m) \ |
| 614 | in_dword_masked(HWIO_SS_STATUS_READ_ONLY_ADDR(x), m) |
| 615 | #define HWIO_SS_STATUS_READ_ONLY_REF_CLKREQ_N_BMSK 0x2 |
| 616 | #define HWIO_SS_STATUS_READ_ONLY_REF_CLKREQ_N_SHFT 0x1 |
| 617 | #define HWIO_SS_STATUS_READ_ONLY_RTUNE_ACK_BMSK 0x1 |
| 618 | #define HWIO_SS_STATUS_READ_ONLY_RTUNE_ACK_SHFT 0x0 |
| 619 | |
| 620 | #define HWIO_PWR_EVNT_IRQ_STAT_ADDR(x) ((x) + 0x00000058) |
| 621 | #define HWIO_PWR_EVNT_IRQ_STAT_RMSK 0x3f |
| 622 | #define HWIO_PWR_EVNT_IRQ_STAT_POR 0x00000000 |
| 623 | #define HWIO_PWR_EVNT_IRQ_STAT_IN(x) \ |
| 624 | in_dword_masked(HWIO_PWR_EVNT_IRQ_STAT_ADDR(x), HWIO_PWR_EVNT_IRQ_STAT_RMSK) |
| 625 | #define HWIO_PWR_EVNT_IRQ_STAT_INM(x, m) \ |
| 626 | in_dword_masked(HWIO_PWR_EVNT_IRQ_STAT_ADDR(x), m) |
| 627 | #define HWIO_PWR_EVNT_IRQ_STAT_OUT(x, v) \ |
| 628 | out_dword(HWIO_PWR_EVNT_IRQ_STAT_ADDR(x),v) |
| 629 | #define HWIO_PWR_EVNT_IRQ_STAT_OUTM(x,m,v) \ |
| 630 | out_dword_masked_ns(HWIO_PWR_EVNT_IRQ_STAT_ADDR(x),m,v,HWIO_PWR_EVNT_IRQ_STAT_IN(x)) |
| 631 | #define HWIO_PWR_EVNT_IRQ_STAT_LPM_OUT_L2_IRQ_STAT_BMSK 0x20 |
| 632 | #define HWIO_PWR_EVNT_IRQ_STAT_LPM_OUT_L2_IRQ_STAT_SHFT 0x5 |
| 633 | #define HWIO_PWR_EVNT_IRQ_STAT_LPM_IN_L2_IRQ_STAT_BMSK 0x10 |
| 634 | #define HWIO_PWR_EVNT_IRQ_STAT_LPM_IN_L2_IRQ_STAT_SHFT 0x4 |
| 635 | #define HWIO_PWR_EVNT_IRQ_STAT_POWERDOWN_OUT_P3_IRQ_STAT_BMSK 0x8 |
| 636 | #define HWIO_PWR_EVNT_IRQ_STAT_POWERDOWN_OUT_P3_IRQ_STAT_SHFT 0x3 |
| 637 | #define HWIO_PWR_EVNT_IRQ_STAT_POWERDOWN_IN_P3_IRQ_STAT_BMSK 0x4 |
| 638 | #define HWIO_PWR_EVNT_IRQ_STAT_POWERDOWN_IN_P3_IRQ_STAT_SHFT 0x2 |
| 639 | #define HWIO_PWR_EVNT_IRQ_STAT_CLK_REQ_IN_P3_IRQ_STAT_BMSK 0x2 |
| 640 | #define HWIO_PWR_EVNT_IRQ_STAT_CLK_REQ_IN_P3_IRQ_STAT_SHFT 0x1 |
| 641 | #define HWIO_PWR_EVNT_IRQ_STAT_CLK_GATE_IN_P3_IRQ_STAT_BMSK 0x1 |
| 642 | #define HWIO_PWR_EVNT_IRQ_STAT_CLK_GATE_IN_P3_IRQ_STAT_SHFT 0x0 |
| 643 | |
| 644 | #define HWIO_PWR_EVNT_IRQ_MASK_ADDR(x) ((x) + 0x0000005c) |
| 645 | #define HWIO_PWR_EVNT_IRQ_MASK_RMSK 0x3f |
| 646 | #define HWIO_PWR_EVNT_IRQ_MASK_POR 0x00000000 |
| 647 | #define HWIO_PWR_EVNT_IRQ_MASK_IN(x) \ |
| 648 | in_dword_masked(HWIO_PWR_EVNT_IRQ_MASK_ADDR(x), HWIO_PWR_EVNT_IRQ_MASK_RMSK) |
| 649 | #define HWIO_PWR_EVNT_IRQ_MASK_INM(x, m) \ |
| 650 | in_dword_masked(HWIO_PWR_EVNT_IRQ_MASK_ADDR(x), m) |
| 651 | #define HWIO_PWR_EVNT_IRQ_MASK_OUT(x, v) \ |
| 652 | out_dword(HWIO_PWR_EVNT_IRQ_MASK_ADDR(x),v) |
| 653 | #define HWIO_PWR_EVNT_IRQ_MASK_OUTM(x,m,v) \ |
| 654 | out_dword_masked_ns(HWIO_PWR_EVNT_IRQ_MASK_ADDR(x),m,v,HWIO_PWR_EVNT_IRQ_MASK_IN(x)) |
| 655 | #define HWIO_PWR_EVNT_IRQ_MASK_LPM_OUT_L2_IRQ_MASK_BMSK 0x20 |
| 656 | #define HWIO_PWR_EVNT_IRQ_MASK_LPM_OUT_L2_IRQ_MASK_SHFT 0x5 |
| 657 | #define HWIO_PWR_EVNT_IRQ_MASK_LPM_IN_L2_IRQ_MASK_BMSK 0x10 |
| 658 | #define HWIO_PWR_EVNT_IRQ_MASK_LPM_IN_L2_IRQ_MASK_SHFT 0x4 |
| 659 | #define HWIO_PWR_EVNT_IRQ_MASK_POWERDOWN_OUT_P3_IRQ_MASK_BMSK 0x8 |
| 660 | #define HWIO_PWR_EVNT_IRQ_MASK_POWERDOWN_OUT_P3_IRQ_MASK_SHFT 0x3 |
| 661 | #define HWIO_PWR_EVNT_IRQ_MASK_POWERDOWN_IN_P3_IRQ_MASK_BMSK 0x4 |
| 662 | #define HWIO_PWR_EVNT_IRQ_MASK_POWERDOWN_IN_P3_IRQ_MASK_SHFT 0x2 |
| 663 | #define HWIO_PWR_EVNT_IRQ_MASK_CLK_REQ_IN_P3_IRQ_MASK_BMSK 0x2 |
| 664 | #define HWIO_PWR_EVNT_IRQ_MASK_CLK_REQ_IN_P3_IRQ_MASK_SHFT 0x1 |
| 665 | #define HWIO_PWR_EVNT_IRQ_MASK_CLK_GATE_IN_P3_IRQ_MASK_BMSK 0x1 |
| 666 | #define HWIO_PWR_EVNT_IRQ_MASK_CLK_GATE_IN_P3_IRQ_MASK_SHFT 0x0 |
| 667 | |
| 668 | #define HWIO_HW_SW_EVT_CTRL_REG_ADDR(x) ((x) + 0x00000060) |
| 669 | #define HWIO_HW_SW_EVT_CTRL_REG_RMSK 0x131 |
| 670 | #define HWIO_HW_SW_EVT_CTRL_REG_POR 0x00000001 |
| 671 | #define HWIO_HW_SW_EVT_CTRL_REG_IN(x) \ |
| 672 | in_dword_masked(HWIO_HW_SW_EVT_CTRL_REG_ADDR(x), HWIO_HW_SW_EVT_CTRL_REG_RMSK) |
| 673 | #define HWIO_HW_SW_EVT_CTRL_REG_INM(x, m) \ |
| 674 | in_dword_masked(HWIO_HW_SW_EVT_CTRL_REG_ADDR(x), m) |
| 675 | #define HWIO_HW_SW_EVT_CTRL_REG_OUT(x, v) \ |
| 676 | out_dword(HWIO_HW_SW_EVT_CTRL_REG_ADDR(x),v) |
| 677 | #define HWIO_HW_SW_EVT_CTRL_REG_OUTM(x,m,v) \ |
| 678 | out_dword_masked_ns(HWIO_HW_SW_EVT_CTRL_REG_ADDR(x),m,v,HWIO_HW_SW_EVT_CTRL_REG_IN(x)) |
| 679 | #define HWIO_HW_SW_EVT_CTRL_REG_SW_EVT_MUX_SEL_BMSK 0x100 |
| 680 | #define HWIO_HW_SW_EVT_CTRL_REG_SW_EVT_MUX_SEL_SHFT 0x8 |
| 681 | #define HWIO_HW_SW_EVT_CTRL_REG_HW_EVT_MUX_CTRL_BMSK 0x30 |
| 682 | #define HWIO_HW_SW_EVT_CTRL_REG_HW_EVT_MUX_CTRL_SHFT 0x4 |
| 683 | #define HWIO_HW_SW_EVT_CTRL_REG_EVENT_BUS_HALT_BMSK 0x1 |
| 684 | #define HWIO_HW_SW_EVT_CTRL_REG_EVENT_BUS_HALT_SHFT 0x0 |
| 685 | |
| 686 | #define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x) ((x) + 0x00000064) |
| 687 | #define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_RMSK 0x7 |
| 688 | #define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_POR 0x00000000 |
| 689 | #define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_IN(x) \ |
| 690 | in_dword_masked(HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x), HWIO_VMIDMT_AMEMTYPE_CTRL_REG_RMSK) |
| 691 | #define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_INM(x, m) \ |
| 692 | in_dword_masked(HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x), m) |
| 693 | #define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_OUT(x, v) \ |
| 694 | out_dword(HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x),v) |
| 695 | #define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_OUTM(x,m,v) \ |
| 696 | out_dword_masked_ns(HWIO_VMIDMT_AMEMTYPE_CTRL_REG_ADDR(x),m,v,HWIO_VMIDMT_AMEMTYPE_CTRL_REG_IN(x)) |
| 697 | #define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_VMIDMT_AMEMTYPE_VALUE_BMSK 0x7 |
| 698 | #define HWIO_VMIDMT_AMEMTYPE_CTRL_REG_VMIDMT_AMEMTYPE_VALUE_SHFT 0x0 |
| 699 | |
| 700 | #define HWIO_FLADJ_30MHZ_REG_ADDR(x) ((x) + 0x00000068) |
| 701 | #define HWIO_FLADJ_30MHZ_REG_RMSK 0x3f |
| 702 | #define HWIO_FLADJ_30MHZ_REG_POR 0x00000020 |
| 703 | #define HWIO_FLADJ_30MHZ_REG_IN(x) \ |
| 704 | in_dword_masked(HWIO_FLADJ_30MHZ_REG_ADDR(x), HWIO_FLADJ_30MHZ_REG_RMSK) |
| 705 | #define HWIO_FLADJ_30MHZ_REG_INM(x, m) \ |
| 706 | in_dword_masked(HWIO_FLADJ_30MHZ_REG_ADDR(x), m) |
| 707 | #define HWIO_FLADJ_30MHZ_REG_OUT(x, v) \ |
| 708 | out_dword(HWIO_FLADJ_30MHZ_REG_ADDR(x),v) |
| 709 | #define HWIO_FLADJ_30MHZ_REG_OUTM(x,m,v) \ |
| 710 | out_dword_masked_ns(HWIO_FLADJ_30MHZ_REG_ADDR(x),m,v,HWIO_FLADJ_30MHZ_REG_IN(x)) |
| 711 | #define HWIO_FLADJ_30MHZ_REG_FLADJ_30MHZ_VALUE_BMSK 0x3f |
| 712 | #define HWIO_FLADJ_30MHZ_REG_FLADJ_30MHZ_VALUE_SHFT 0x0 |
| 713 | |
| 714 | #define HWIO_M_AW_USER_REG_ADDR(x) ((x) + 0x0000006c) |
| 715 | #define HWIO_M_AW_USER_REG_RMSK 0x97f |
| 716 | #define HWIO_M_AW_USER_REG_POR 0x00000122 |
| 717 | #define HWIO_M_AW_USER_REG_IN(x) \ |
| 718 | in_dword_masked(HWIO_M_AW_USER_REG_ADDR(x), HWIO_M_AW_USER_REG_RMSK) |
| 719 | #define HWIO_M_AW_USER_REG_INM(x, m) \ |
| 720 | in_dword_masked(HWIO_M_AW_USER_REG_ADDR(x), m) |
| 721 | #define HWIO_M_AW_USER_REG_OUT(x, v) \ |
| 722 | out_dword(HWIO_M_AW_USER_REG_ADDR(x),v) |
| 723 | #define HWIO_M_AW_USER_REG_OUTM(x,m,v) \ |
| 724 | out_dword_masked_ns(HWIO_M_AW_USER_REG_ADDR(x),m,v,HWIO_M_AW_USER_REG_IN(x)) |
| 725 | #define HWIO_M_AW_USER_REG_AW_MEMTYPE_1_SEL_BMSK 0x800 |
| 726 | #define HWIO_M_AW_USER_REG_AW_MEMTYPE_1_SEL_SHFT 0xb |
| 727 | #define HWIO_M_AW_USER_REG_AW_NOALLOACATE_BMSK 0x100 |
| 728 | #define HWIO_M_AW_USER_REG_AW_NOALLOACATE_SHFT 0x8 |
| 729 | #define HWIO_M_AW_USER_REG_AW_MEMTYPE_BMSK 0x70 |
| 730 | #define HWIO_M_AW_USER_REG_AW_MEMTYPE_SHFT 0x4 |
| 731 | #define HWIO_M_AW_USER_REG_AW_CACHE_BMSK 0xf |
| 732 | #define HWIO_M_AW_USER_REG_AW_CACHE_SHFT 0x0 |
| 733 | |
| 734 | #define HWIO_M_AR_USER_REG_ADDR(x) ((x) + 0x00000070) |
| 735 | #define HWIO_M_AR_USER_REG_RMSK 0x97f |
| 736 | #define HWIO_M_AR_USER_REG_POR 0x00000122 |
| 737 | #define HWIO_M_AR_USER_REG_IN(x) \ |
| 738 | in_dword_masked(HWIO_M_AR_USER_REG_ADDR(x), HWIO_M_AR_USER_REG_RMSK) |
| 739 | #define HWIO_M_AR_USER_REG_INM(x, m) \ |
| 740 | in_dword_masked(HWIO_M_AR_USER_REG_ADDR(x), m) |
| 741 | #define HWIO_M_AR_USER_REG_OUT(x, v) \ |
| 742 | out_dword(HWIO_M_AR_USER_REG_ADDR(x),v) |
| 743 | #define HWIO_M_AR_USER_REG_OUTM(x,m,v) \ |
| 744 | out_dword_masked_ns(HWIO_M_AR_USER_REG_ADDR(x),m,v,HWIO_M_AR_USER_REG_IN(x)) |
| 745 | #define HWIO_M_AR_USER_REG_AR_MEMTYPE_1_SEL_BMSK 0x800 |
| 746 | #define HWIO_M_AR_USER_REG_AR_MEMTYPE_1_SEL_SHFT 0xb |
| 747 | #define HWIO_M_AR_USER_REG_AR_NOALLOACATE_BMSK 0x100 |
| 748 | #define HWIO_M_AR_USER_REG_AR_NOALLOACATE_SHFT 0x8 |
| 749 | #define HWIO_M_AR_USER_REG_AR_MEMTYPE_BMSK 0x70 |
| 750 | #define HWIO_M_AR_USER_REG_AR_MEMTYPE_SHFT 0x4 |
| 751 | #define HWIO_M_AR_USER_REG_AR_CACHE_BMSK 0xf |
| 752 | #define HWIO_M_AR_USER_REG_AR_CACHE_SHFT 0x0 |
| 753 | |
| 754 | #define HWIO_QSCRTCH_REG_n_ADDR(base,n) ((base) + 0x00000074 + 0x4 * (n)) |
| 755 | #define HWIO_QSCRTCH_REG_n_RMSK 0xffffffff |
| 756 | #define HWIO_QSCRTCH_REG_n_MAXn 2 |
| 757 | #define HWIO_QSCRTCH_REG_n_POR 0x00000000 |
| 758 | #define HWIO_QSCRTCH_REG_n_INI(base,n) \ |
| 759 | in_dword_masked(HWIO_QSCRTCH_REG_n_ADDR(base,n), HWIO_QSCRTCH_REG_n_RMSK) |
| 760 | #define HWIO_QSCRTCH_REG_n_INMI(base,n,mask) \ |
| 761 | in_dword_masked(HWIO_QSCRTCH_REG_n_ADDR(base,n), mask) |
| 762 | #define HWIO_QSCRTCH_REG_n_OUTI(base,n,val) \ |
| 763 | out_dword(HWIO_QSCRTCH_REG_n_ADDR(base,n),val) |
| 764 | #define HWIO_QSCRTCH_REG_n_OUTMI(base,n,mask,val) \ |
| 765 | out_dword_masked_ns(HWIO_QSCRTCH_REG_n_ADDR(base,n),mask,val,HWIO_QSCRTCH_REG_n_INI(base,n)) |
| 766 | #define HWIO_QSCRTCH_REG_n_QSCRTCH_REG_BMSK 0xffffffff |
| 767 | #define HWIO_QSCRTCH_REG_n_QSCRTCH_REG_SHFT 0x0 |
| 768 | |
| 769 | |
| 770 | #endif /* __DWC_USB30_QSCRATCH_HWIO_H__ */ |