Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 32 | #include <err.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 33 | #include <msm_panel.h> |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 34 | #include <mipi_dsi.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <board.h> |
| 38 | #include <mdp5.h> |
Aravind Venkateswaran | 2713dc9 | 2013-09-19 15:23:34 -0700 | [diff] [blame] | 39 | #include <scm.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 40 | #include <platform/gpio.h> |
| 41 | #include <platform/iomap.h> |
| 42 | #include <target/display.h> |
| 43 | |
Casey Piper | cbdfbd2 | 2013-08-14 17:22:16 -0700 | [diff] [blame] | 44 | #include "include/panel.h" |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 45 | #include "include/display_resource.h" |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 46 | |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 47 | #define HFPLL_LDO_ID 8 |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 48 | #define MAX_M_SEQ_COUNTER 7 |
Sandeep Panda | abe9ad4 | 2015-08-21 12:20:40 +0530 | [diff] [blame] | 49 | #define DSI_PLL_POLL_MAX_READS 10 |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 50 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 51 | static struct pm8x41_wled_data wled_ctrl = { |
rayzhang | a3667cd | 2013-07-01 12:22:54 +0800 | [diff] [blame] | 52 | .mod_scheme = 0x00, |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 53 | .led1_brightness = (0x0F << 8) | 0xEF, |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 54 | .max_duty_cycle = 0x01, |
rayzhang | a3667cd | 2013-07-01 12:22:54 +0800 | [diff] [blame] | 55 | .ovp = 0x0, |
Zhenhua Huang | d5355cb | 2013-09-04 16:03:01 +0800 | [diff] [blame] | 56 | .full_current_scale = 0x19, |
| 57 | .fdbck = 0x1 |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 58 | }; |
| 59 | |
Sandeep Panda | abe9ad4 | 2015-08-21 12:20:40 +0530 | [diff] [blame] | 60 | static int mdss_dsi_pll_lock_status(uint32_t ctl_base) |
| 61 | { |
| 62 | int pll_locked = 0, i = 0; |
| 63 | |
| 64 | while (i < DSI_PLL_POLL_MAX_READS) { |
| 65 | pll_locked = (readl(ctl_base + 0x02c0) & 0x01); |
| 66 | if (pll_locked) |
| 67 | break; |
| 68 | udelay(50); |
| 69 | i++; |
| 70 | } |
| 71 | return pll_locked; |
| 72 | } |
| 73 | |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 74 | static uint32_t dsi_pll_enable_seq_m(uint32_t ctl_base) |
| 75 | { |
| 76 | uint32_t i = 0; |
| 77 | uint32_t pll_locked = 0; |
| 78 | |
| 79 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 80 | |
| 81 | /* |
| 82 | * Add hardware recommended delays between register writes for |
| 83 | * the updates to take effect. These delays are necessary for the |
| 84 | * PLL to successfully lock |
| 85 | */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 86 | writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/ |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 87 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 88 | udelay(200); |
| 89 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 90 | udelay(200); |
| 91 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 92 | udelay(600); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 93 | |
| 94 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
Sandeep Panda | abe9ad4 | 2015-08-21 12:20:40 +0530 | [diff] [blame] | 95 | pll_locked = mdss_dsi_pll_lock_status(ctl_base); |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 96 | for (i = 0; (i < MAX_M_SEQ_COUNTER) && !pll_locked; i++) { |
| 97 | writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */ |
| 98 | udelay(50); |
| 99 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 100 | udelay(100); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 101 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 102 | udelay(600); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 103 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
Sandeep Panda | abe9ad4 | 2015-08-21 12:20:40 +0530 | [diff] [blame] | 104 | pll_locked = mdss_dsi_pll_lock_status(ctl_base); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | return pll_locked; |
| 108 | } |
| 109 | |
| 110 | static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base) |
| 111 | { |
| 112 | uint32_t pll_locked = 0; |
| 113 | |
| 114 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 115 | |
| 116 | /* |
| 117 | * Add hardware recommended delays between register writes for |
| 118 | * the updates to take effect. These delays are necessary for the |
| 119 | * PLL to successfully lock |
| 120 | */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 121 | writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */ |
| 122 | udelay(50); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 123 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 124 | udelay(200); |
| 125 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 126 | udelay(200); |
| 127 | writel(0x07, ctl_base + 0x0220); /* GLB CFG */ |
| 128 | udelay(200); |
| 129 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 130 | udelay(200); |
| 131 | writel(0x07, ctl_base + 0x0220); /* GLB CFG */ |
| 132 | udelay(200); |
| 133 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 134 | udelay(600); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 135 | |
| 136 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
Sandeep Panda | abe9ad4 | 2015-08-21 12:20:40 +0530 | [diff] [blame] | 137 | pll_locked = mdss_dsi_pll_lock_status(ctl_base); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 138 | |
| 139 | return pll_locked; |
| 140 | } |
| 141 | |
| 142 | static uint32_t dsi_pll_enable_seq_f1(uint32_t ctl_base) |
| 143 | { |
| 144 | uint32_t pll_locked = 0; |
| 145 | |
| 146 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 147 | |
| 148 | /* |
| 149 | * Add hardware recommended delays between register writes for |
| 150 | * the updates to take effect. These delays are necessary for the |
| 151 | * PLL to successfully lock |
| 152 | */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 153 | writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */ |
| 154 | udelay(50); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 155 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 156 | udelay(200); |
| 157 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 158 | udelay(200); |
| 159 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 160 | udelay(200); |
| 161 | writel(0x0d, ctl_base + 0x0220); /* GLB CFG */ |
| 162 | udelay(200); |
| 163 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 164 | udelay(600); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 165 | |
| 166 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
Sandeep Panda | abe9ad4 | 2015-08-21 12:20:40 +0530 | [diff] [blame] | 167 | pll_locked = mdss_dsi_pll_lock_status(ctl_base); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 168 | |
| 169 | return pll_locked; |
| 170 | } |
| 171 | |
| 172 | static uint32_t dsi_pll_enable_seq_c(uint32_t ctl_base) |
| 173 | { |
| 174 | uint32_t pll_locked = 0; |
| 175 | |
| 176 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 177 | |
| 178 | /* |
| 179 | * Add hardware recommended delays between register writes for |
| 180 | * the updates to take effect. These delays are necessary for the |
| 181 | * PLL to successfully lock |
| 182 | */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 183 | writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */ |
| 184 | udelay(50); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 185 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 186 | udelay(200); |
| 187 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 188 | udelay(200); |
| 189 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 190 | udelay(600); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 191 | |
| 192 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
Sandeep Panda | abe9ad4 | 2015-08-21 12:20:40 +0530 | [diff] [blame] | 193 | pll_locked = mdss_dsi_pll_lock_status(ctl_base); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 194 | |
| 195 | return pll_locked; |
| 196 | } |
| 197 | |
| 198 | static uint32_t dsi_pll_enable_seq_e(uint32_t ctl_base) |
| 199 | { |
| 200 | uint32_t pll_locked = 0; |
| 201 | |
| 202 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 203 | |
| 204 | /* |
| 205 | * Add hardware recommended delays between register writes for |
| 206 | * the updates to take effect. These delays are necessary for the |
| 207 | * PLL to successfully lock |
| 208 | */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 209 | writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */ |
| 210 | udelay(50); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 211 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 212 | udelay(200); |
| 213 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 214 | udelay(200); |
| 215 | writel(0x0d, ctl_base + 0x0220); /* GLB CFG */ |
| 216 | udelay(1); |
| 217 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 218 | udelay(600); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 219 | |
| 220 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
Sandeep Panda | abe9ad4 | 2015-08-21 12:20:40 +0530 | [diff] [blame] | 221 | pll_locked = mdss_dsi_pll_lock_status(ctl_base); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 222 | |
| 223 | return pll_locked; |
| 224 | } |
| 225 | |
Vineet Bajaj | 0d557f4 | 2014-05-15 19:06:27 +0530 | [diff] [blame] | 226 | static int msm8226_wled_backlight_ctrl(uint8_t enable) |
| 227 | { |
| 228 | if (enable) { |
| 229 | pm8x41_wled_config(&wled_ctrl); |
| 230 | pm8x41_wled_sink_control(enable); |
| 231 | pm8x41_wled_iled_sync_control(enable); |
| 232 | pm8x41_wled_led_mod_enable(enable); |
| 233 | } |
| 234 | pm8x41_wled_enable(enable); |
| 235 | |
| 236 | return NO_ERROR; |
| 237 | } |
| 238 | |
| 239 | static int msm8226_pwm_backlight_ctrl(int gpio_num, int lpg_chan, int enable) |
| 240 | { |
| 241 | struct pm8x41_gpio gpio_param = { |
| 242 | .direction = PM_GPIO_DIR_OUT, |
| 243 | .function = PM_GPIO_FUNC_2, |
| 244 | .vin_sel = 2, /* VIN_2 */ |
| 245 | .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10, |
| 246 | .output_buffer = PM_GPIO_OUT_CMOS, |
| 247 | .out_strength = PM_GPIO_OUT_DRIVE_HIGH, |
| 248 | }; |
| 249 | |
| 250 | dprintf(SPEW, "%s: gpio=%d lpg=%d enable=%d\n", __func__, |
| 251 | gpio_num, lpg_chan, enable); |
| 252 | |
| 253 | if (enable) { |
| 254 | pm8x41_gpio_config(gpio_num, &gpio_param); |
| 255 | pm8x41_lpg_write(lpg_chan, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */ |
| 256 | pm8x41_lpg_write(lpg_chan, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */ |
| 257 | pm8x41_lpg_write(lpg_chan, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */ |
| 258 | pm8x41_lpg_write(lpg_chan, 0x44, 0xb2); /* LPG_VALUE_LSB */ |
| 259 | pm8x41_lpg_write(lpg_chan, 0x45, 0x01); /* LPG_VALUE_MSB */ |
| 260 | pm8x41_lpg_write(lpg_chan, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */ |
| 261 | } else { |
| 262 | pm8x41_lpg_write(lpg_chan, 0x46, 0x00); |
| 263 | } |
| 264 | |
| 265 | return NO_ERROR; |
| 266 | } |
| 267 | |
| 268 | |
Kuogee Hsieh | 7c3982a | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 269 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 270 | { |
Vineet Bajaj | 0d557f4 | 2014-05-15 19:06:27 +0530 | [diff] [blame] | 271 | uint32_t ret = NO_ERROR; |
| 272 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 273 | dprintf(SPEW, "target_backlight_ctrl\n"); |
| 274 | |
Kuogee Hsieh | 7c3982a | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 275 | if (!bl) { |
| 276 | dprintf(CRITICAL, "backlight structure is not available\n"); |
| 277 | return ERR_INVALID_ARGS; |
| 278 | } |
| 279 | |
Vineet Bajaj | 0d557f4 | 2014-05-15 19:06:27 +0530 | [diff] [blame] | 280 | switch (bl->bl_interface_type) { |
| 281 | case BL_WLED: |
| 282 | ret = msm8226_wled_backlight_ctrl(enable); |
| 283 | break; |
| 284 | case BL_PWM: |
| 285 | ret = msm8226_pwm_backlight_ctrl(pwm_gpio.pin_id, |
| 286 | PWM_BL_LPG_CHAN_ID, |
| 287 | enable); |
| 288 | break; |
| 289 | default: |
| 290 | dprintf(CRITICAL, "backlight type:%d not supported\n", |
Kuogee Hsieh | 7c3982a | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 291 | bl->bl_interface_type); |
Vineet Bajaj | 0d557f4 | 2014-05-15 19:06:27 +0530 | [diff] [blame] | 292 | return ERR_NOT_SUPPORTED; |
Kuogee Hsieh | 7c3982a | 2013-12-18 14:13:45 -0800 | [diff] [blame] | 293 | } |
| 294 | |
Vineet Bajaj | 0d557f4 | 2014-05-15 19:06:27 +0530 | [diff] [blame] | 295 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 296 | } |
| 297 | |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 298 | static void dsi_pll_enable_seq(uint32_t ctl_base) |
| 299 | { |
| 300 | if (dsi_pll_enable_seq_m(ctl_base)) { |
Sandeep Panda | 0ce96e9 | 2015-05-13 12:24:10 +0530 | [diff] [blame] | 301 | } else if (dsi_pll_enable_seq_m(ctl_base)) { |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 302 | } else if (dsi_pll_enable_seq_d(ctl_base)) { |
| 303 | } else if (dsi_pll_enable_seq_d(ctl_base)) { |
| 304 | } else if (dsi_pll_enable_seq_f1(ctl_base)) { |
| 305 | } else if (dsi_pll_enable_seq_c(ctl_base)) { |
| 306 | } else if (dsi_pll_enable_seq_e(ctl_base)) { |
| 307 | } else { |
| 308 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
| 309 | } |
| 310 | } |
| 311 | |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 312 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 313 | { |
Aravind Venkateswaran | 2713dc9 | 2013-09-19 15:23:34 -0700 | [diff] [blame] | 314 | int32_t ret; |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 315 | struct mdss_dsi_pll_config *pll_data; |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 316 | dprintf(SPEW, "target_panel_clock\n"); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 317 | |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 318 | pll_data = pinfo->mipi.dsi_pll_config; |
| 319 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 320 | if (enable) { |
| 321 | mdp_gdsc_ctrl(enable); |
Aravind Venkateswaran | 24406c0 | 2013-09-19 15:13:43 -0700 | [diff] [blame] | 322 | mmss_bus_clocks_enable(); |
| 323 | mdp_clock_enable(); |
Aravind Venkateswaran | 2713dc9 | 2013-09-19 15:23:34 -0700 | [diff] [blame] | 324 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 325 | if (ret) { |
| 326 | dprintf(CRITICAL, |
| 327 | "%s: Failed to restore MDP security configs", |
| 328 | __func__); |
| 329 | mdp_clock_disable(); |
| 330 | mmss_bus_clocks_disable(); |
| 331 | mdp_gdsc_ctrl(0); |
| 332 | return ret; |
| 333 | } |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 334 | mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data); |
| 335 | dsi_pll_enable_seq(MIPI_DSI0_BASE); |
Aravind Venkateswaran | 24406c0 | 2013-09-19 15:13:43 -0700 | [diff] [blame] | 336 | mmss_dsi_clocks_enable(pll_data->pclk_m, |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 337 | pll_data->pclk_n, |
| 338 | pll_data->pclk_d); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 339 | } else if(!target_cont_splash_screen()) { |
Aravind Venkateswaran | 24406c0 | 2013-09-19 15:13:43 -0700 | [diff] [blame] | 340 | mmss_dsi_clocks_disable(); |
| 341 | mdp_clock_disable(); |
| 342 | mmss_bus_clocks_disable(); |
| 343 | mdp_gdsc_ctrl(enable); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 349 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 350 | struct msm_panel_info *pinfo) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 351 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 352 | int ret = NO_ERROR; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 353 | if (enable) { |
Aravind Venkateswaran | d039850 | 2013-11-04 16:46:46 -0800 | [diff] [blame] | 354 | if (pinfo->mipi.use_enable_gpio) { |
| 355 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 356 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 357 | enable_gpio.pin_strength, |
| 358 | enable_gpio.pin_state); |
| 359 | |
| 360 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 361 | } |
| 362 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 363 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 364 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 365 | reset_gpio.pin_strength, reset_gpio.pin_state); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 366 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 367 | gpio_set_dir(reset_gpio.pin_id, 2); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 368 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 369 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[0]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 370 | mdelay(resetseq->sleep[0]); |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 371 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[1]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 372 | mdelay(resetseq->sleep[1]); |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 373 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[2]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 374 | mdelay(resetseq->sleep[2]); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 375 | } else if(!target_cont_splash_screen()) { |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 376 | gpio_set_value(reset_gpio.pin_id, 0); |
Aravind Venkateswaran | d039850 | 2013-11-04 16:46:46 -0800 | [diff] [blame] | 377 | if (pinfo->mipi.use_enable_gpio) |
| 378 | gpio_set_value(enable_gpio.pin_id, 0); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 379 | } |
| 380 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 381 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 382 | } |
| 383 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 384 | int target_ldo_ctrl(uint8_t enable) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 385 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 386 | uint32_t ret = NO_ERROR; |
| 387 | uint32_t ldocounter = 0; |
| 388 | uint32_t pm8x41_ldo_base = 0x13F00; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 389 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 390 | while (ldocounter < TOTAL_LDO_DEFINED) { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 391 | struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base + |
| 392 | 0x100 * ldo_entry_array[ldocounter].ldo_id), |
| 393 | ldo_entry_array[ldocounter].ldo_type); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 394 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 395 | dprintf(SPEW, "Setting %s\n", |
| 396 | ldo_entry_array[ldocounter].ldo_id); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 397 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 398 | /* Set voltage during power on */ |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 399 | if (enable) { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 400 | pm8x41_ldo_set_voltage(&ldo_entry, |
| 401 | ldo_entry_array[ldocounter].ldo_voltage); |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 402 | |
| 403 | pm8x41_ldo_control(&ldo_entry, enable); |
| 404 | |
| 405 | } else if(!target_cont_splash_screen() && |
| 406 | ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) { |
| 407 | pm8x41_ldo_control(&ldo_entry, enable); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 408 | } |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 409 | ldocounter++; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 410 | } |
| 411 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 412 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 413 | } |
| 414 | |
Aravind Venkateswaran | 35d110b | 2014-02-25 16:45:11 -0800 | [diff] [blame] | 415 | void target_display_init(const char *panel_name) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 416 | { |
Pradeep Jilagam | cd51b52 | 2013-10-29 13:08:51 +0530 | [diff] [blame] | 417 | uint32_t panel_loop = 0; |
| 418 | uint32_t ret = 0; |
| 419 | |
| 420 | do { |
Justin Philip | d4b293a | 2014-09-17 12:26:49 +0530 | [diff] [blame] | 421 | target_force_cont_splash_disable(false); |
Aravind Venkateswaran | 927e910 | 2014-02-25 17:16:49 -0800 | [diff] [blame] | 422 | ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR); |
Pradeep Jilagam | cd51b52 | 2013-10-29 13:08:51 +0530 | [diff] [blame] | 423 | if (!ret || ret == ERR_NOT_SUPPORTED) { |
| 424 | break; |
| 425 | } else { |
| 426 | target_force_cont_splash_disable(true); |
| 427 | msm_display_off(); |
Pradeep Jilagam | cd51b52 | 2013-10-29 13:08:51 +0530 | [diff] [blame] | 428 | } |
| 429 | } while (++panel_loop <= oem_panel_max_auto_detect_panels()); |
| 430 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 431 | } |
| 432 | |
Aravind Venkateswaran | 497653f | 2014-02-25 14:42:43 -0800 | [diff] [blame] | 433 | void target_display_shutdown(void) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 434 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 435 | gcdb_display_shutdown(); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 436 | } |