Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008, Google Inc. |
| 3 | * All rights reserved. |
| 4 | * |
Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 5 | * Copyright (c) 2012, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | 3acfb74 | 2011-11-15 18:19:32 +0530 | [diff] [blame] | 6 | * |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * * Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * * Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in |
| 14 | * the documentation and/or other materials provided with the |
| 15 | * distribution. |
| 16 | * * Neither the name of Google, Inc. nor the names of its contributors |
| 17 | * may be used to endorse or promote products derived from this |
| 18 | * software without specific prior written permission. |
| 19 | * |
| 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 23 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 24 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 26 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 27 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 28 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 29 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 30 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 31 | * SUCH DAMAGE. |
| 32 | */ |
| 33 | |
| 34 | #include <debug.h> |
| 35 | #include <arch/arm.h> |
| 36 | #include <reg.h> |
| 37 | #include <kernel/thread.h> |
| 38 | #include <platform/interrupts.h> |
| 39 | |
| 40 | #include <platform/irqs.h> |
| 41 | #include <platform/iomap.h> |
| 42 | |
| 43 | #define VIC_REG(off) (MSM_VIC_BASE + (off)) |
| 44 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 45 | #define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */ |
| 46 | #define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */ |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 47 | #define VIC_INT_EN0 VIC_REG(0x0010) |
| 48 | #define VIC_INT_EN1 VIC_REG(0x0014) |
| 49 | #define VIC_INT_ENCLEAR0 VIC_REG(0x0020) |
| 50 | #define VIC_INT_ENCLEAR1 VIC_REG(0x0024) |
| 51 | #define VIC_INT_ENSET0 VIC_REG(0x0030) |
| 52 | #define VIC_INT_ENSET1 VIC_REG(0x0034) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 53 | #define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */ |
| 54 | #define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */ |
| 55 | #define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */ |
| 56 | #define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */ |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 57 | #define VIC_NO_PEND_VAL VIC_REG(0x0060) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 58 | #define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */ |
| 59 | #define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */ |
| 60 | #define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */ |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 61 | #define VIC_IRQ_STATUS0 VIC_REG(0x0080) |
| 62 | #define VIC_IRQ_STATUS1 VIC_REG(0x0084) |
| 63 | #define VIC_FIQ_STATUS0 VIC_REG(0x0090) |
| 64 | #define VIC_FIQ_STATUS1 VIC_REG(0x0094) |
| 65 | #define VIC_RAW_STATUS0 VIC_REG(0x00A0) |
| 66 | #define VIC_RAW_STATUS1 VIC_REG(0x00A4) |
| 67 | #define VIC_INT_CLEAR0 VIC_REG(0x00B0) |
| 68 | #define VIC_INT_CLEAR1 VIC_REG(0x00B4) |
| 69 | #define VIC_SOFTINT0 VIC_REG(0x00C0) |
| 70 | #define VIC_SOFTINT1 VIC_REG(0x00C4) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 71 | #define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */ |
| 72 | #define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */ |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 73 | #define VIC_IRQ_VEC_WR VIC_REG(0x00D8) |
| 74 | #define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0) |
| 75 | #define VIC_IRQ_IN_STACK VIC_REG(0x00E4) |
| 76 | #define VIC_TEST_BUS_SEL VIC_REG(0x00E8) |
| 77 | |
| 78 | struct ihandler { |
| 79 | int_handler func; |
| 80 | void *arg; |
| 81 | }; |
| 82 | |
Channagoud Kadabi | 3acfb74 | 2011-11-15 18:19:32 +0530 | [diff] [blame] | 83 | static struct ihandler handler[NR_IRQS_VIC]; |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 84 | |
| 85 | void platform_init_interrupts(void) |
| 86 | { |
| 87 | writel(0xffffffff, VIC_INT_CLEAR0); |
| 88 | writel(0xffffffff, VIC_INT_CLEAR1); |
| 89 | writel(0, VIC_INT_SELECT0); |
| 90 | writel(0, VIC_INT_SELECT1); |
| 91 | writel(0xffffffff, VIC_INT_TYPE0); |
| 92 | writel(0xffffffff, VIC_INT_TYPE1); |
| 93 | writel(0, VIC_CONFIG); |
| 94 | writel(1, VIC_INT_MASTEREN); |
| 95 | } |
| 96 | |
Channagoud Kadabi | 81ba110 | 2011-10-01 16:37:59 +0530 | [diff] [blame] | 97 | enum handler_return vic_platform_irq(struct arm_iframe *frame) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 98 | { |
| 99 | unsigned num; |
| 100 | enum handler_return ret; |
| 101 | num = readl(VIC_IRQ_VEC_RD); |
| 102 | num = readl(VIC_IRQ_VEC_PEND_RD); |
Channagoud Kadabi | 3acfb74 | 2011-11-15 18:19:32 +0530 | [diff] [blame] | 103 | if (num > NR_IRQS_VIC) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 104 | return 0; |
| 105 | writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0); |
| 106 | ret = handler[num].func(handler[num].arg); |
| 107 | writel(0, VIC_IRQ_VEC_WR); |
| 108 | return ret; |
| 109 | } |
| 110 | |
Channagoud Kadabi | 81ba110 | 2011-10-01 16:37:59 +0530 | [diff] [blame] | 111 | void vic_platform_fiq(struct arm_iframe *frame) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 112 | { |
| 113 | PANIC_UNIMPLEMENTED; |
| 114 | } |
| 115 | |
Channagoud Kadabi | 81ba110 | 2011-10-01 16:37:59 +0530 | [diff] [blame] | 116 | status_t vic_mask_interrupt(unsigned int vector) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 117 | { |
| 118 | unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0; |
| 119 | unsigned bit = 1 << (vector & 31); |
| 120 | writel(bit, reg); |
| 121 | return 0; |
| 122 | } |
| 123 | |
Channagoud Kadabi | 81ba110 | 2011-10-01 16:37:59 +0530 | [diff] [blame] | 124 | status_t vic_unmask_interrupt(unsigned int vector) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 125 | { |
| 126 | unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0; |
| 127 | unsigned bit = 1 << (vector & 31); |
| 128 | writel(bit, reg); |
| 129 | return 0; |
| 130 | } |
| 131 | |
Channagoud Kadabi | 81ba110 | 2011-10-01 16:37:59 +0530 | [diff] [blame] | 132 | void vic_register_int_handler(unsigned int vector, int_handler func, void *arg) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 133 | { |
Channagoud Kadabi | 3acfb74 | 2011-11-15 18:19:32 +0530 | [diff] [blame] | 134 | if (vector >= NR_IRQS_VIC) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 135 | return; |
| 136 | |
| 137 | enter_critical_section(); |
| 138 | handler[vector].func = func; |
| 139 | handler[vector].arg = arg; |
| 140 | exit_critical_section(); |
| 141 | } |