Dinh Nguyen | 475dc86 | 2014-09-04 16:45:56 -0500 | [diff] [blame] | 1 | /* |
Dinh Nguyen | 88c8e4c | 2015-03-09 22:57:04 -0500 | [diff] [blame] | 2 | * Copyright (C) 2015 Altera Corporation <www.altera.com> |
Dinh Nguyen | 475dc86 | 2014-09-04 16:45:56 -0500 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
Dinh Nguyen | 475dc86 | 2014-09-04 16:45:56 -0500 | [diff] [blame] | 17 | #include "socfpga_arria10.dtsi" |
| 18 | |
| 19 | / { |
| 20 | model = "Altera SOCFPGA Arria 10"; |
| 21 | compatible = "altr,socfpga-arria10", "altr,socfpga"; |
| 22 | |
Dinh Nguyen | efb6672 | 2016-05-03 08:59:01 -0500 | [diff] [blame] | 23 | aliases { |
| 24 | ethernet0 = &gmac0; |
Matthew Gerlach | b65c0ef | 2016-05-12 10:24:42 -0700 | [diff] [blame] | 25 | serial0 = &uart1; |
Dinh Nguyen | efb6672 | 2016-05-03 08:59:01 -0500 | [diff] [blame] | 26 | }; |
| 27 | |
Dinh Nguyen | 475dc86 | 2014-09-04 16:45:56 -0500 | [diff] [blame] | 28 | chosen { |
Dinh Nguyen | efc1985 | 2015-07-14 17:19:02 -0500 | [diff] [blame] | 29 | bootargs = "earlyprintk"; |
Matthew Gerlach | b65c0ef | 2016-05-12 10:24:42 -0700 | [diff] [blame] | 30 | stdout-path = "serial0:115200n8"; |
Dinh Nguyen | 475dc86 | 2014-09-04 16:45:56 -0500 | [diff] [blame] | 31 | }; |
| 32 | |
| 33 | memory { |
| 34 | name = "memory"; |
| 35 | device_type = "memory"; |
| 36 | reg = <0x0 0x40000000>; /* 1GB */ |
| 37 | }; |
| 38 | |
| 39 | soc { |
| 40 | clkmgr@ffd04000 { |
| 41 | clocks { |
| 42 | osc1 { |
| 43 | clock-frequency = <25000000>; |
| 44 | }; |
| 45 | }; |
| 46 | }; |
Dinh Nguyen | 475dc86 | 2014-09-04 16:45:56 -0500 | [diff] [blame] | 47 | }; |
| 48 | }; |
Dinh Nguyen | 74568da | 2015-04-02 13:26:35 -0500 | [diff] [blame] | 49 | |
Dinh Nguyen | 112cadf | 2015-06-02 21:31:00 -0500 | [diff] [blame] | 50 | &gmac0 { |
| 51 | phy-mode = "rgmii"; |
| 52 | phy-addr = <0xffffffff>; /* probe for phy addr */ |
| 53 | |
| 54 | /* |
| 55 | * These skews assume the user's FPGA design is adding 600ps of delay |
| 56 | * for TX_CLK on Arria 10. |
| 57 | * |
| 58 | * All skews are offset since hardware skew values for the ksz9031 |
| 59 | * range from a negative skew to a positive skew. |
| 60 | * See the micrel-ksz90x1.txt Documentation file for details. |
| 61 | */ |
| 62 | txd0-skew-ps = <0>; /* -420ps */ |
| 63 | txd1-skew-ps = <0>; /* -420ps */ |
| 64 | txd2-skew-ps = <0>; /* -420ps */ |
| 65 | txd3-skew-ps = <0>; /* -420ps */ |
| 66 | rxd0-skew-ps = <420>; /* 0ps */ |
| 67 | rxd1-skew-ps = <420>; /* 0ps */ |
| 68 | rxd2-skew-ps = <420>; /* 0ps */ |
| 69 | rxd3-skew-ps = <420>; /* 0ps */ |
| 70 | txen-skew-ps = <0>; /* -420ps */ |
| 71 | txc-skew-ps = <1860>; /* 960ps */ |
| 72 | rxdv-skew-ps = <420>; /* 0ps */ |
| 73 | rxc-skew-ps = <1680>; /* 780ps */ |
| 74 | max-frame-size = <3800>; |
| 75 | status = "okay"; |
| 76 | }; |
| 77 | |
Thor Thayer | 07e75f4 | 2016-06-02 17:52:27 +0000 | [diff] [blame^] | 78 | &gpio1 { |
| 79 | status = "okay"; |
| 80 | }; |
| 81 | |
Thor Thayer | 5984be0 | 2016-06-02 17:52:26 +0000 | [diff] [blame] | 82 | &spi1 { |
| 83 | status = "okay"; |
| 84 | |
| 85 | resource-manager@0 { |
| 86 | compatible = "altr,a10sr"; |
| 87 | reg = <0>; |
| 88 | spi-max-frequency = <100000>; |
| 89 | /* low-level active IRQ at GPIO1_5 */ |
| 90 | interrupt-parent = <&portb>; |
| 91 | interrupts = <5 IRQ_TYPE_LEVEL_LOW>; |
| 92 | interrupt-controller; |
| 93 | #interrupt-cells = <2>; |
| 94 | |
| 95 | a10sr_gpio: gpio-controller { |
| 96 | compatible = "altr,a10sr-gpio"; |
| 97 | gpio-controller; |
| 98 | #gpio-cells = <2>; |
| 99 | }; |
| 100 | }; |
| 101 | }; |
| 102 | |
Dinh Nguyen | 19c2138 | 2015-09-22 14:50:37 -0500 | [diff] [blame] | 103 | &i2c1 { |
| 104 | speed-mode = <0>; |
| 105 | status = "okay"; |
| 106 | |
| 107 | /* |
| 108 | * adjust the falling times to decrease the i2c frequency to 50Khz |
| 109 | * because the LCD module does not work at the standard 100Khz |
| 110 | */ |
| 111 | i2c-sda-falling-time-ns = <6000>; |
| 112 | i2c-scl-falling-time-ns = <6000>; |
| 113 | |
| 114 | eeprom@51 { |
| 115 | compatible = "atmel,24c32"; |
| 116 | reg = <0x51>; |
| 117 | pagesize = <32>; |
| 118 | }; |
| 119 | |
| 120 | rtc@68 { |
| 121 | compatible = "dallas,ds1339"; |
| 122 | reg = <0x68>; |
| 123 | }; |
| 124 | }; |
| 125 | |
Dinh Nguyen | 74568da | 2015-04-02 13:26:35 -0500 | [diff] [blame] | 126 | &uart1 { |
| 127 | status = "okay"; |
| 128 | }; |
Dinh Nguyen | 19c2138 | 2015-09-22 14:50:37 -0500 | [diff] [blame] | 129 | |
| 130 | &usb0 { |
| 131 | status = "okay"; |
| 132 | }; |