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gerrit-public.fairphone.software / kernel / msm-4.19 / 07ed1eed529395e239d1e90806043f1dafc211fc / . / arch / arm / boot / dts / atlas6.dtsi
blob: f8674bcc4489f0ce09d5409711baddfbb7efae76 [file] [log] [blame]
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]1/*
2 * DTS file for CSR SiRFatlas6 SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,atlas6";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 reg = <0x0>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
26 /* from bootloader */
27 timebase-frequency = <0>;
28 bus-frequency = <0>;
29 clock-frequency = <0>;
Rongjun Ying683659f2014-01-09 12:14:37 +0800[diff] [blame]30 clocks = <&clks 12>;
31 operating-points = <
32 /* kHz uV */
33 200000 1025000
34 400000 1025000
35 600000 1050000
36 800000 1100000
37 >;
38 clock-latency = <150000>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]39 };
40 };
41
42 axi {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges = <0x40000000 0x40000000 0x80000000>;
47
48 intc: interrupt-controller@80020000 {
49 #interrupt-cells = <1>;
50 interrupt-controller;
51 compatible = "sirf,prima2-intc";
52 reg = <0x80020000 0x1000>;
53 };
54
55 sys-iobg {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges = <0x88000000 0x88000000 0x40000>;
60
61 clks: clock-controller@88000000 {
62 compatible = "sirf,atlas6-clkc";
63 reg = <0x88000000 0x1000>;
64 interrupts = <3>;
65 #clock-cells = <1>;
66 };
67
68 reset-controller@88010000 {
69 compatible = "sirf,prima2-rstc";
70 reg = <0x88010000 0x1000>;
71 };
72
73 rsc-controller@88020000 {
74 compatible = "sirf,prima2-rsc";
75 reg = <0x88020000 0x1000>;
76 };
Barry Song06718402013-09-22 18:21:03 +0800[diff] [blame]77
78 cphifbg@88030000 {
79 compatible = "sirf,prima2-cphifbg";
80 reg = <0x88030000 0x1000>;
Barry Song794f8b22014-01-09 12:02:53 +0800[diff] [blame]81 clocks = <&clks 42>;
Barry Song06718402013-09-22 18:21:03 +0800[diff] [blame]82 };
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]83 };
84
85 mem-iobg {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <0x90000000 0x90000000 0x10000>;
90
91 memory-controller@90000000 {
92 compatible = "sirf,prima2-memc";
Ye He5fadea22013-09-22 17:00:51 +0800[diff] [blame]93 reg = <0x90000000 0x2000>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]94 interrupts = <27>;
95 clocks = <&clks 5>;
96 };
Ye He5fadea22013-09-22 17:00:51 +0800[diff] [blame]97
98 memc-monitor {
99 compatible = "sirf,prima2-memcmon";
100 reg = <0x90002000 0x200>;
101 interrupts = <4>;
102 clocks = <&clks 32>;
103 };
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]104 };
105
106 disp-iobg {
107 compatible = "simple-bus";
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0x90010000 0x90010000 0x30000>;
111
112 lcd@90010000 {
113 compatible = "sirf,prima2-lcd";
114 reg = <0x90010000 0x20000>;
115 interrupts = <30>;
116 clocks = <&clks 34>;
117 display=<&display>;
118 /* later transfer to pwm */
119 bl-gpio = <&gpio 7 0>;
120 default-panel = <&panel0>;
121 };
122
123 vpp@90020000 {
124 compatible = "sirf,prima2-vpp";
125 reg = <0x90020000 0x10000>;
126 interrupts = <31>;
127 clocks = <&clks 35>;
128 };
129 };
130
131 graphics-iobg {
132 compatible = "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 ranges = <0x98000000 0x98000000 0x8000000>;
136
137 graphics@98000000 {
138 compatible = "powervr,sgx510";
139 reg = <0x98000000 0x8000000>;
140 interrupts = <6>;
141 clocks = <&clks 32>;
142 };
143 };
144
Jiansong Chen304ec422013-09-05 18:33:17 +0800[diff] [blame]145 graphics2d-iobg {
146 compatible = "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 ranges = <0xa0000000 0xa0000000 0x8000000>;
150
151 ble@a0000000 {
152 compatible = "sirf,atlas6-ble";
153 reg = <0xa0000000 0x2000>;
154 interrupts = <5>;
155 clocks = <&clks 33>;
156 };
157 };
158
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]159 dsp-iobg {
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges = <0xa8000000 0xa8000000 0x2000000>;
164
165 dspif@a8000000 {
166 compatible = "sirf,prima2-dspif";
167 reg = <0xa8000000 0x10000>;
168 interrupts = <9>;
169 };
170
171 gps@a8010000 {
172 compatible = "sirf,prima2-gps";
173 reg = <0xa8010000 0x10000>;
174 interrupts = <7>;
175 clocks = <&clks 9>;
176 };
177
178 dsp@a9000000 {
179 compatible = "sirf,prima2-dsp";
180 reg = <0xa9000000 0x1000000>;
181 interrupts = <8>;
182 clocks = <&clks 8>;
183 };
184 };
185
186 peri-iobg {
187 compatible = "simple-bus";
188 #address-cells = <1>;
189 #size-cells = <1>;
190 ranges = <0xb0000000 0xb0000000 0x180000>,
191 <0x56000000 0x56000000 0x1b00000>;
192
193 timer@b0020000 {
194 compatible = "sirf,prima2-tick";
195 reg = <0xb0020000 0x1000>;
196 interrupts = <0>;
197 };
198
199 nand@b0030000 {
200 compatible = "sirf,prima2-nand";
201 reg = <0xb0030000 0x10000>;
202 interrupts = <41>;
203 clocks = <&clks 26>;
204 };
205
206 audio@b0040000 {
207 compatible = "sirf,prima2-audio";
208 reg = <0xb0040000 0x10000>;
209 interrupts = <35>;
210 clocks = <&clks 27>;
211 };
212
213 uart0: uart@b0050000 {
214 cell-index = <0>;
215 compatible = "sirf,prima2-uart";
216 reg = <0xb0050000 0x1000>;
217 interrupts = <17>;
218 fifosize = <128>;
219 clocks = <&clks 13>;
Qipan Lia1369972013-09-23 23:15:08 +0800[diff] [blame]220 sirf,uart-dma-rx-channel = <21>;
221 sirf,uart-dma-tx-channel = <2>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]222 };
223
224 uart1: uart@b0060000 {
225 cell-index = <1>;
226 compatible = "sirf,prima2-uart";
227 reg = <0xb0060000 0x1000>;
228 interrupts = <18>;
229 fifosize = <32>;
230 clocks = <&clks 14>;
231 };
232
233 uart2: uart@b0070000 {
234 cell-index = <2>;
235 compatible = "sirf,prima2-uart";
236 reg = <0xb0070000 0x1000>;
237 interrupts = <19>;
238 fifosize = <128>;
239 clocks = <&clks 15>;
Qipan Lia1369972013-09-23 23:15:08 +0800[diff] [blame]240 sirf,uart-dma-rx-channel = <6>;
241 sirf,uart-dma-tx-channel = <7>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]242 };
243
244 usp0: usp@b0080000 {
245 cell-index = <0>;
246 compatible = "sirf,prima2-usp";
247 reg = <0xb0080000 0x10000>;
248 interrupts = <20>;
Qipan Lia1369972013-09-23 23:15:08 +0800[diff] [blame]249 fifosize = <128>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]250 clocks = <&clks 28>;
Qipan Lia1369972013-09-23 23:15:08 +0800[diff] [blame]251 sirf,usp-dma-rx-channel = <17>;
252 sirf,usp-dma-tx-channel = <18>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]253 };
254
255 usp1: usp@b0090000 {
256 cell-index = <1>;
257 compatible = "sirf,prima2-usp";
258 reg = <0xb0090000 0x10000>;
259 interrupts = <21>;
Qipan Lia1369972013-09-23 23:15:08 +0800[diff] [blame]260 fifosize = <128>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]261 clocks = <&clks 29>;
Qipan Lia1369972013-09-23 23:15:08 +0800[diff] [blame]262 sirf,usp-dma-rx-channel = <14>;
263 sirf,usp-dma-tx-channel = <15>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]264 };
265
266 dmac0: dma-controller@b00b0000 {
267 cell-index = <0>;
268 compatible = "sirf,prima2-dmac";
269 reg = <0xb00b0000 0x10000>;
270 interrupts = <12>;
271 clocks = <&clks 24>;
272 };
273
274 dmac1: dma-controller@b0160000 {
275 cell-index = <1>;
276 compatible = "sirf,prima2-dmac";
277 reg = <0xb0160000 0x10000>;
278 interrupts = <13>;
279 clocks = <&clks 25>;
280 };
281
282 vip@b00C0000 {
283 compatible = "sirf,prima2-vip";
284 reg = <0xb00C0000 0x10000>;
285 clocks = <&clks 31>;
Renwei Wu262bcc12013-09-23 23:57:11 +0800[diff] [blame]286 interrupts = <14>;
287 sirf,vip-dma-rx-channel = <16>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]288 };
289
290 spi0: spi@b00d0000 {
291 cell-index = <0>;
292 compatible = "sirf,prima2-spi";
293 reg = <0xb00d0000 0x10000>;
294 interrupts = <15>;
295 sirf,spi-num-chipselects = <1>;
296 cs-gpios = <&gpio 0 0>;
297 sirf,spi-dma-rx-channel = <25>;
298 sirf,spi-dma-tx-channel = <20>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 clocks = <&clks 19>;
302 status = "disabled";
303 };
304
305 spi1: spi@b0170000 {
306 cell-index = <1>;
307 compatible = "sirf,prima2-spi";
308 reg = <0xb0170000 0x10000>;
309 interrupts = <16>;
Barry Song6f425112013-09-23 23:29:56 +0800[diff] [blame]310 sirf,spi-num-chipselects = <1>;
311 sirf,spi-dma-rx-channel = <12>;
312 sirf,spi-dma-tx-channel = <13>;
313 #address-cells = <1>;
314 #size-cells = <0>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]315 clocks = <&clks 20>;
316 status = "disabled";
317 };
318
319 i2c0: i2c@b00e0000 {
320 cell-index = <0>;
321 compatible = "sirf,prima2-i2c";
322 reg = <0xb00e0000 0x10000>;
323 interrupts = <24>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 clocks = <&clks 17>;
327 };
328
329 i2c1: i2c@b00f0000 {
330 cell-index = <1>;
331 compatible = "sirf,prima2-i2c";
332 reg = <0xb00f0000 0x10000>;
333 interrupts = <25>;
334 #address-cells = <1>;
335 #size-cells = <0>;
336 clocks = <&clks 18>;
337 };
338
339 tsc@b0110000 {
340 compatible = "sirf,prima2-tsc";
341 reg = <0xb0110000 0x10000>;
342 interrupts = <33>;
343 clocks = <&clks 16>;
344 };
345
346 gpio: pinctrl@b0120000 {
347 #gpio-cells = <2>;
348 #interrupt-cells = <2>;
349 compatible = "sirf,atlas6-pinctrl";
350 reg = <0xb0120000 0x10000>;
351 interrupts = <43 44 45 46 47>;
352 gpio-controller;
353 interrupt-controller;
354
355 lcd_16pins_a: lcd0@0 {
356 lcd {
357 sirf,pins = "lcd_16bitsgrp";
358 sirf,function = "lcd_16bits";
359 };
360 };
361 lcd_18pins_a: lcd0@1 {
362 lcd {
363 sirf,pins = "lcd_18bitsgrp";
364 sirf,function = "lcd_18bits";
365 };
366 };
367 lcd_24pins_a: lcd0@2 {
368 lcd {
369 sirf,pins = "lcd_24bitsgrp";
370 sirf,function = "lcd_24bits";
371 };
372 };
373 lcdrom_pins_a: lcdrom0@0 {
374 lcd {
375 sirf,pins = "lcdromgrp";
376 sirf,function = "lcdrom";
377 };
378 };
379 uart0_pins_a: uart0@0 {
380 uart {
381 sirf,pins = "uart0grp";
382 sirf,function = "uart0";
383 };
384 };
Qipan Li031b8ce2013-08-19 16:15:49 +0800[diff] [blame]385 uart0_noflow_pins_a: uart0@1 {
386 uart {
387 sirf,pins = "uart0_nostreamctrlgrp";
388 sirf,function = "uart0_nostreamctrl";
389 };
390 };
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]391 uart1_pins_a: uart1@0 {
392 uart {
393 sirf,pins = "uart1grp";
394 sirf,function = "uart1";
395 };
396 };
397 uart2_pins_a: uart2@0 {
398 uart {
399 sirf,pins = "uart2grp";
400 sirf,function = "uart2";
401 };
402 };
403 uart2_noflow_pins_a: uart2@1 {
404 uart {
405 sirf,pins = "uart2_nostreamctrlgrp";
406 sirf,function = "uart2_nostreamctrl";
407 };
408 };
409 spi0_pins_a: spi0@0 {
410 spi {
411 sirf,pins = "spi0grp";
412 sirf,function = "spi0";
413 };
414 };
415 spi1_pins_a: spi1@0 {
416 spi {
417 sirf,pins = "spi1grp";
418 sirf,function = "spi1";
419 };
420 };
421 i2c0_pins_a: i2c0@0 {
422 i2c {
423 sirf,pins = "i2c0grp";
424 sirf,function = "i2c0";
425 };
426 };
427 i2c1_pins_a: i2c1@0 {
428 i2c {
429 sirf,pins = "i2c1grp";
430 sirf,function = "i2c1";
431 };
432 };
433 pwm0_pins_a: pwm0@0 {
434 pwm {
435 sirf,pins = "pwm0grp";
436 sirf,function = "pwm0";
437 };
438 };
439 pwm1_pins_a: pwm1@0 {
440 pwm {
441 sirf,pins = "pwm1grp";
442 sirf,function = "pwm1";
443 };
444 };
445 pwm2_pins_a: pwm2@0 {
446 pwm {
447 sirf,pins = "pwm2grp";
448 sirf,function = "pwm2";
449 };
450 };
451 pwm3_pins_a: pwm3@0 {
452 pwm {
453 sirf,pins = "pwm3grp";
454 sirf,function = "pwm3";
455 };
456 };
457 pwm4_pins_a: pwm4@0 {
458 pwm {
459 sirf,pins = "pwm4grp";
460 sirf,function = "pwm4";
461 };
462 };
463 gps_pins_a: gps@0 {
464 gps {
465 sirf,pins = "gpsgrp";
466 sirf,function = "gps";
467 };
468 };
469 vip_pins_a: vip@0 {
470 vip {
471 sirf,pins = "vipgrp";
472 sirf,function = "vip";
473 };
474 };
475 sdmmc0_pins_a: sdmmc0@0 {
476 sdmmc0 {
477 sirf,pins = "sdmmc0grp";
478 sirf,function = "sdmmc0";
479 };
480 };
481 sdmmc1_pins_a: sdmmc1@0 {
482 sdmmc1 {
483 sirf,pins = "sdmmc1grp";
484 sirf,function = "sdmmc1";
485 };
486 };
487 sdmmc2_pins_a: sdmmc2@0 {
488 sdmmc2 {
489 sirf,pins = "sdmmc2grp";
490 sirf,function = "sdmmc2";
491 };
492 };
493 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
494 sdmmc2_nowp {
495 sirf,pins = "sdmmc2_nowpgrp";
496 sirf,function = "sdmmc2_nowp";
497 };
498 };
499 sdmmc3_pins_a: sdmmc3@0 {
500 sdmmc3 {
501 sirf,pins = "sdmmc3grp";
502 sirf,function = "sdmmc3";
503 };
504 };
505 sdmmc5_pins_a: sdmmc5@0 {
506 sdmmc5 {
507 sirf,pins = "sdmmc5grp";
508 sirf,function = "sdmmc5";
509 };
510 };
511 i2s_pins_a: i2s@0 {
512 i2s {
513 sirf,pins = "i2sgrp";
514 sirf,function = "i2s";
515 };
516 };
517 i2s_no_din_pins_a: i2s_no_din@0 {
518 i2s_no_din {
519 sirf,pins = "i2s_no_dingrp";
520 sirf,function = "i2s_no_din";
521 };
522 };
523 i2s_6chn_pins_a: i2s_6chn@0 {
524 i2s_6chn {
525 sirf,pins = "i2s_6chngrp";
526 sirf,function = "i2s_6chn";
527 };
528 };
529 ac97_pins_a: ac97@0 {
530 ac97 {
531 sirf,pins = "ac97grp";
532 sirf,function = "ac97";
533 };
534 };
535 nand_pins_a: nand@0 {
536 nand {
537 sirf,pins = "nandgrp";
538 sirf,function = "nand";
539 };
540 };
541 usp0_pins_a: usp0@0 {
542 usp0 {
543 sirf,pins = "usp0grp";
544 sirf,function = "usp0";
545 };
546 };
Qipan Lid58e9a02013-07-04 15:55:26 +0800[diff] [blame]547 usp0_uart_nostreamctrl_pins_a: usp0@1 {
548 usp0 {
549 sirf,pins = "usp0_uart_nostreamctrl_grp";
550 sirf,function = "usp0_uart_nostreamctrl";
551 };
552 };
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]553 usp1_pins_a: usp1@0 {
554 usp1 {
555 sirf,pins = "usp1grp";
556 sirf,function = "usp1";
557 };
558 };
Qipan Liec2b50c2014-01-03 10:59:23 +0800[diff] [blame]559 usp1_uart_nostreamctrl_pins_a: usp1@1 {
560 usp1 {
561 sirf,pins = "usp1_uart_nostreamctrl_grp";
562 sirf,function = "usp1_uart_nostreamctrl";
563 };
564 };
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]565 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
566 usb0_upli_drvbus {
567 sirf,pins = "usb0_upli_drvbusgrp";
568 sirf,function = "usb0_upli_drvbus";
569 };
570 };
571 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
572 usb1_utmi_drvbus {
573 sirf,pins = "usb1_utmi_drvbusgrp";
574 sirf,function = "usb1_utmi_drvbus";
575 };
576 };
Rong Wang6a08a922013-09-29 22:27:59 +0800[diff] [blame]577 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
578 usb1_dp_dn {
579 sirf,pins = "usb1_dp_dngrp";
580 sirf,function = "usb1_dp_dn";
581 };
582 };
583 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
584 uart1_route_io_usb1 {
585 sirf,pins = "uart1_route_io_usb1grp";
586 sirf,function = "uart1_route_io_usb1";
587 };
588 };
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]589 warm_rst_pins_a: warm_rst@0 {
590 warm_rst {
591 sirf,pins = "warm_rstgrp";
592 sirf,function = "warm_rst";
593 };
594 };
595 pulse_count_pins_a: pulse_count@0 {
596 pulse_count {
597 sirf,pins = "pulse_countgrp";
598 sirf,function = "pulse_count";
599 };
600 };
Barry Songc8078de2013-07-04 15:55:27 +0800[diff] [blame]601 cko0_pins_a: cko0@0 {
602 cko0 {
603 sirf,pins = "cko0grp";
604 sirf,function = "cko0";
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]605 };
606 };
Barry Songc8078de2013-07-04 15:55:27 +0800[diff] [blame]607 cko1_pins_a: cko1@0 {
608 cko1 {
609 sirf,pins = "cko1grp";
610 sirf,function = "cko1";
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]611 };
612 };
613 };
614
615 pwm@b0130000 {
616 compatible = "sirf,prima2-pwm";
617 reg = <0xb0130000 0x10000>;
618 clocks = <&clks 21>;
619 };
620
621 efusesys@b0140000 {
622 compatible = "sirf,prima2-efuse";
623 reg = <0xb0140000 0x10000>;
624 clocks = <&clks 22>;
625 };
626
627 pulsec@b0150000 {
628 compatible = "sirf,prima2-pulsec";
629 reg = <0xb0150000 0x10000>;
630 interrupts = <48>;
631 clocks = <&clks 23>;
632 };
633
634 pci-iobg {
635 compatible = "sirf,prima2-pciiobg", "simple-bus";
636 #address-cells = <1>;
637 #size-cells = <1>;
638 ranges = <0x56000000 0x56000000 0x1b00000>;
639
640 sd0: sdhci@56000000 {
641 cell-index = <0>;
642 compatible = "sirf,prima2-sdhc";
643 reg = <0x56000000 0x100000>;
644 interrupts = <38>;
645 bus-width = <8>;
646 clocks = <&clks 36>;
647 };
648
649 sd1: sdhci@56100000 {
650 cell-index = <1>;
651 compatible = "sirf,prima2-sdhc";
652 reg = <0x56100000 0x100000>;
653 interrupts = <38>;
654 status = "disabled";
Bin Shi7f97c302014-01-09 12:08:46 +0800[diff] [blame]655 bus-width = <4>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]656 clocks = <&clks 36>;
657 };
658
659 sd2: sdhci@56200000 {
660 cell-index = <2>;
661 compatible = "sirf,prima2-sdhc";
662 reg = <0x56200000 0x100000>;
663 interrupts = <23>;
664 status = "disabled";
Bin Shi7f97c302014-01-09 12:08:46 +0800[diff] [blame]665 bus-width = <4>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]666 clocks = <&clks 37>;
667 };
668
669 sd3: sdhci@56300000 {
670 cell-index = <3>;
671 compatible = "sirf,prima2-sdhc";
672 reg = <0x56300000 0x100000>;
673 interrupts = <23>;
674 status = "disabled";
Bin Shi7f97c302014-01-09 12:08:46 +0800[diff] [blame]675 bus-width = <4>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]676 clocks = <&clks 37>;
677 };
678
679 sd5: sdhci@56500000 {
680 cell-index = <5>;
681 compatible = "sirf,prima2-sdhc";
682 reg = <0x56500000 0x100000>;
683 interrupts = <39>;
684 status = "disabled";
Bin Shi7f97c302014-01-09 12:08:46 +0800[diff] [blame]685 bus-width = <4>;
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]686 clocks = <&clks 38>;
687 };
688
689 pci-copy@57900000 {
690 compatible = "sirf,prima2-pcicp";
691 reg = <0x57900000 0x100000>;
692 interrupts = <40>;
693 };
694
695 rom-interface@57a00000 {
696 compatible = "sirf,prima2-romif";
697 reg = <0x57a00000 0x100000>;
698 };
699 };
700 };
701
702 rtc-iobg {
Xianglong Due88b8152013-07-03 15:08:04 -0700[diff] [blame]703 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]704 #address-cells = <1>;
705 #size-cells = <1>;
706 reg = <0x80030000 0x10000>;
707
708 gpsrtc@1000 {
709 compatible = "sirf,prima2-gpsrtc";
710 reg = <0x1000 0x1000>;
711 interrupts = <55 56 57>;
712 };
713
714 sysrtc@2000 {
715 compatible = "sirf,prima2-sysrtc";
716 reg = <0x2000 0x1000>;
717 interrupts = <52 53 54>;
718 };
719
Xianglong Du423ef792014-01-09 12:23:09 +0800[diff] [blame]720 minigpsrtc@2000 {
721 compatible = "sirf,prima2-minigpsrtc";
722 reg = <0x2000 0x1000>;
723 interrupts = <54>;
724 };
725
Barry Song5fa2f9a2013-03-18 15:04:39 +0800[diff] [blame]726 pwrc@3000 {
727 compatible = "sirf,prima2-pwrc";
728 reg = <0x3000 0x1000>;
729 interrupts = <32>;
730 };
731 };
732
733 uus-iobg {
734 compatible = "simple-bus";
735 #address-cells = <1>;
736 #size-cells = <1>;
737 ranges = <0xb8000000 0xb8000000 0x40000>;
738
739 usb0: usb@b00e0000 {
740 compatible = "chipidea,ci13611a-prima2";
741 reg = <0xb8000000 0x10000>;
742 interrupts = <10>;
743 clocks = <&clks 40>;
744 };
745
746 usb1: usb@b00f0000 {
747 compatible = "chipidea,ci13611a-prima2";
748 reg = <0xb8010000 0x10000>;
749 interrupts = <11>;
750 clocks = <&clks 41>;
751 };
752
753 security@b00f0000 {
754 compatible = "sirf,prima2-security";
755 reg = <0xb8030000 0x10000>;
756 interrupts = <42>;
757 clocks = <&clks 7>;
758 };
759 };
760 };
761};