Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Low-Level PCI Access for i386 machines. |
| 3 | * |
| 4 | * (c) 1999 Martin Mares <mj@ucw.cz> |
| 5 | */ |
| 6 | |
| 7 | #undef DEBUG |
| 8 | |
| 9 | #ifdef DEBUG |
| 10 | #define DBG(x...) printk(x) |
| 11 | #else |
| 12 | #define DBG(x...) |
| 13 | #endif |
| 14 | |
| 15 | #define PCI_PROBE_BIOS 0x0001 |
| 16 | #define PCI_PROBE_CONF1 0x0002 |
| 17 | #define PCI_PROBE_CONF2 0x0004 |
| 18 | #define PCI_PROBE_MMCONF 0x0008 |
Linus Torvalds | 79e453d | 2006-09-19 08:15:22 -0700 | [diff] [blame] | 19 | #define PCI_PROBE_MASK 0x000f |
Andi Kleen | 0637a70 | 2006-09-26 10:52:41 +0200 | [diff] [blame] | 20 | #define PCI_PROBE_NOEARLY 0x0010 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #define PCI_NO_CHECKS 0x0400 |
| 23 | #define PCI_USE_PIRQ_MASK 0x0800 |
| 24 | #define PCI_ASSIGN_ROMS 0x1000 |
| 25 | #define PCI_BIOS_IRQ_SCAN 0x2000 |
| 26 | #define PCI_ASSIGN_ALL_BUSSES 0x4000 |
Gary Hade | 036fff4 | 2007-10-03 15:56:14 -0700 | [diff] [blame] | 27 | #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 |
Linus Torvalds | 236e946 | 2009-06-24 16:23:03 -0700 | [diff] [blame] | 28 | #define PCI_USE__CRS 0x10000 |
Yinghai Lu | 5f0b297 | 2008-04-14 16:08:25 -0700 | [diff] [blame] | 29 | #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 |
Robert Richter | 3a27dd1 | 2008-06-12 20:19:23 +0200 | [diff] [blame] | 30 | #define PCI_HAS_IO_ECS 0x40000 |
Linus Torvalds | dc7c65d | 2008-07-16 17:25:46 -0700 | [diff] [blame] | 31 | #define PCI_NOASSIGN_ROMS 0x80000 |
Bjorn Helgaas | 7bc5e3f | 2010-02-23 10:24:41 -0700 | [diff] [blame] | 32 | #define PCI_ROOT_NO_CRS 0x100000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | |
| 34 | extern unsigned int pci_probe; |
jayalk@intworks.biz | 120bb42 | 2005-03-21 20:20:42 -0800 | [diff] [blame] | 35 | extern unsigned long pirq_table_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Matt Domsch | 6b4b78f | 2006-09-29 15:23:23 -0500 | [diff] [blame] | 37 | enum pci_bf_sort_state { |
| 38 | pci_bf_sort_default, |
| 39 | pci_force_nobf, |
| 40 | pci_force_bf, |
| 41 | pci_dmi_bf, |
| 42 | }; |
| 43 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | /* pci-i386.c */ |
| 45 | |
| 46 | extern unsigned int pcibios_max_latency; |
| 47 | |
| 48 | void pcibios_resource_survey(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
| 50 | /* pci-pc.c */ |
| 51 | |
| 52 | extern int pcibios_last_bus; |
| 53 | extern struct pci_bus *pci_root_bus; |
| 54 | extern struct pci_ops pci_root_ops; |
| 55 | |
| 56 | /* pci-irq.c */ |
| 57 | |
| 58 | struct irq_info { |
| 59 | u8 bus, devfn; /* Bus, device and function */ |
| 60 | struct { |
Jaswinder Singh Rajput | 8248771 | 2008-12-27 18:32:28 +0530 | [diff] [blame] | 61 | u8 link; /* IRQ line ID, chipset dependent, |
| 62 | 0 = not routed */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | u16 bitmap; /* Available IRQs */ |
| 64 | } __attribute__((packed)) irq[4]; |
| 65 | u8 slot; /* Slot number, 0=onboard */ |
| 66 | u8 rfu; |
| 67 | } __attribute__((packed)); |
| 68 | |
| 69 | struct irq_routing_table { |
| 70 | u32 signature; /* PIRQ_SIGNATURE should be here */ |
| 71 | u16 version; /* PIRQ_VERSION */ |
| 72 | u16 size; /* Table size in bytes */ |
| 73 | u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ |
Jaswinder Singh Rajput | 8248771 | 2008-12-27 18:32:28 +0530 | [diff] [blame] | 74 | u16 exclusive_irqs; /* IRQs devoted exclusively to |
| 75 | PCI usage */ |
| 76 | u16 rtr_vendor, rtr_device; /* Vendor and device ID of |
| 77 | interrupt router */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | u32 miniport_data; /* Crap */ |
| 79 | u8 rfu[11]; |
Jaswinder Singh Rajput | 8248771 | 2008-12-27 18:32:28 +0530 | [diff] [blame] | 80 | u8 checksum; /* Modulo 256 checksum must give 0 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | struct irq_info slots[0]; |
| 82 | } __attribute__((packed)); |
| 83 | |
| 84 | extern unsigned int pcibios_irq_mask; |
| 85 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | extern spinlock_t pci_config_lock; |
| 87 | |
| 88 | extern int (*pcibios_enable_irq)(struct pci_dev *dev); |
David Shaohua Li | 87bec66 | 2005-07-27 23:02:00 -0400 | [diff] [blame] | 89 | extern void (*pcibios_disable_irq)(struct pci_dev *dev); |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 90 | |
Matthew Wilcox | b6ce068 | 2008-02-10 09:45:28 -0500 | [diff] [blame] | 91 | struct pci_raw_ops { |
| 92 | int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, |
| 93 | int reg, int len, u32 *val); |
| 94 | int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn, |
| 95 | int reg, int len, u32 val); |
| 96 | }; |
| 97 | |
| 98 | extern struct pci_raw_ops *raw_pci_ops; |
| 99 | extern struct pci_raw_ops *raw_pci_ext_ops; |
| 100 | |
| 101 | extern struct pci_raw_ops pci_direct_conf1; |
H. Peter Anvin | 14d7ca5 | 2008-11-11 16:19:48 -0800 | [diff] [blame] | 102 | extern bool port_cf9_safe; |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 103 | |
Robert Richter | 8dd779b | 2008-07-02 22:50:29 +0200 | [diff] [blame] | 104 | /* arch_initcall level */ |
Andi Kleen | 5e544d6 | 2006-09-26 10:52:40 +0200 | [diff] [blame] | 105 | extern int pci_direct_probe(void); |
| 106 | extern void pci_direct_init(int type); |
Andi Kleen | 92c05fc | 2006-03-23 14:35:12 -0800 | [diff] [blame] | 107 | extern void pci_pcbios_init(void); |
Robert Richter | 8dd779b | 2008-07-02 22:50:29 +0200 | [diff] [blame] | 108 | extern void __init dmi_check_pciprobe(void); |
| 109 | extern void __init dmi_check_skip_isa_align(void); |
| 110 | |
| 111 | /* some common used subsys_initcalls */ |
| 112 | extern int __init pci_acpi_init(void); |
Thomas Gleixner | ab3b379 | 2009-08-29 17:47:33 +0200 | [diff] [blame] | 113 | extern void __init pcibios_irq_init(void); |
Robert Richter | 8dd779b | 2008-07-02 22:50:29 +0200 | [diff] [blame] | 114 | extern int __init pcibios_init(void); |
Thomas Gleixner | b72d0db | 2009-08-29 16:24:51 +0200 | [diff] [blame] | 115 | extern int pci_legacy_init(void); |
Thomas Gleixner | 9325a28 | 2009-08-29 17:51:26 +0200 | [diff] [blame] | 116 | extern void pcibios_fixup_irqs(void); |
Andi Kleen | 5e544d6 | 2006-09-26 10:52:40 +0200 | [diff] [blame] | 117 | |
Olivier Galibert | b786739 | 2007-02-13 13:26:20 +0100 | [diff] [blame] | 118 | /* pci-mmconfig.c */ |
| 119 | |
Bjorn Helgaas | 56ddf4d | 2009-11-13 17:34:29 -0700 | [diff] [blame] | 120 | /* "PCI MMCONFIG %04x [bus %02x-%02x]" */ |
| 121 | #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) |
| 122 | |
Bjorn Helgaas | d215a9c | 2009-11-13 17:34:13 -0700 | [diff] [blame] | 123 | struct pci_mmcfg_region { |
Bjorn Helgaas | ff097dd | 2009-11-13 17:34:49 -0700 | [diff] [blame] | 124 | struct list_head list; |
Bjorn Helgaas | 56ddf4d | 2009-11-13 17:34:29 -0700 | [diff] [blame] | 125 | struct resource res; |
Bjorn Helgaas | d215a9c | 2009-11-13 17:34:13 -0700 | [diff] [blame] | 126 | u64 address; |
Bjorn Helgaas | 3f0f550 | 2009-11-13 17:34:39 -0700 | [diff] [blame] | 127 | char __iomem *virt; |
Bjorn Helgaas | d7e6b66 | 2009-11-13 17:34:18 -0700 | [diff] [blame] | 128 | u16 segment; |
| 129 | u8 start_bus; |
| 130 | u8 end_bus; |
Bjorn Helgaas | 56ddf4d | 2009-11-13 17:34:29 -0700 | [diff] [blame] | 131 | char name[PCI_MMCFG_RESOURCE_NAME_LEN]; |
Bjorn Helgaas | d215a9c | 2009-11-13 17:34:13 -0700 | [diff] [blame] | 132 | }; |
| 133 | |
OGAWA Hirofumi | 429d512 | 2007-02-13 13:26:20 +0100 | [diff] [blame] | 134 | extern int __init pci_mmcfg_arch_init(void); |
Yinghai Lu | 0b64ad7 | 2008-02-15 01:28:41 -0800 | [diff] [blame] | 135 | extern void __init pci_mmcfg_arch_free(void); |
Bjorn Helgaas | f6e1d8c | 2009-11-13 17:35:04 -0700 | [diff] [blame] | 136 | extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); |
dean gaudet | 3320ad9 | 2007-08-10 22:30:59 +0200 | [diff] [blame] | 137 | |
Bjorn Helgaas | ff097dd | 2009-11-13 17:34:49 -0700 | [diff] [blame] | 138 | extern struct list_head pci_mmcfg_list; |
Len Brown | c4bf2f3 | 2009-06-11 23:53:55 -0400 | [diff] [blame] | 139 | |
Bjorn Helgaas | df5eb1d | 2009-11-13 17:34:08 -0700 | [diff] [blame] | 140 | #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) |
| 141 | |
dean gaudet | 3320ad9 | 2007-08-10 22:30:59 +0200 | [diff] [blame] | 142 | /* |
| 143 | * AMD Fam10h CPUs are buggy, and cannot access MMIO config space |
| 144 | * on their northbrige except through the * %eax register. As such, you MUST |
| 145 | * NOT use normal IOMEM accesses, you need to only use the magic mmio-config |
| 146 | * accessor functions. |
| 147 | * In fact just use pci_config_*, nothing else please. |
| 148 | */ |
| 149 | static inline unsigned char mmio_config_readb(void __iomem *pos) |
| 150 | { |
| 151 | u8 val; |
| 152 | asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos)); |
| 153 | return val; |
| 154 | } |
| 155 | |
| 156 | static inline unsigned short mmio_config_readw(void __iomem *pos) |
| 157 | { |
| 158 | u16 val; |
| 159 | asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos)); |
| 160 | return val; |
| 161 | } |
| 162 | |
| 163 | static inline unsigned int mmio_config_readl(void __iomem *pos) |
| 164 | { |
| 165 | u32 val; |
| 166 | asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos)); |
| 167 | return val; |
| 168 | } |
| 169 | |
| 170 | static inline void mmio_config_writeb(void __iomem *pos, u8 val) |
| 171 | { |
Jaswinder Singh Rajput | 8248771 | 2008-12-27 18:32:28 +0530 | [diff] [blame] | 172 | asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory"); |
dean gaudet | 3320ad9 | 2007-08-10 22:30:59 +0200 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | static inline void mmio_config_writew(void __iomem *pos, u16 val) |
| 176 | { |
Jaswinder Singh Rajput | 8248771 | 2008-12-27 18:32:28 +0530 | [diff] [blame] | 177 | asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory"); |
dean gaudet | 3320ad9 | 2007-08-10 22:30:59 +0200 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | static inline void mmio_config_writel(void __iomem *pos, u32 val) |
| 181 | { |
Jaswinder Singh Rajput | 8248771 | 2008-12-27 18:32:28 +0530 | [diff] [blame] | 182 | asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory"); |
dean gaudet | 3320ad9 | 2007-08-10 22:30:59 +0200 | [diff] [blame] | 183 | } |
Thomas Gleixner | b72d0db | 2009-08-29 16:24:51 +0200 | [diff] [blame] | 184 | |
| 185 | #ifdef CONFIG_PCI |
| 186 | # ifdef CONFIG_ACPI |
| 187 | # define x86_default_pci_init pci_acpi_init |
| 188 | # else |
| 189 | # define x86_default_pci_init pci_legacy_init |
| 190 | # endif |
Thomas Gleixner | ab3b379 | 2009-08-29 17:47:33 +0200 | [diff] [blame] | 191 | # define x86_default_pci_init_irq pcibios_irq_init |
Thomas Gleixner | 9325a28 | 2009-08-29 17:51:26 +0200 | [diff] [blame] | 192 | # define x86_default_pci_fixup_irqs pcibios_fixup_irqs |
Thomas Gleixner | b72d0db | 2009-08-29 16:24:51 +0200 | [diff] [blame] | 193 | #else |
| 194 | # define x86_default_pci_init NULL |
Thomas Gleixner | ab3b379 | 2009-08-29 17:47:33 +0200 | [diff] [blame] | 195 | # define x86_default_pci_init_irq NULL |
Thomas Gleixner | 9325a28 | 2009-08-29 17:51:26 +0200 | [diff] [blame] | 196 | # define x86_default_pci_fixup_irqs NULL |
Thomas Gleixner | b72d0db | 2009-08-29 16:24:51 +0200 | [diff] [blame] | 197 | #endif |