Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
| 3 | * |
| 4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
| 5 | * David Mosberger-Tang |
| 6 | * |
| 7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/pci.h> |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 14 | #include <linux/pm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/spinlock.h> |
Tim Schmielau | 4e57b68 | 2005-10-30 15:03:48 -0800 | [diff] [blame] | 17 | #include <linux/string.h> |
vignesh babu | 229f5af | 2007-08-13 18:23:14 +0530 | [diff] [blame] | 18 | #include <linux/log2.h> |
Shaohua Li | 7d715a6 | 2008-02-25 09:46:41 +0800 | [diff] [blame] | 19 | #include <linux/pci-aspm.h> |
Stephen Rothwell | c300bd2fb | 2008-07-10 02:16:44 +0200 | [diff] [blame] | 20 | #include <linux/pm_wakeup.h> |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 21 | #include <linux/interrupt.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
Greg KH | bc56b9e | 2005-04-08 14:53:31 +0900 | [diff] [blame] | 23 | #include "pci.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | |
Rafael J. Wysocki | aa8c6c9 | 2009-01-16 21:54:43 +0100 | [diff] [blame] | 25 | unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | |
Jeff Garzik | 32a2eea | 2007-10-11 16:57:27 -0400 | [diff] [blame] | 27 | #ifdef CONFIG_PCI_DOMAINS |
| 28 | int pci_domains_supported = 1; |
| 29 | #endif |
| 30 | |
Atsushi Nemoto | 4516a61 | 2007-02-05 16:36:06 -0800 | [diff] [blame] | 31 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
| 32 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) |
| 33 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ |
| 34 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; |
| 35 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; |
| 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | /** |
| 38 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children |
| 39 | * @bus: pointer to PCI bus structure to search |
| 40 | * |
| 41 | * Given a PCI bus, returns the highest PCI bus number present in the set |
| 42 | * including the given PCI bus and its list of child PCI buses. |
| 43 | */ |
Sam Ravnborg | 96bde06 | 2007-03-26 21:53:30 -0800 | [diff] [blame] | 44 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | { |
| 46 | struct list_head *tmp; |
| 47 | unsigned char max, n; |
| 48 | |
Kristen Accardi | b82db5c | 2006-01-17 16:56:56 -0800 | [diff] [blame] | 49 | max = bus->subordinate; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | list_for_each(tmp, &bus->children) { |
| 51 | n = pci_bus_max_busnr(pci_bus_b(tmp)); |
| 52 | if(n > max) |
| 53 | max = n; |
| 54 | } |
| 55 | return max; |
| 56 | } |
Kristen Accardi | b82db5c | 2006-01-17 16:56:56 -0800 | [diff] [blame] | 57 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | |
Andrew Morton | 1684f5d | 2008-12-01 14:30:30 -0800 | [diff] [blame] | 59 | #ifdef CONFIG_HAS_IOMEM |
| 60 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) |
| 61 | { |
| 62 | /* |
| 63 | * Make sure the BAR is actually a memory resource, not an IO resource |
| 64 | */ |
| 65 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { |
| 66 | WARN_ON(1); |
| 67 | return NULL; |
| 68 | } |
| 69 | return ioremap_nocache(pci_resource_start(pdev, bar), |
| 70 | pci_resource_len(pdev, bar)); |
| 71 | } |
| 72 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); |
| 73 | #endif |
| 74 | |
Kristen Accardi | b82db5c | 2006-01-17 16:56:56 -0800 | [diff] [blame] | 75 | #if 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | /** |
| 77 | * pci_max_busnr - returns maximum PCI bus number |
| 78 | * |
| 79 | * Returns the highest PCI bus number present in the system global list of |
| 80 | * PCI buses. |
| 81 | */ |
| 82 | unsigned char __devinit |
| 83 | pci_max_busnr(void) |
| 84 | { |
| 85 | struct pci_bus *bus = NULL; |
| 86 | unsigned char max, n; |
| 87 | |
| 88 | max = 0; |
| 89 | while ((bus = pci_find_next_bus(bus)) != NULL) { |
| 90 | n = pci_bus_max_busnr(bus); |
| 91 | if(n > max) |
| 92 | max = n; |
| 93 | } |
| 94 | return max; |
| 95 | } |
| 96 | |
Adrian Bunk | 54c762f | 2005-12-22 01:08:52 +0100 | [diff] [blame] | 97 | #endif /* 0 */ |
| 98 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 99 | #define PCI_FIND_CAP_TTL 48 |
| 100 | |
| 101 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, |
| 102 | u8 pos, int cap, int *ttl) |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 103 | { |
| 104 | u8 id; |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 105 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 106 | while ((*ttl)--) { |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 107 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
| 108 | if (pos < 0x40) |
| 109 | break; |
| 110 | pos &= ~3; |
| 111 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, |
| 112 | &id); |
| 113 | if (id == 0xff) |
| 114 | break; |
| 115 | if (id == cap) |
| 116 | return pos; |
| 117 | pos += PCI_CAP_LIST_NEXT; |
| 118 | } |
| 119 | return 0; |
| 120 | } |
| 121 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 122 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
| 123 | u8 pos, int cap) |
| 124 | { |
| 125 | int ttl = PCI_FIND_CAP_TTL; |
| 126 | |
| 127 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); |
| 128 | } |
| 129 | |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 130 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
| 131 | { |
| 132 | return __pci_find_next_cap(dev->bus, dev->devfn, |
| 133 | pos + PCI_CAP_LIST_NEXT, cap); |
| 134 | } |
| 135 | EXPORT_SYMBOL_GPL(pci_find_next_capability); |
| 136 | |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 137 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
| 138 | unsigned int devfn, u8 hdr_type) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | { |
| 140 | u16 status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | |
| 142 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); |
| 143 | if (!(status & PCI_STATUS_CAP_LIST)) |
| 144 | return 0; |
| 145 | |
| 146 | switch (hdr_type) { |
| 147 | case PCI_HEADER_TYPE_NORMAL: |
| 148 | case PCI_HEADER_TYPE_BRIDGE: |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 149 | return PCI_CAPABILITY_LIST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | case PCI_HEADER_TYPE_CARDBUS: |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 151 | return PCI_CB_CAPABILITY_LIST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | default: |
| 153 | return 0; |
| 154 | } |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 155 | |
| 156 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | } |
| 158 | |
| 159 | /** |
| 160 | * pci_find_capability - query for devices' capabilities |
| 161 | * @dev: PCI device to query |
| 162 | * @cap: capability code |
| 163 | * |
| 164 | * Tell if a device supports a given PCI capability. |
| 165 | * Returns the address of the requested capability structure within the |
| 166 | * device's PCI configuration space or 0 in case the device does not |
| 167 | * support it. Possible values for @cap: |
| 168 | * |
| 169 | * %PCI_CAP_ID_PM Power Management |
| 170 | * %PCI_CAP_ID_AGP Accelerated Graphics Port |
| 171 | * %PCI_CAP_ID_VPD Vital Product Data |
| 172 | * %PCI_CAP_ID_SLOTID Slot Identification |
| 173 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
| 174 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
| 175 | * %PCI_CAP_ID_PCIX PCI-X |
| 176 | * %PCI_CAP_ID_EXP PCI Express |
| 177 | */ |
| 178 | int pci_find_capability(struct pci_dev *dev, int cap) |
| 179 | { |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 180 | int pos; |
| 181 | |
| 182 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); |
| 183 | if (pos) |
| 184 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); |
| 185 | |
| 186 | return pos; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | /** |
| 190 | * pci_bus_find_capability - query for devices' capabilities |
| 191 | * @bus: the PCI bus to query |
| 192 | * @devfn: PCI device to query |
| 193 | * @cap: capability code |
| 194 | * |
| 195 | * Like pci_find_capability() but works for pci devices that do not have a |
| 196 | * pci_dev structure set up yet. |
| 197 | * |
| 198 | * Returns the address of the requested capability structure within the |
| 199 | * device's PCI configuration space or 0 in case the device does not |
| 200 | * support it. |
| 201 | */ |
| 202 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) |
| 203 | { |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 204 | int pos; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | u8 hdr_type; |
| 206 | |
| 207 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); |
| 208 | |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 209 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
| 210 | if (pos) |
| 211 | pos = __pci_find_next_cap(bus, devfn, pos, cap); |
| 212 | |
| 213 | return pos; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | /** |
| 217 | * pci_find_ext_capability - Find an extended capability |
| 218 | * @dev: PCI device to query |
| 219 | * @cap: capability code |
| 220 | * |
| 221 | * Returns the address of the requested extended capability structure |
| 222 | * within the device's PCI configuration space or 0 if the device does |
| 223 | * not support it. Possible values for @cap: |
| 224 | * |
| 225 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting |
| 226 | * %PCI_EXT_CAP_ID_VC Virtual Channel |
| 227 | * %PCI_EXT_CAP_ID_DSN Device Serial Number |
| 228 | * %PCI_EXT_CAP_ID_PWR Power Budgeting |
| 229 | */ |
| 230 | int pci_find_ext_capability(struct pci_dev *dev, int cap) |
| 231 | { |
| 232 | u32 header; |
Zhao, Yu | 557848c | 2008-10-13 19:18:07 +0800 | [diff] [blame] | 233 | int ttl; |
| 234 | int pos = PCI_CFG_SPACE_SIZE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | |
Zhao, Yu | 557848c | 2008-10-13 19:18:07 +0800 | [diff] [blame] | 236 | /* minimum 8 bytes per capability */ |
| 237 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; |
| 238 | |
| 239 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | return 0; |
| 241 | |
| 242 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
| 243 | return 0; |
| 244 | |
| 245 | /* |
| 246 | * If we have no capabilities, this is indicated by cap ID, |
| 247 | * cap version and next pointer all being 0. |
| 248 | */ |
| 249 | if (header == 0) |
| 250 | return 0; |
| 251 | |
| 252 | while (ttl-- > 0) { |
| 253 | if (PCI_EXT_CAP_ID(header) == cap) |
| 254 | return pos; |
| 255 | |
| 256 | pos = PCI_EXT_CAP_NEXT(header); |
Zhao, Yu | 557848c | 2008-10-13 19:18:07 +0800 | [diff] [blame] | 257 | if (pos < PCI_CFG_SPACE_SIZE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | break; |
| 259 | |
| 260 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
| 261 | break; |
| 262 | } |
| 263 | |
| 264 | return 0; |
| 265 | } |
Brice Goglin | 3a720d7 | 2006-05-23 06:10:01 -0400 | [diff] [blame] | 266 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 267 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 268 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
| 269 | { |
| 270 | int rc, ttl = PCI_FIND_CAP_TTL; |
| 271 | u8 cap, mask; |
| 272 | |
| 273 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) |
| 274 | mask = HT_3BIT_CAP_MASK; |
| 275 | else |
| 276 | mask = HT_5BIT_CAP_MASK; |
| 277 | |
| 278 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, |
| 279 | PCI_CAP_ID_HT, &ttl); |
| 280 | while (pos) { |
| 281 | rc = pci_read_config_byte(dev, pos + 3, &cap); |
| 282 | if (rc != PCIBIOS_SUCCESSFUL) |
| 283 | return 0; |
| 284 | |
| 285 | if ((cap & mask) == ht_cap) |
| 286 | return pos; |
| 287 | |
Brice Goglin | 47a4d5b | 2007-01-10 23:15:29 -0800 | [diff] [blame] | 288 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
| 289 | pos + PCI_CAP_LIST_NEXT, |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 290 | PCI_CAP_ID_HT, &ttl); |
| 291 | } |
| 292 | |
| 293 | return 0; |
| 294 | } |
| 295 | /** |
| 296 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities |
| 297 | * @dev: PCI device to query |
| 298 | * @pos: Position from which to continue searching |
| 299 | * @ht_cap: Hypertransport capability code |
| 300 | * |
| 301 | * To be used in conjunction with pci_find_ht_capability() to search for |
| 302 | * all capabilities matching @ht_cap. @pos should always be a value returned |
| 303 | * from pci_find_ht_capability(). |
| 304 | * |
| 305 | * NB. To be 100% safe against broken PCI devices, the caller should take |
| 306 | * steps to avoid an infinite loop. |
| 307 | */ |
| 308 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) |
| 309 | { |
| 310 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); |
| 311 | } |
| 312 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); |
| 313 | |
| 314 | /** |
| 315 | * pci_find_ht_capability - query a device's Hypertransport capabilities |
| 316 | * @dev: PCI device to query |
| 317 | * @ht_cap: Hypertransport capability code |
| 318 | * |
| 319 | * Tell if a device supports a given Hypertransport capability. |
| 320 | * Returns an address within the device's PCI configuration space |
| 321 | * or 0 in case the device does not support the request capability. |
| 322 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, |
| 323 | * which has a Hypertransport capability matching @ht_cap. |
| 324 | */ |
| 325 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) |
| 326 | { |
| 327 | int pos; |
| 328 | |
| 329 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); |
| 330 | if (pos) |
| 331 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); |
| 332 | |
| 333 | return pos; |
| 334 | } |
| 335 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); |
| 336 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | /** |
| 338 | * pci_find_parent_resource - return resource region of parent bus of given region |
| 339 | * @dev: PCI device structure contains resources to be searched |
| 340 | * @res: child resource record for which parent is sought |
| 341 | * |
| 342 | * For given resource region of given device, return the resource |
| 343 | * region of parent bus the given region is contained in or where |
| 344 | * it should be allocated from. |
| 345 | */ |
| 346 | struct resource * |
| 347 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) |
| 348 | { |
| 349 | const struct pci_bus *bus = dev->bus; |
| 350 | int i; |
| 351 | struct resource *best = NULL; |
| 352 | |
| 353 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { |
| 354 | struct resource *r = bus->resource[i]; |
| 355 | if (!r) |
| 356 | continue; |
| 357 | if (res->start && !(res->start >= r->start && res->end <= r->end)) |
| 358 | continue; /* Not contained */ |
| 359 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) |
| 360 | continue; /* Wrong type */ |
| 361 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) |
| 362 | return r; /* Exact match */ |
| 363 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) |
| 364 | best = r; /* Approximating prefetchable by non-prefetchable */ |
| 365 | } |
| 366 | return best; |
| 367 | } |
| 368 | |
| 369 | /** |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 370 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) |
| 371 | * @dev: PCI device to have its BARs restored |
| 372 | * |
| 373 | * Restore the BAR values for a given device, so as to make it |
| 374 | * accessible by its driver. |
| 375 | */ |
Adrian Bunk | ad668599 | 2007-10-27 03:06:22 +0200 | [diff] [blame] | 376 | static void |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 377 | pci_restore_bars(struct pci_dev *dev) |
| 378 | { |
Yu Zhao | bc5f5a8 | 2008-11-22 02:40:00 +0800 | [diff] [blame] | 379 | int i; |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 380 | |
Yu Zhao | bc5f5a8 | 2008-11-22 02:40:00 +0800 | [diff] [blame] | 381 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
Yu Zhao | 14add80 | 2008-11-22 02:38:52 +0800 | [diff] [blame] | 382 | pci_update_resource(dev, i); |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 383 | } |
| 384 | |
Rafael J. Wysocki | 961d912 | 2008-07-07 03:32:02 +0200 | [diff] [blame] | 385 | static struct pci_platform_pm_ops *pci_platform_pm; |
| 386 | |
| 387 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) |
| 388 | { |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 389 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
| 390 | || !ops->sleep_wake || !ops->can_wakeup) |
Rafael J. Wysocki | 961d912 | 2008-07-07 03:32:02 +0200 | [diff] [blame] | 391 | return -EINVAL; |
| 392 | pci_platform_pm = ops; |
| 393 | return 0; |
| 394 | } |
| 395 | |
| 396 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) |
| 397 | { |
| 398 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; |
| 399 | } |
| 400 | |
| 401 | static inline int platform_pci_set_power_state(struct pci_dev *dev, |
| 402 | pci_power_t t) |
| 403 | { |
| 404 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; |
| 405 | } |
| 406 | |
| 407 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
| 408 | { |
| 409 | return pci_platform_pm ? |
| 410 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; |
| 411 | } |
Randy Dunlap | 8f7020d | 2005-10-23 11:57:38 -0700 | [diff] [blame] | 412 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 413 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
| 414 | { |
| 415 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; |
| 416 | } |
| 417 | |
| 418 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
| 419 | { |
| 420 | return pci_platform_pm ? |
| 421 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; |
| 422 | } |
| 423 | |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 424 | /** |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 425 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
| 426 | * given PCI device |
| 427 | * @dev: PCI device to handle. |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 428 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | * |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 430 | * RETURN VALUE: |
| 431 | * -EINVAL if the requested state is invalid. |
| 432 | * -EIO if device does not support PCI PM or its PM capabilities register has a |
| 433 | * wrong version, or device doesn't support the requested state. |
| 434 | * 0 if device already is in the requested state. |
| 435 | * 0 if device's power state has been successfully changed. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | */ |
Rafael J. Wysocki | f00a20e | 2009-03-16 22:40:08 +0100 | [diff] [blame] | 437 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 439 | u16 pmcsr; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 440 | bool need_restore = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 441 | |
Rafael J. Wysocki | 4a86590 | 2009-03-16 22:40:36 +0100 | [diff] [blame] | 442 | /* Check if we're already there */ |
| 443 | if (dev->current_state == state) |
| 444 | return 0; |
| 445 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 446 | if (!dev->pm_cap) |
Andrew Lunn | cca03de | 2007-07-09 11:55:58 -0700 | [diff] [blame] | 447 | return -EIO; |
| 448 | |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 449 | if (state < PCI_D0 || state > PCI_D3hot) |
| 450 | return -EINVAL; |
| 451 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 452 | /* Validate current state: |
| 453 | * Can enter D0 from any state, but if we can only go deeper |
| 454 | * to sleep if we're already in a low power state |
| 455 | */ |
Rafael J. Wysocki | 4a86590 | 2009-03-16 22:40:36 +0100 | [diff] [blame] | 456 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 457 | && dev->current_state > state) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 458 | dev_err(&dev->dev, "invalid power transition " |
| 459 | "(from state %d to %d)\n", dev->current_state, state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | return -EINVAL; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 461 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 463 | /* check if this device supports the desired state */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 464 | if ((state == PCI_D1 && !dev->d1_support) |
| 465 | || (state == PCI_D2 && !dev->d2_support)) |
Daniel Ritz | 3fe9d19 | 2005-08-17 15:32:19 -0700 | [diff] [blame] | 466 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 468 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 469 | |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 470 | /* If we're (effectively) in D3, force entire word to 0. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 471 | * This doesn't affect PME_Status, disables PME_En, and |
| 472 | * sets PowerState to 0. |
| 473 | */ |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 474 | switch (dev->current_state) { |
John W. Linville | d3535fb | 2005-09-28 17:50:51 -0400 | [diff] [blame] | 475 | case PCI_D0: |
| 476 | case PCI_D1: |
| 477 | case PCI_D2: |
| 478 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; |
| 479 | pmcsr |= state; |
| 480 | break; |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 481 | case PCI_UNKNOWN: /* Boot-up */ |
| 482 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot |
Rafael J. Wysocki | f00a20e | 2009-03-16 22:40:08 +0100 | [diff] [blame] | 483 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 484 | need_restore = true; |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 485 | /* Fall-through: force to D0 */ |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 486 | default: |
John W. Linville | d3535fb | 2005-09-28 17:50:51 -0400 | [diff] [blame] | 487 | pmcsr = 0; |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 488 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | } |
| 490 | |
| 491 | /* enter specified state */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 492 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | |
| 494 | /* Mandatory power management transition delays */ |
| 495 | /* see PCI PM 1.1 5.6.1 table 18 */ |
| 496 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
Kristen Carlson Accardi | ffadcc2 | 2006-07-12 08:59:00 -0700 | [diff] [blame] | 497 | msleep(pci_pm_d3_delay); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 498 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
Rafael J. Wysocki | aa8c6c9 | 2009-01-16 21:54:43 +0100 | [diff] [blame] | 499 | udelay(PCI_PM_D2_DELAY); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | |
David Shaohua Li | b913100 | 2005-03-19 00:16:18 -0500 | [diff] [blame] | 501 | dev->current_state = state; |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 502 | |
| 503 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT |
| 504 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
| 505 | * from D3hot to D0 _may_ perform an internal reset, thereby |
| 506 | * going to "D0 Uninitialized" rather than "D0 Initialized". |
| 507 | * For example, at least some versions of the 3c905B and the |
| 508 | * 3c556B exhibit this behaviour. |
| 509 | * |
| 510 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave |
| 511 | * devices in a D3hot state at boot. Consequently, we need to |
| 512 | * restore at least the BARs so that the device will be |
| 513 | * accessible to its driver. |
| 514 | */ |
| 515 | if (need_restore) |
| 516 | pci_restore_bars(dev); |
| 517 | |
Rafael J. Wysocki | f00a20e | 2009-03-16 22:40:08 +0100 | [diff] [blame] | 518 | if (dev->bus->self) |
Shaohua Li | 7d715a6 | 2008-02-25 09:46:41 +0800 | [diff] [blame] | 519 | pcie_aspm_pm_state_change(dev->bus->self); |
| 520 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 521 | return 0; |
| 522 | } |
| 523 | |
| 524 | /** |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 525 | * pci_update_current_state - Read PCI power state of given device from its |
| 526 | * PCI PM registers and cache it |
| 527 | * @dev: PCI device to handle. |
Rafael J. Wysocki | f06fc0b | 2008-12-27 16:30:52 +0100 | [diff] [blame] | 528 | * @state: State to cache in case the device doesn't have the PM capability |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 529 | */ |
Rafael J. Wysocki | 73410429 | 2009-01-07 13:07:15 +0100 | [diff] [blame] | 530 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 531 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 532 | if (dev->pm_cap) { |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 533 | u16 pmcsr; |
| 534 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 535 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 536 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
Rafael J. Wysocki | f06fc0b | 2008-12-27 16:30:52 +0100 | [diff] [blame] | 537 | } else { |
| 538 | dev->current_state = state; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 539 | } |
| 540 | } |
| 541 | |
| 542 | /** |
| 543 | * pci_set_power_state - Set the power state of a PCI device |
| 544 | * @dev: PCI device to handle. |
| 545 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
| 546 | * |
| 547 | * Transition a device to a new power state, using the platform formware and/or |
| 548 | * the device's PCI PM registers. |
| 549 | * |
| 550 | * RETURN VALUE: |
| 551 | * -EINVAL if the requested state is invalid. |
| 552 | * -EIO if device does not support PCI PM or its PM capabilities register has a |
| 553 | * wrong version, or device doesn't support the requested state. |
| 554 | * 0 if device already is in the requested state. |
| 555 | * 0 if device's power state has been successfully changed. |
| 556 | */ |
| 557 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
| 558 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 559 | int error; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 560 | |
| 561 | /* bound the state we're entering */ |
| 562 | if (state > PCI_D3hot) |
| 563 | state = PCI_D3hot; |
| 564 | else if (state < PCI_D0) |
| 565 | state = PCI_D0; |
| 566 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) |
| 567 | /* |
| 568 | * If the device or the parent bridge do not support PCI PM, |
| 569 | * ignore the request if we're doing anything other than putting |
| 570 | * it into D0 (which would only happen on boot). |
| 571 | */ |
| 572 | return 0; |
| 573 | |
Rafael J. Wysocki | 4a86590 | 2009-03-16 22:40:36 +0100 | [diff] [blame] | 574 | /* Check if we're already there */ |
| 575 | if (dev->current_state == state) |
| 576 | return 0; |
| 577 | |
| 578 | if (state == PCI_D0) { |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 579 | /* |
| 580 | * Allow the platform to change the state, for example via ACPI |
| 581 | * _PR0, _PS0 and some such, but do not trust it. |
| 582 | */ |
Rafael J. Wysocki | 4a86590 | 2009-03-16 22:40:36 +0100 | [diff] [blame] | 583 | int ret = platform_pci_power_manageable(dev) ? |
| 584 | platform_pci_set_power_state(dev, PCI_D0) : 0; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 585 | if (!ret) |
Rafael J. Wysocki | f06fc0b | 2008-12-27 16:30:52 +0100 | [diff] [blame] | 586 | pci_update_current_state(dev, PCI_D0); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 587 | } |
Alan Cox | 979b179 | 2008-07-24 17:18:38 +0100 | [diff] [blame] | 588 | /* This device is quirked not to be put into D3, so |
| 589 | don't put it in D3 */ |
| 590 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
| 591 | return 0; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 592 | |
Rafael J. Wysocki | f00a20e | 2009-03-16 22:40:08 +0100 | [diff] [blame] | 593 | error = pci_raw_set_power_state(dev, state); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 594 | |
| 595 | if (state > PCI_D0 && platform_pci_power_manageable(dev)) { |
| 596 | /* Allow the platform to finalize the transition */ |
| 597 | int ret = platform_pci_set_power_state(dev, state); |
| 598 | if (!ret) { |
Rafael J. Wysocki | f06fc0b | 2008-12-27 16:30:52 +0100 | [diff] [blame] | 599 | pci_update_current_state(dev, state); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 600 | error = 0; |
| 601 | } |
| 602 | } |
| 603 | |
| 604 | return error; |
| 605 | } |
| 606 | |
| 607 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | * pci_choose_state - Choose the power state of a PCI device |
| 609 | * @dev: PCI device to be suspended |
| 610 | * @state: target sleep state for the whole system. This is the value |
| 611 | * that is passed to suspend() function. |
| 612 | * |
| 613 | * Returns PCI power state suitable for given device and given system |
| 614 | * message. |
| 615 | */ |
| 616 | |
| 617 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) |
| 618 | { |
Shaohua Li | ab826ca | 2007-07-20 10:03:22 +0800 | [diff] [blame] | 619 | pci_power_t ret; |
David Shaohua Li | 0f64474 | 2005-03-19 00:15:48 -0500 | [diff] [blame] | 620 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 621 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
| 622 | return PCI_D0; |
| 623 | |
Rafael J. Wysocki | 961d912 | 2008-07-07 03:32:02 +0200 | [diff] [blame] | 624 | ret = platform_pci_choose_state(dev); |
| 625 | if (ret != PCI_POWER_ERROR) |
| 626 | return ret; |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 627 | |
| 628 | switch (state.event) { |
| 629 | case PM_EVENT_ON: |
| 630 | return PCI_D0; |
| 631 | case PM_EVENT_FREEZE: |
David Brownell | b887d2e | 2006-08-14 23:11:05 -0700 | [diff] [blame] | 632 | case PM_EVENT_PRETHAW: |
| 633 | /* REVISIT both freeze and pre-thaw "should" use D0 */ |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 634 | case PM_EVENT_SUSPEND: |
Rafael J. Wysocki | 3a2d5b7 | 2008-02-23 19:13:25 +0100 | [diff] [blame] | 635 | case PM_EVENT_HIBERNATE: |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 636 | return PCI_D3hot; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | default: |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 638 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
| 639 | state.event); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | BUG(); |
| 641 | } |
| 642 | return PCI_D0; |
| 643 | } |
| 644 | |
| 645 | EXPORT_SYMBOL(pci_choose_state); |
| 646 | |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 647 | static int pci_save_pcie_state(struct pci_dev *dev) |
| 648 | { |
| 649 | int pos, i = 0; |
| 650 | struct pci_cap_saved_state *save_state; |
| 651 | u16 *cap; |
| 652 | |
| 653 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 654 | if (pos <= 0) |
| 655 | return 0; |
| 656 | |
Eric W. Biederman | 9f35575 | 2007-03-08 13:06:13 -0700 | [diff] [blame] | 657 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 658 | if (!save_state) { |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 659 | dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 660 | return -ENOMEM; |
| 661 | } |
| 662 | cap = (u16 *)&save_state->data[0]; |
| 663 | |
| 664 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); |
| 665 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); |
| 666 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); |
| 667 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 668 | |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 669 | return 0; |
| 670 | } |
| 671 | |
| 672 | static void pci_restore_pcie_state(struct pci_dev *dev) |
| 673 | { |
| 674 | int i = 0, pos; |
| 675 | struct pci_cap_saved_state *save_state; |
| 676 | u16 *cap; |
| 677 | |
| 678 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
| 679 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 680 | if (!save_state || pos <= 0) |
| 681 | return; |
| 682 | cap = (u16 *)&save_state->data[0]; |
| 683 | |
| 684 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); |
| 685 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); |
| 686 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); |
| 687 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 688 | } |
| 689 | |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 690 | |
| 691 | static int pci_save_pcix_state(struct pci_dev *dev) |
| 692 | { |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 693 | int pos; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 694 | struct pci_cap_saved_state *save_state; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 695 | |
| 696 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 697 | if (pos <= 0) |
| 698 | return 0; |
| 699 | |
Shaohua Li | f34303d | 2007-12-18 09:56:47 +0800 | [diff] [blame] | 700 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 701 | if (!save_state) { |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 702 | dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__); |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 703 | return -ENOMEM; |
| 704 | } |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 705 | |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 706 | pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data); |
| 707 | |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 708 | return 0; |
| 709 | } |
| 710 | |
| 711 | static void pci_restore_pcix_state(struct pci_dev *dev) |
| 712 | { |
| 713 | int i = 0, pos; |
| 714 | struct pci_cap_saved_state *save_state; |
| 715 | u16 *cap; |
| 716 | |
| 717 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
| 718 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 719 | if (!save_state || pos <= 0) |
| 720 | return; |
| 721 | cap = (u16 *)&save_state->data[0]; |
| 722 | |
| 723 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 724 | } |
| 725 | |
| 726 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | /** |
| 728 | * pci_save_state - save the PCI configuration space of a device before suspending |
| 729 | * @dev: - PCI device that we're dealing with |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 730 | */ |
| 731 | int |
| 732 | pci_save_state(struct pci_dev *dev) |
| 733 | { |
| 734 | int i; |
| 735 | /* XXX: 100% dword access ok here? */ |
| 736 | for (i = 0; i < 16; i++) |
| 737 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); |
Rafael J. Wysocki | aa8c6c9 | 2009-01-16 21:54:43 +0100 | [diff] [blame] | 738 | dev->state_saved = true; |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 739 | if ((i = pci_save_pcie_state(dev)) != 0) |
| 740 | return i; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 741 | if ((i = pci_save_pcix_state(dev)) != 0) |
| 742 | return i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 743 | return 0; |
| 744 | } |
| 745 | |
| 746 | /** |
| 747 | * pci_restore_state - Restore the saved state of a PCI device |
| 748 | * @dev: - PCI device that we're dealing with |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 749 | */ |
| 750 | int |
| 751 | pci_restore_state(struct pci_dev *dev) |
| 752 | { |
| 753 | int i; |
Al Viro | b4482a4 | 2007-10-14 19:35:40 +0100 | [diff] [blame] | 754 | u32 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 756 | /* PCI Express register must be restored first */ |
| 757 | pci_restore_pcie_state(dev); |
| 758 | |
Yu, Luming | 8b8c8d2 | 2006-04-25 00:00:34 -0700 | [diff] [blame] | 759 | /* |
| 760 | * The Base Address register should be programmed before the command |
| 761 | * register(s) |
| 762 | */ |
| 763 | for (i = 15; i >= 0; i--) { |
Dave Jones | 04d9c1a | 2006-04-18 21:06:51 -0700 | [diff] [blame] | 764 | pci_read_config_dword(dev, i * 4, &val); |
| 765 | if (val != dev->saved_config_space[i]) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 766 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
| 767 | "space at offset %#x (was %#x, writing %#x)\n", |
| 768 | i, val, (int)dev->saved_config_space[i]); |
Dave Jones | 04d9c1a | 2006-04-18 21:06:51 -0700 | [diff] [blame] | 769 | pci_write_config_dword(dev,i * 4, |
| 770 | dev->saved_config_space[i]); |
| 771 | } |
| 772 | } |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 773 | pci_restore_pcix_state(dev); |
Shaohua Li | 41017f0 | 2006-02-08 17:11:38 +0800 | [diff] [blame] | 774 | pci_restore_msi_state(dev); |
Michael Ellerman | 8fed4b6 | 2007-01-25 19:34:08 +1100 | [diff] [blame] | 775 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 776 | return 0; |
| 777 | } |
| 778 | |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 779 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
| 780 | { |
| 781 | int err; |
| 782 | |
| 783 | err = pci_set_power_state(dev, PCI_D0); |
| 784 | if (err < 0 && err != -EIO) |
| 785 | return err; |
| 786 | err = pcibios_enable_device(dev, bars); |
| 787 | if (err < 0) |
| 788 | return err; |
| 789 | pci_fixup_device(pci_fixup_enable, dev); |
| 790 | |
| 791 | return 0; |
| 792 | } |
| 793 | |
| 794 | /** |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 795 | * pci_reenable_device - Resume abandoned device |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 796 | * @dev: PCI device to be resumed |
| 797 | * |
| 798 | * Note this function is a backend of pci_default_resume and is not supposed |
| 799 | * to be called by normal code, write proper resume handler and use it instead. |
| 800 | */ |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 801 | int pci_reenable_device(struct pci_dev *dev) |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 802 | { |
| 803 | if (atomic_read(&dev->enable_cnt)) |
| 804 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
| 805 | return 0; |
| 806 | } |
| 807 | |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 808 | static int __pci_enable_device_flags(struct pci_dev *dev, |
| 809 | resource_size_t flags) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 810 | { |
| 811 | int err; |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 812 | int i, bars = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 813 | |
Hidetoshi Seto | 9fb625c | 2006-12-18 10:28:43 +0900 | [diff] [blame] | 814 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
| 815 | return 0; /* already enabled */ |
| 816 | |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 817 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
| 818 | if (dev->resource[i].flags & flags) |
| 819 | bars |= (1 << i); |
| 820 | |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 821 | err = do_pci_enable_device(dev, bars); |
Greg Kroah-Hartman | 95a6296 | 2005-07-28 11:37:33 -0700 | [diff] [blame] | 822 | if (err < 0) |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 823 | atomic_dec(&dev->enable_cnt); |
Hidetoshi Seto | 9fb625c | 2006-12-18 10:28:43 +0900 | [diff] [blame] | 824 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 825 | } |
| 826 | |
| 827 | /** |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 828 | * pci_enable_device_io - Initialize a device for use with IO space |
| 829 | * @dev: PCI device to be initialized |
| 830 | * |
| 831 | * Initialize device before it's used by a driver. Ask low-level code |
| 832 | * to enable I/O resources. Wake up the device if it was suspended. |
| 833 | * Beware, this function can fail. |
| 834 | */ |
| 835 | int pci_enable_device_io(struct pci_dev *dev) |
| 836 | { |
| 837 | return __pci_enable_device_flags(dev, IORESOURCE_IO); |
| 838 | } |
| 839 | |
| 840 | /** |
| 841 | * pci_enable_device_mem - Initialize a device for use with Memory space |
| 842 | * @dev: PCI device to be initialized |
| 843 | * |
| 844 | * Initialize device before it's used by a driver. Ask low-level code |
| 845 | * to enable Memory resources. Wake up the device if it was suspended. |
| 846 | * Beware, this function can fail. |
| 847 | */ |
| 848 | int pci_enable_device_mem(struct pci_dev *dev) |
| 849 | { |
| 850 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); |
| 851 | } |
| 852 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 853 | /** |
| 854 | * pci_enable_device - Initialize device before it's used by a driver. |
| 855 | * @dev: PCI device to be initialized |
| 856 | * |
| 857 | * Initialize device before it's used by a driver. Ask low-level code |
| 858 | * to enable I/O and memory. Wake up the device if it was suspended. |
| 859 | * Beware, this function can fail. |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 860 | * |
| 861 | * Note we don't actually enable the device many times if we call |
| 862 | * this function repeatedly (we just increment the count). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 863 | */ |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 864 | int pci_enable_device(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 865 | { |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 866 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 867 | } |
| 868 | |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 869 | /* |
| 870 | * Managed PCI resources. This manages device on/off, intx/msi/msix |
| 871 | * on/off and BAR regions. pci_dev itself records msi/msix status, so |
| 872 | * there's no need to track it separately. pci_devres is initialized |
| 873 | * when a device is enabled using managed PCI device enable interface. |
| 874 | */ |
| 875 | struct pci_devres { |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 876 | unsigned int enabled:1; |
| 877 | unsigned int pinned:1; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 878 | unsigned int orig_intx:1; |
| 879 | unsigned int restore_intx:1; |
| 880 | u32 region_mask; |
| 881 | }; |
| 882 | |
| 883 | static void pcim_release(struct device *gendev, void *res) |
| 884 | { |
| 885 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); |
| 886 | struct pci_devres *this = res; |
| 887 | int i; |
| 888 | |
| 889 | if (dev->msi_enabled) |
| 890 | pci_disable_msi(dev); |
| 891 | if (dev->msix_enabled) |
| 892 | pci_disable_msix(dev); |
| 893 | |
| 894 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
| 895 | if (this->region_mask & (1 << i)) |
| 896 | pci_release_region(dev, i); |
| 897 | |
| 898 | if (this->restore_intx) |
| 899 | pci_intx(dev, this->orig_intx); |
| 900 | |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 901 | if (this->enabled && !this->pinned) |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 902 | pci_disable_device(dev); |
| 903 | } |
| 904 | |
| 905 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) |
| 906 | { |
| 907 | struct pci_devres *dr, *new_dr; |
| 908 | |
| 909 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); |
| 910 | if (dr) |
| 911 | return dr; |
| 912 | |
| 913 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); |
| 914 | if (!new_dr) |
| 915 | return NULL; |
| 916 | return devres_get(&pdev->dev, new_dr, NULL, NULL); |
| 917 | } |
| 918 | |
| 919 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) |
| 920 | { |
| 921 | if (pci_is_managed(pdev)) |
| 922 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); |
| 923 | return NULL; |
| 924 | } |
| 925 | |
| 926 | /** |
| 927 | * pcim_enable_device - Managed pci_enable_device() |
| 928 | * @pdev: PCI device to be initialized |
| 929 | * |
| 930 | * Managed pci_enable_device(). |
| 931 | */ |
| 932 | int pcim_enable_device(struct pci_dev *pdev) |
| 933 | { |
| 934 | struct pci_devres *dr; |
| 935 | int rc; |
| 936 | |
| 937 | dr = get_pci_dr(pdev); |
| 938 | if (unlikely(!dr)) |
| 939 | return -ENOMEM; |
Tejun Heo | b95d58e | 2008-01-30 18:20:04 +0900 | [diff] [blame] | 940 | if (dr->enabled) |
| 941 | return 0; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 942 | |
| 943 | rc = pci_enable_device(pdev); |
| 944 | if (!rc) { |
| 945 | pdev->is_managed = 1; |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 946 | dr->enabled = 1; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 947 | } |
| 948 | return rc; |
| 949 | } |
| 950 | |
| 951 | /** |
| 952 | * pcim_pin_device - Pin managed PCI device |
| 953 | * @pdev: PCI device to pin |
| 954 | * |
| 955 | * Pin managed PCI device @pdev. Pinned device won't be disabled on |
| 956 | * driver detach. @pdev must have been enabled with |
| 957 | * pcim_enable_device(). |
| 958 | */ |
| 959 | void pcim_pin_device(struct pci_dev *pdev) |
| 960 | { |
| 961 | struct pci_devres *dr; |
| 962 | |
| 963 | dr = find_pci_dr(pdev); |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 964 | WARN_ON(!dr || !dr->enabled); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 965 | if (dr) |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 966 | dr->pinned = 1; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 967 | } |
| 968 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 969 | /** |
| 970 | * pcibios_disable_device - disable arch specific PCI resources for device dev |
| 971 | * @dev: the PCI device to disable |
| 972 | * |
| 973 | * Disables architecture specific PCI resources for the device. This |
| 974 | * is the default implementation. Architecture implementations can |
| 975 | * override this. |
| 976 | */ |
| 977 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} |
| 978 | |
Rafael J. Wysocki | fa58d30 | 2009-01-07 13:03:42 +0100 | [diff] [blame] | 979 | static void do_pci_disable_device(struct pci_dev *dev) |
| 980 | { |
| 981 | u16 pci_command; |
| 982 | |
| 983 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
| 984 | if (pci_command & PCI_COMMAND_MASTER) { |
| 985 | pci_command &= ~PCI_COMMAND_MASTER; |
| 986 | pci_write_config_word(dev, PCI_COMMAND, pci_command); |
| 987 | } |
| 988 | |
| 989 | pcibios_disable_device(dev); |
| 990 | } |
| 991 | |
| 992 | /** |
| 993 | * pci_disable_enabled_device - Disable device without updating enable_cnt |
| 994 | * @dev: PCI device to disable |
| 995 | * |
| 996 | * NOTE: This function is a backend of PCI power management routines and is |
| 997 | * not supposed to be called drivers. |
| 998 | */ |
| 999 | void pci_disable_enabled_device(struct pci_dev *dev) |
| 1000 | { |
| 1001 | if (atomic_read(&dev->enable_cnt)) |
| 1002 | do_pci_disable_device(dev); |
| 1003 | } |
| 1004 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1005 | /** |
| 1006 | * pci_disable_device - Disable PCI device after use |
| 1007 | * @dev: PCI device to be disabled |
| 1008 | * |
| 1009 | * Signal to the system that the PCI device is not in use by the system |
| 1010 | * anymore. This only involves disabling PCI bus-mastering, if active. |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 1011 | * |
| 1012 | * Note we don't actually disable the device until all callers of |
| 1013 | * pci_device_enable() have called pci_device_disable(). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1014 | */ |
| 1015 | void |
| 1016 | pci_disable_device(struct pci_dev *dev) |
| 1017 | { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1018 | struct pci_devres *dr; |
Shaohua Li | 99dc804 | 2006-05-26 10:58:27 +0800 | [diff] [blame] | 1019 | |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1020 | dr = find_pci_dr(dev); |
| 1021 | if (dr) |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 1022 | dr->enabled = 0; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1023 | |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 1024 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
| 1025 | return; |
| 1026 | |
Rafael J. Wysocki | fa58d30 | 2009-01-07 13:03:42 +0100 | [diff] [blame] | 1027 | do_pci_disable_device(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1028 | |
Rafael J. Wysocki | fa58d30 | 2009-01-07 13:03:42 +0100 | [diff] [blame] | 1029 | dev->is_busmaster = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1030 | } |
| 1031 | |
| 1032 | /** |
Brian King | f7bdd12 | 2007-04-06 16:39:36 -0500 | [diff] [blame] | 1033 | * pcibios_set_pcie_reset_state - set reset state for device dev |
| 1034 | * @dev: the PCI-E device reset |
| 1035 | * @state: Reset state to enter into |
| 1036 | * |
| 1037 | * |
| 1038 | * Sets the PCI-E reset state for the device. This is the default |
| 1039 | * implementation. Architecture implementations can override this. |
| 1040 | */ |
| 1041 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, |
| 1042 | enum pcie_reset_state state) |
| 1043 | { |
| 1044 | return -EINVAL; |
| 1045 | } |
| 1046 | |
| 1047 | /** |
| 1048 | * pci_set_pcie_reset_state - set reset state for device dev |
| 1049 | * @dev: the PCI-E device reset |
| 1050 | * @state: Reset state to enter into |
| 1051 | * |
| 1052 | * |
| 1053 | * Sets the PCI reset state for the device. |
| 1054 | */ |
| 1055 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
| 1056 | { |
| 1057 | return pcibios_set_pcie_reset_state(dev, state); |
| 1058 | } |
| 1059 | |
| 1060 | /** |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1061 | * pci_pme_capable - check the capability of PCI device to generate PME# |
| 1062 | * @dev: PCI device to handle. |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1063 | * @state: PCI state from which device will issue PME#. |
| 1064 | */ |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 1065 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1066 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1067 | if (!dev->pm_cap) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1068 | return false; |
| 1069 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1070 | return !!(dev->pme_support & (1 << state)); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1071 | } |
| 1072 | |
| 1073 | /** |
| 1074 | * pci_pme_active - enable or disable PCI device's PME# function |
| 1075 | * @dev: PCI device to handle. |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1076 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
| 1077 | * |
| 1078 | * The caller must verify that the device is capable of generating PME# before |
| 1079 | * calling this function with @enable equal to 'true'. |
| 1080 | */ |
Rafael J. Wysocki | 5a6c9b6 | 2008-08-08 00:14:24 +0200 | [diff] [blame] | 1081 | void pci_pme_active(struct pci_dev *dev, bool enable) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1082 | { |
| 1083 | u16 pmcsr; |
| 1084 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1085 | if (!dev->pm_cap) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1086 | return; |
| 1087 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1088 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1089 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
| 1090 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; |
| 1091 | if (!enable) |
| 1092 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; |
| 1093 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1094 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1095 | |
| 1096 | dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", |
| 1097 | enable ? "enabled" : "disabled"); |
| 1098 | } |
| 1099 | |
| 1100 | /** |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1101 | * pci_enable_wake - enable PCI device as wakeup event source |
| 1102 | * @dev: PCI device affected |
| 1103 | * @state: PCI state from which device will issue wakeup events |
| 1104 | * @enable: True to enable event generation; false to disable |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1105 | * |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1106 | * This enables the device as a wakeup event source, or disables it. |
| 1107 | * When such events involves platform-specific hooks, those hooks are |
| 1108 | * called automatically by this routine. |
| 1109 | * |
| 1110 | * Devices with legacy power management (no standard PCI PM capabilities) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1111 | * always require such platform hooks. |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1112 | * |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1113 | * RETURN VALUE: |
| 1114 | * 0 is returned on success |
| 1115 | * -EINVAL is returned if device is not supposed to wake up the system |
| 1116 | * Error code depending on the platform is returned if both the platform and |
| 1117 | * the native mechanism fail to enable the generation of wake-up events |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1118 | */ |
| 1119 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) |
| 1120 | { |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1121 | int error = 0; |
| 1122 | bool pme_done = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1123 | |
Alan Stern | bebd590 | 2008-12-16 14:06:58 -0500 | [diff] [blame] | 1124 | if (enable && !device_may_wakeup(&dev->dev)) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1125 | return -EINVAL; |
| 1126 | |
| 1127 | /* |
| 1128 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don |
| 1129 | * Anderson we should be doing PME# wake enable followed by ACPI wake |
| 1130 | * enable. To disable wake-up we call the platform first, for symmetry. |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1131 | */ |
| 1132 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1133 | if (!enable && platform_pci_can_wakeup(dev)) |
| 1134 | error = platform_pci_sleep_wake(dev, false); |
| 1135 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1136 | if (!enable || pci_pme_capable(dev, state)) { |
| 1137 | pci_pme_active(dev, enable); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1138 | pme_done = true; |
| 1139 | } |
| 1140 | |
| 1141 | if (enable && platform_pci_can_wakeup(dev)) |
| 1142 | error = platform_pci_sleep_wake(dev, true); |
| 1143 | |
| 1144 | return pme_done ? 0 : error; |
| 1145 | } |
| 1146 | |
| 1147 | /** |
Rafael J. Wysocki | 0235c4f | 2008-08-18 21:38:00 +0200 | [diff] [blame] | 1148 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold |
| 1149 | * @dev: PCI device to prepare |
| 1150 | * @enable: True to enable wake-up event generation; false to disable |
| 1151 | * |
| 1152 | * Many drivers want the device to wake up the system from D3_hot or D3_cold |
| 1153 | * and this function allows them to set that up cleanly - pci_enable_wake() |
| 1154 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI |
| 1155 | * ordering constraints. |
| 1156 | * |
| 1157 | * This function only returns error code if the device is not capable of |
| 1158 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to |
| 1159 | * enable wake-up power for it. |
| 1160 | */ |
| 1161 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
| 1162 | { |
| 1163 | return pci_pme_capable(dev, PCI_D3cold) ? |
| 1164 | pci_enable_wake(dev, PCI_D3cold, enable) : |
| 1165 | pci_enable_wake(dev, PCI_D3hot, enable); |
| 1166 | } |
| 1167 | |
| 1168 | /** |
Jesse Barnes | 3713907 | 2008-07-28 11:49:26 -0700 | [diff] [blame] | 1169 | * pci_target_state - find an appropriate low power state for a given PCI dev |
| 1170 | * @dev: PCI device |
| 1171 | * |
| 1172 | * Use underlying platform code to find a supported low power state for @dev. |
| 1173 | * If the platform can't manage @dev, return the deepest state from which it |
| 1174 | * can generate wake events, based on any available PME info. |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1175 | */ |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 1176 | pci_power_t pci_target_state(struct pci_dev *dev) |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1177 | { |
| 1178 | pci_power_t target_state = PCI_D3hot; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1179 | |
| 1180 | if (platform_pci_power_manageable(dev)) { |
| 1181 | /* |
| 1182 | * Call the platform to choose the target state of the device |
| 1183 | * and enable wake-up from this state if supported. |
| 1184 | */ |
| 1185 | pci_power_t state = platform_pci_choose_state(dev); |
| 1186 | |
| 1187 | switch (state) { |
| 1188 | case PCI_POWER_ERROR: |
| 1189 | case PCI_UNKNOWN: |
| 1190 | break; |
| 1191 | case PCI_D1: |
| 1192 | case PCI_D2: |
| 1193 | if (pci_no_d1d2(dev)) |
| 1194 | break; |
| 1195 | default: |
| 1196 | target_state = state; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1197 | } |
| 1198 | } else if (device_may_wakeup(&dev->dev)) { |
| 1199 | /* |
| 1200 | * Find the deepest state from which the device can generate |
| 1201 | * wake-up events, make it the target state and enable device |
| 1202 | * to generate PME#. |
| 1203 | */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1204 | if (!dev->pm_cap) |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 1205 | return PCI_POWER_ERROR; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1206 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1207 | if (dev->pme_support) { |
| 1208 | while (target_state |
| 1209 | && !(dev->pme_support & (1 << target_state))) |
| 1210 | target_state--; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1211 | } |
| 1212 | } |
| 1213 | |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 1214 | return target_state; |
| 1215 | } |
| 1216 | |
| 1217 | /** |
| 1218 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state |
| 1219 | * @dev: Device to handle. |
| 1220 | * |
| 1221 | * Choose the power state appropriate for the device depending on whether |
| 1222 | * it can wake up the system and/or is power manageable by the platform |
| 1223 | * (PCI_D3hot is the default) and put the device into that state. |
| 1224 | */ |
| 1225 | int pci_prepare_to_sleep(struct pci_dev *dev) |
| 1226 | { |
| 1227 | pci_power_t target_state = pci_target_state(dev); |
| 1228 | int error; |
| 1229 | |
| 1230 | if (target_state == PCI_POWER_ERROR) |
| 1231 | return -EIO; |
| 1232 | |
Rafael J. Wysocki | c157dfa | 2008-07-13 22:45:06 +0200 | [diff] [blame] | 1233 | pci_enable_wake(dev, target_state, true); |
| 1234 | |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1235 | error = pci_set_power_state(dev, target_state); |
| 1236 | |
| 1237 | if (error) |
| 1238 | pci_enable_wake(dev, target_state, false); |
| 1239 | |
| 1240 | return error; |
| 1241 | } |
| 1242 | |
| 1243 | /** |
Randy Dunlap | 443bd1c | 2008-07-21 09:27:18 -0700 | [diff] [blame] | 1244 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1245 | * @dev: Device to handle. |
| 1246 | * |
| 1247 | * Disable device's sytem wake-up capability and put it into D0. |
| 1248 | */ |
| 1249 | int pci_back_from_sleep(struct pci_dev *dev) |
| 1250 | { |
| 1251 | pci_enable_wake(dev, PCI_D0, false); |
| 1252 | return pci_set_power_state(dev, PCI_D0); |
| 1253 | } |
| 1254 | |
| 1255 | /** |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1256 | * pci_pm_init - Initialize PM functions of given PCI device |
| 1257 | * @dev: PCI device to handle. |
| 1258 | */ |
| 1259 | void pci_pm_init(struct pci_dev *dev) |
| 1260 | { |
| 1261 | int pm; |
| 1262 | u16 pmc; |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1263 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1264 | dev->pm_cap = 0; |
| 1265 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1266 | /* find PCI PM capability in list */ |
| 1267 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1268 | if (!pm) |
Linus Torvalds | 50246dd | 2009-01-16 08:14:51 -0800 | [diff] [blame] | 1269 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1270 | /* Check device's ability to generate PME# */ |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1271 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1272 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1273 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
| 1274 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", |
| 1275 | pmc & PCI_PM_CAP_VER_MASK); |
Linus Torvalds | 50246dd | 2009-01-16 08:14:51 -0800 | [diff] [blame] | 1276 | return; |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1277 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1278 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1279 | dev->pm_cap = pm; |
| 1280 | |
| 1281 | dev->d1_support = false; |
| 1282 | dev->d2_support = false; |
| 1283 | if (!pci_no_d1d2(dev)) { |
Bjorn Helgaas | c9ed77e | 2008-08-22 09:37:02 -0600 | [diff] [blame] | 1284 | if (pmc & PCI_PM_CAP_D1) |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1285 | dev->d1_support = true; |
Bjorn Helgaas | c9ed77e | 2008-08-22 09:37:02 -0600 | [diff] [blame] | 1286 | if (pmc & PCI_PM_CAP_D2) |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1287 | dev->d2_support = true; |
Bjorn Helgaas | c9ed77e | 2008-08-22 09:37:02 -0600 | [diff] [blame] | 1288 | |
| 1289 | if (dev->d1_support || dev->d2_support) |
| 1290 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", |
Jesse Barnes | ec84f12 | 2008-09-23 11:43:34 -0700 | [diff] [blame] | 1291 | dev->d1_support ? " D1" : "", |
| 1292 | dev->d2_support ? " D2" : ""); |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1293 | } |
| 1294 | |
| 1295 | pmc &= PCI_PM_CAP_PME_MASK; |
| 1296 | if (pmc) { |
Bjorn Helgaas | c9ed77e | 2008-08-22 09:37:02 -0600 | [diff] [blame] | 1297 | dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n", |
| 1298 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
| 1299 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", |
| 1300 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", |
| 1301 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", |
| 1302 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1303 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1304 | /* |
| 1305 | * Make device's PM flags reflect the wake-up capability, but |
| 1306 | * let the user space enable it to wake up the system as needed. |
| 1307 | */ |
| 1308 | device_set_wakeup_capable(&dev->dev, true); |
| 1309 | device_set_wakeup_enable(&dev->dev, false); |
| 1310 | /* Disable the PME# generation functionality */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1311 | pci_pme_active(dev, false); |
| 1312 | } else { |
| 1313 | dev->pme_support = 0; |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1314 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1315 | } |
| 1316 | |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1317 | /** |
Jesse Barnes | eb9c39d | 2008-12-17 12:10:05 -0800 | [diff] [blame] | 1318 | * platform_pci_wakeup_init - init platform wakeup if present |
| 1319 | * @dev: PCI device |
| 1320 | * |
| 1321 | * Some devices don't have PCI PM caps but can still generate wakeup |
| 1322 | * events through platform methods (like ACPI events). If @dev supports |
| 1323 | * platform wakeup events, set the device flag to indicate as much. This |
| 1324 | * may be redundant if the device also supports PCI PM caps, but double |
| 1325 | * initialization should be safe in that case. |
| 1326 | */ |
| 1327 | void platform_pci_wakeup_init(struct pci_dev *dev) |
| 1328 | { |
| 1329 | if (!platform_pci_can_wakeup(dev)) |
| 1330 | return; |
| 1331 | |
| 1332 | device_set_wakeup_capable(&dev->dev, true); |
| 1333 | device_set_wakeup_enable(&dev->dev, false); |
| 1334 | platform_pci_sleep_wake(dev, false); |
| 1335 | } |
| 1336 | |
| 1337 | /** |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 1338 | * pci_add_save_buffer - allocate buffer for saving given capability registers |
| 1339 | * @dev: the PCI device |
| 1340 | * @cap: the capability to allocate the buffer for |
| 1341 | * @size: requested size of the buffer |
| 1342 | */ |
| 1343 | static int pci_add_cap_save_buffer( |
| 1344 | struct pci_dev *dev, char cap, unsigned int size) |
| 1345 | { |
| 1346 | int pos; |
| 1347 | struct pci_cap_saved_state *save_state; |
| 1348 | |
| 1349 | pos = pci_find_capability(dev, cap); |
| 1350 | if (pos <= 0) |
| 1351 | return 0; |
| 1352 | |
| 1353 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); |
| 1354 | if (!save_state) |
| 1355 | return -ENOMEM; |
| 1356 | |
| 1357 | save_state->cap_nr = cap; |
| 1358 | pci_add_saved_cap(dev, save_state); |
| 1359 | |
| 1360 | return 0; |
| 1361 | } |
| 1362 | |
| 1363 | /** |
| 1364 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities |
| 1365 | * @dev: the PCI device |
| 1366 | */ |
| 1367 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) |
| 1368 | { |
| 1369 | int error; |
| 1370 | |
| 1371 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 4 * sizeof(u16)); |
| 1372 | if (error) |
| 1373 | dev_err(&dev->dev, |
| 1374 | "unable to preallocate PCI Express save buffer\n"); |
| 1375 | |
| 1376 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); |
| 1377 | if (error) |
| 1378 | dev_err(&dev->dev, |
| 1379 | "unable to preallocate PCI-X save buffer\n"); |
| 1380 | } |
| 1381 | |
| 1382 | /** |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1383 | * pci_enable_ari - enable ARI forwarding if hardware support it |
| 1384 | * @dev: the PCI device |
| 1385 | */ |
| 1386 | void pci_enable_ari(struct pci_dev *dev) |
| 1387 | { |
| 1388 | int pos; |
| 1389 | u32 cap; |
| 1390 | u16 ctrl; |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1391 | struct pci_dev *bridge; |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1392 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1393 | if (!dev->is_pcie || dev->devfn) |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1394 | return; |
| 1395 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1396 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1397 | if (!pos) |
| 1398 | return; |
| 1399 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1400 | bridge = dev->bus->self; |
| 1401 | if (!bridge || !bridge->is_pcie) |
| 1402 | return; |
| 1403 | |
| 1404 | pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); |
| 1405 | if (!pos) |
| 1406 | return; |
| 1407 | |
| 1408 | pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1409 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
| 1410 | return; |
| 1411 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1412 | pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1413 | ctrl |= PCI_EXP_DEVCTL2_ARI; |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1414 | pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1415 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1416 | bridge->ari_enabled = 1; |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1417 | } |
| 1418 | |
Bjorn Helgaas | 57c2cf7 | 2008-12-11 11:24:23 -0700 | [diff] [blame] | 1419 | /** |
| 1420 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge |
| 1421 | * @dev: the PCI device |
| 1422 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) |
| 1423 | * |
| 1424 | * Perform INTx swizzling for a device behind one level of bridge. This is |
| 1425 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices |
| 1426 | * behind bridges on add-in cards. |
| 1427 | */ |
| 1428 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) |
| 1429 | { |
| 1430 | return (((pin - 1) + PCI_SLOT(dev->devfn)) % 4) + 1; |
| 1431 | } |
| 1432 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1433 | int |
| 1434 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
| 1435 | { |
| 1436 | u8 pin; |
| 1437 | |
Kristen Accardi | 514d207 | 2005-11-02 16:24:39 -0800 | [diff] [blame] | 1438 | pin = dev->pin; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1439 | if (!pin) |
| 1440 | return -1; |
Bjorn Helgaas | 878f2e5 | 2008-12-09 16:11:46 -0700 | [diff] [blame] | 1441 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1442 | while (dev->bus->self) { |
Bjorn Helgaas | 57c2cf7 | 2008-12-11 11:24:23 -0700 | [diff] [blame] | 1443 | pin = pci_swizzle_interrupt_pin(dev, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1444 | dev = dev->bus->self; |
| 1445 | } |
| 1446 | *bridge = dev; |
| 1447 | return pin; |
| 1448 | } |
| 1449 | |
| 1450 | /** |
Bjorn Helgaas | 68feac8 | 2008-12-16 21:36:55 -0700 | [diff] [blame] | 1451 | * pci_common_swizzle - swizzle INTx all the way to root bridge |
| 1452 | * @dev: the PCI device |
| 1453 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) |
| 1454 | * |
| 1455 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI |
| 1456 | * bridges all the way up to a PCI root bus. |
| 1457 | */ |
| 1458 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) |
| 1459 | { |
| 1460 | u8 pin = *pinp; |
| 1461 | |
| 1462 | while (dev->bus->self) { |
| 1463 | pin = pci_swizzle_interrupt_pin(dev, pin); |
| 1464 | dev = dev->bus->self; |
| 1465 | } |
| 1466 | *pinp = pin; |
| 1467 | return PCI_SLOT(dev->devfn); |
| 1468 | } |
| 1469 | |
| 1470 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1471 | * pci_release_region - Release a PCI bar |
| 1472 | * @pdev: PCI device whose resources were previously reserved by pci_request_region |
| 1473 | * @bar: BAR to release |
| 1474 | * |
| 1475 | * Releases the PCI I/O and memory resources previously reserved by a |
| 1476 | * successful call to pci_request_region. Call this function only |
| 1477 | * after all use of the PCI regions has ceased. |
| 1478 | */ |
| 1479 | void pci_release_region(struct pci_dev *pdev, int bar) |
| 1480 | { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1481 | struct pci_devres *dr; |
| 1482 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1483 | if (pci_resource_len(pdev, bar) == 0) |
| 1484 | return; |
| 1485 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) |
| 1486 | release_region(pci_resource_start(pdev, bar), |
| 1487 | pci_resource_len(pdev, bar)); |
| 1488 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) |
| 1489 | release_mem_region(pci_resource_start(pdev, bar), |
| 1490 | pci_resource_len(pdev, bar)); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1491 | |
| 1492 | dr = find_pci_dr(pdev); |
| 1493 | if (dr) |
| 1494 | dr->region_mask &= ~(1 << bar); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1495 | } |
| 1496 | |
| 1497 | /** |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 1498 | * __pci_request_region - Reserved PCI I/O and memory resource |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1499 | * @pdev: PCI device whose resources are to be reserved |
| 1500 | * @bar: BAR to be reserved |
| 1501 | * @res_name: Name to be associated with resource. |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 1502 | * @exclusive: whether the region access is exclusive or not |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1503 | * |
| 1504 | * Mark the PCI region associated with PCI device @pdev BR @bar as |
| 1505 | * being reserved by owner @res_name. Do not access any |
| 1506 | * address inside the PCI regions unless this call returns |
| 1507 | * successfully. |
| 1508 | * |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 1509 | * If @exclusive is set, then the region is marked so that userspace |
| 1510 | * is explicitly not allowed to map the resource via /dev/mem or |
| 1511 | * sysfs MMIO access. |
| 1512 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1513 | * Returns 0 on success, or %EBUSY on error. A warning |
| 1514 | * message is also printed on failure. |
| 1515 | */ |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1516 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
| 1517 | int exclusive) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1518 | { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1519 | struct pci_devres *dr; |
| 1520 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1521 | if (pci_resource_len(pdev, bar) == 0) |
| 1522 | return 0; |
| 1523 | |
| 1524 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
| 1525 | if (!request_region(pci_resource_start(pdev, bar), |
| 1526 | pci_resource_len(pdev, bar), res_name)) |
| 1527 | goto err_out; |
| 1528 | } |
| 1529 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1530 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
| 1531 | pci_resource_len(pdev, bar), res_name, |
| 1532 | exclusive)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1533 | goto err_out; |
| 1534 | } |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1535 | |
| 1536 | dr = find_pci_dr(pdev); |
| 1537 | if (dr) |
| 1538 | dr->region_mask |= 1 << bar; |
| 1539 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1540 | return 0; |
| 1541 | |
| 1542 | err_out: |
Benjamin Herrenschmidt | 096e6f6 | 2008-10-20 15:07:37 +1100 | [diff] [blame] | 1543 | dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n", |
Jesse Barnes | e4ec7a0 | 2008-06-25 16:12:25 -0700 | [diff] [blame] | 1544 | bar, |
| 1545 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", |
Benjamin Herrenschmidt | 096e6f6 | 2008-10-20 15:07:37 +1100 | [diff] [blame] | 1546 | &pdev->resource[bar]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1547 | return -EBUSY; |
| 1548 | } |
| 1549 | |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1550 | /** |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 1551 | * pci_request_region - Reserve PCI I/O and memory resource |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1552 | * @pdev: PCI device whose resources are to be reserved |
| 1553 | * @bar: BAR to be reserved |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 1554 | * @res_name: Name to be associated with resource |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1555 | * |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 1556 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1557 | * being reserved by owner @res_name. Do not access any |
| 1558 | * address inside the PCI regions unless this call returns |
| 1559 | * successfully. |
| 1560 | * |
| 1561 | * Returns 0 on success, or %EBUSY on error. A warning |
| 1562 | * message is also printed on failure. |
| 1563 | */ |
| 1564 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
| 1565 | { |
| 1566 | return __pci_request_region(pdev, bar, res_name, 0); |
| 1567 | } |
| 1568 | |
| 1569 | /** |
| 1570 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource |
| 1571 | * @pdev: PCI device whose resources are to be reserved |
| 1572 | * @bar: BAR to be reserved |
| 1573 | * @res_name: Name to be associated with resource. |
| 1574 | * |
| 1575 | * Mark the PCI region associated with PCI device @pdev BR @bar as |
| 1576 | * being reserved by owner @res_name. Do not access any |
| 1577 | * address inside the PCI regions unless this call returns |
| 1578 | * successfully. |
| 1579 | * |
| 1580 | * Returns 0 on success, or %EBUSY on error. A warning |
| 1581 | * message is also printed on failure. |
| 1582 | * |
| 1583 | * The key difference that _exclusive makes it that userspace is |
| 1584 | * explicitly not allowed to map the resource via /dev/mem or |
| 1585 | * sysfs. |
| 1586 | */ |
| 1587 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) |
| 1588 | { |
| 1589 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); |
| 1590 | } |
| 1591 | /** |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1592 | * pci_release_selected_regions - Release selected PCI I/O and memory resources |
| 1593 | * @pdev: PCI device whose resources were previously reserved |
| 1594 | * @bars: Bitmask of BARs to be released |
| 1595 | * |
| 1596 | * Release selected PCI I/O and memory resources previously reserved. |
| 1597 | * Call this function only after all use of the PCI regions has ceased. |
| 1598 | */ |
| 1599 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) |
| 1600 | { |
| 1601 | int i; |
| 1602 | |
| 1603 | for (i = 0; i < 6; i++) |
| 1604 | if (bars & (1 << i)) |
| 1605 | pci_release_region(pdev, i); |
| 1606 | } |
| 1607 | |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1608 | int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
| 1609 | const char *res_name, int excl) |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1610 | { |
| 1611 | int i; |
| 1612 | |
| 1613 | for (i = 0; i < 6; i++) |
| 1614 | if (bars & (1 << i)) |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1615 | if (__pci_request_region(pdev, i, res_name, excl)) |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1616 | goto err_out; |
| 1617 | return 0; |
| 1618 | |
| 1619 | err_out: |
| 1620 | while(--i >= 0) |
| 1621 | if (bars & (1 << i)) |
| 1622 | pci_release_region(pdev, i); |
| 1623 | |
| 1624 | return -EBUSY; |
| 1625 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1626 | |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1627 | |
| 1628 | /** |
| 1629 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources |
| 1630 | * @pdev: PCI device whose resources are to be reserved |
| 1631 | * @bars: Bitmask of BARs to be requested |
| 1632 | * @res_name: Name to be associated with resource |
| 1633 | */ |
| 1634 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, |
| 1635 | const char *res_name) |
| 1636 | { |
| 1637 | return __pci_request_selected_regions(pdev, bars, res_name, 0); |
| 1638 | } |
| 1639 | |
| 1640 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, |
| 1641 | int bars, const char *res_name) |
| 1642 | { |
| 1643 | return __pci_request_selected_regions(pdev, bars, res_name, |
| 1644 | IORESOURCE_EXCLUSIVE); |
| 1645 | } |
| 1646 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1647 | /** |
| 1648 | * pci_release_regions - Release reserved PCI I/O and memory resources |
| 1649 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions |
| 1650 | * |
| 1651 | * Releases all PCI I/O and memory resources previously reserved by a |
| 1652 | * successful call to pci_request_regions. Call this function only |
| 1653 | * after all use of the PCI regions has ceased. |
| 1654 | */ |
| 1655 | |
| 1656 | void pci_release_regions(struct pci_dev *pdev) |
| 1657 | { |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1658 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1659 | } |
| 1660 | |
| 1661 | /** |
| 1662 | * pci_request_regions - Reserved PCI I/O and memory resources |
| 1663 | * @pdev: PCI device whose resources are to be reserved |
| 1664 | * @res_name: Name to be associated with resource. |
| 1665 | * |
| 1666 | * Mark all PCI regions associated with PCI device @pdev as |
| 1667 | * being reserved by owner @res_name. Do not access any |
| 1668 | * address inside the PCI regions unless this call returns |
| 1669 | * successfully. |
| 1670 | * |
| 1671 | * Returns 0 on success, or %EBUSY on error. A warning |
| 1672 | * message is also printed on failure. |
| 1673 | */ |
Jeff Garzik | 3c990e9 | 2006-03-04 21:52:42 -0500 | [diff] [blame] | 1674 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1675 | { |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1676 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1677 | } |
| 1678 | |
| 1679 | /** |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1680 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources |
| 1681 | * @pdev: PCI device whose resources are to be reserved |
| 1682 | * @res_name: Name to be associated with resource. |
| 1683 | * |
| 1684 | * Mark all PCI regions associated with PCI device @pdev as |
| 1685 | * being reserved by owner @res_name. Do not access any |
| 1686 | * address inside the PCI regions unless this call returns |
| 1687 | * successfully. |
| 1688 | * |
| 1689 | * pci_request_regions_exclusive() will mark the region so that |
| 1690 | * /dev/mem and the sysfs MMIO access will not be allowed. |
| 1691 | * |
| 1692 | * Returns 0 on success, or %EBUSY on error. A warning |
| 1693 | * message is also printed on failure. |
| 1694 | */ |
| 1695 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) |
| 1696 | { |
| 1697 | return pci_request_selected_regions_exclusive(pdev, |
| 1698 | ((1 << 6) - 1), res_name); |
| 1699 | } |
| 1700 | |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 1701 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
| 1702 | { |
| 1703 | u16 old_cmd, cmd; |
| 1704 | |
| 1705 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); |
| 1706 | if (enable) |
| 1707 | cmd = old_cmd | PCI_COMMAND_MASTER; |
| 1708 | else |
| 1709 | cmd = old_cmd & ~PCI_COMMAND_MASTER; |
| 1710 | if (cmd != old_cmd) { |
| 1711 | dev_dbg(&dev->dev, "%s bus mastering\n", |
| 1712 | enable ? "enabling" : "disabling"); |
| 1713 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1714 | } |
| 1715 | dev->is_busmaster = enable; |
| 1716 | } |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 1717 | |
| 1718 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1719 | * pci_set_master - enables bus-mastering for device dev |
| 1720 | * @dev: the PCI device to enable |
| 1721 | * |
| 1722 | * Enables bus-mastering on the device and calls pcibios_set_master() |
| 1723 | * to do the needed arch specific settings. |
| 1724 | */ |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 1725 | void pci_set_master(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1726 | { |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 1727 | __pci_set_master(dev, true); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1728 | pcibios_set_master(dev); |
| 1729 | } |
| 1730 | |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 1731 | /** |
| 1732 | * pci_clear_master - disables bus-mastering for device dev |
| 1733 | * @dev: the PCI device to disable |
| 1734 | */ |
| 1735 | void pci_clear_master(struct pci_dev *dev) |
| 1736 | { |
| 1737 | __pci_set_master(dev, false); |
| 1738 | } |
| 1739 | |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1740 | #ifdef PCI_DISABLE_MWI |
| 1741 | int pci_set_mwi(struct pci_dev *dev) |
| 1742 | { |
| 1743 | return 0; |
| 1744 | } |
| 1745 | |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 1746 | int pci_try_set_mwi(struct pci_dev *dev) |
| 1747 | { |
| 1748 | return 0; |
| 1749 | } |
| 1750 | |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1751 | void pci_clear_mwi(struct pci_dev *dev) |
| 1752 | { |
| 1753 | } |
| 1754 | |
| 1755 | #else |
Matthew Wilcox | ebf5a24 | 2006-10-10 08:01:20 -0600 | [diff] [blame] | 1756 | |
| 1757 | #ifndef PCI_CACHE_LINE_BYTES |
| 1758 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES |
| 1759 | #endif |
| 1760 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1761 | /* This can be overridden by arch code. */ |
Matthew Wilcox | ebf5a24 | 2006-10-10 08:01:20 -0600 | [diff] [blame] | 1762 | /* Don't forget this is measured in 32-bit words, not bytes */ |
| 1763 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1764 | |
| 1765 | /** |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1766 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
| 1767 | * @dev: the PCI device for which MWI is to be enabled |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1768 | * |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1769 | * Helper function for pci_set_mwi. |
| 1770 | * Originally copied from drivers/net/acenic.c. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1771 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
| 1772 | * |
| 1773 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
| 1774 | */ |
| 1775 | static int |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1776 | pci_set_cacheline_size(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1777 | { |
| 1778 | u8 cacheline_size; |
| 1779 | |
| 1780 | if (!pci_cache_line_size) |
| 1781 | return -EINVAL; /* The system doesn't support MWI. */ |
| 1782 | |
| 1783 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be |
| 1784 | equal to or multiple of the right value. */ |
| 1785 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); |
| 1786 | if (cacheline_size >= pci_cache_line_size && |
| 1787 | (cacheline_size % pci_cache_line_size) == 0) |
| 1788 | return 0; |
| 1789 | |
| 1790 | /* Write the correct value. */ |
| 1791 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); |
| 1792 | /* Read it back. */ |
| 1793 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); |
| 1794 | if (cacheline_size == pci_cache_line_size) |
| 1795 | return 0; |
| 1796 | |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 1797 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
| 1798 | "supported\n", pci_cache_line_size << 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1799 | |
| 1800 | return -EINVAL; |
| 1801 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1802 | |
| 1803 | /** |
| 1804 | * pci_set_mwi - enables memory-write-invalidate PCI transaction |
| 1805 | * @dev: the PCI device for which MWI is enabled |
| 1806 | * |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 1807 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1808 | * |
| 1809 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
| 1810 | */ |
| 1811 | int |
| 1812 | pci_set_mwi(struct pci_dev *dev) |
| 1813 | { |
| 1814 | int rc; |
| 1815 | u16 cmd; |
| 1816 | |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1817 | rc = pci_set_cacheline_size(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1818 | if (rc) |
| 1819 | return rc; |
| 1820 | |
| 1821 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 1822 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 1823 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1824 | cmd |= PCI_COMMAND_INVALIDATE; |
| 1825 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1826 | } |
| 1827 | |
| 1828 | return 0; |
| 1829 | } |
| 1830 | |
| 1831 | /** |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 1832 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction |
| 1833 | * @dev: the PCI device for which MWI is enabled |
| 1834 | * |
| 1835 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
| 1836 | * Callers are not required to check the return value. |
| 1837 | * |
| 1838 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
| 1839 | */ |
| 1840 | int pci_try_set_mwi(struct pci_dev *dev) |
| 1841 | { |
| 1842 | int rc = pci_set_mwi(dev); |
| 1843 | return rc; |
| 1844 | } |
| 1845 | |
| 1846 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1847 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev |
| 1848 | * @dev: the PCI device to disable |
| 1849 | * |
| 1850 | * Disables PCI Memory-Write-Invalidate transaction on the device |
| 1851 | */ |
| 1852 | void |
| 1853 | pci_clear_mwi(struct pci_dev *dev) |
| 1854 | { |
| 1855 | u16 cmd; |
| 1856 | |
| 1857 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 1858 | if (cmd & PCI_COMMAND_INVALIDATE) { |
| 1859 | cmd &= ~PCI_COMMAND_INVALIDATE; |
| 1860 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1861 | } |
| 1862 | } |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 1863 | #endif /* ! PCI_DISABLE_MWI */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1864 | |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1865 | /** |
| 1866 | * pci_intx - enables/disables PCI INTx for device dev |
Randy Dunlap | 8f7020d | 2005-10-23 11:57:38 -0700 | [diff] [blame] | 1867 | * @pdev: the PCI device to operate on |
| 1868 | * @enable: boolean: whether to enable or disable PCI INTx |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1869 | * |
| 1870 | * Enables/disables PCI INTx for device dev |
| 1871 | */ |
| 1872 | void |
| 1873 | pci_intx(struct pci_dev *pdev, int enable) |
| 1874 | { |
| 1875 | u16 pci_command, new; |
| 1876 | |
| 1877 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); |
| 1878 | |
| 1879 | if (enable) { |
| 1880 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
| 1881 | } else { |
| 1882 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
| 1883 | } |
| 1884 | |
| 1885 | if (new != pci_command) { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1886 | struct pci_devres *dr; |
| 1887 | |
Brett M Russ | 2fd9d74 | 2005-09-09 10:02:22 -0700 | [diff] [blame] | 1888 | pci_write_config_word(pdev, PCI_COMMAND, new); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1889 | |
| 1890 | dr = find_pci_dr(pdev); |
| 1891 | if (dr && !dr->restore_intx) { |
| 1892 | dr->restore_intx = 1; |
| 1893 | dr->orig_intx = !enable; |
| 1894 | } |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1895 | } |
| 1896 | } |
| 1897 | |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 1898 | /** |
| 1899 | * pci_msi_off - disables any msi or msix capabilities |
Randy Dunlap | 8d7d86e | 2007-03-16 19:55:52 -0700 | [diff] [blame] | 1900 | * @dev: the PCI device to operate on |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 1901 | * |
| 1902 | * If you want to use msi see pci_enable_msi and friends. |
| 1903 | * This is a lower level primitive that allows us to disable |
| 1904 | * msi operation at the device level. |
| 1905 | */ |
| 1906 | void pci_msi_off(struct pci_dev *dev) |
| 1907 | { |
| 1908 | int pos; |
| 1909 | u16 control; |
| 1910 | |
| 1911 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
| 1912 | if (pos) { |
| 1913 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
| 1914 | control &= ~PCI_MSI_FLAGS_ENABLE; |
| 1915 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
| 1916 | } |
| 1917 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
| 1918 | if (pos) { |
| 1919 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
| 1920 | control &= ~PCI_MSIX_FLAGS_ENABLE; |
| 1921 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
| 1922 | } |
| 1923 | } |
| 1924 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1925 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
| 1926 | /* |
| 1927 | * These can be overridden by arch-specific implementations |
| 1928 | */ |
| 1929 | int |
| 1930 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
| 1931 | { |
| 1932 | if (!pci_dma_supported(dev, mask)) |
| 1933 | return -EIO; |
| 1934 | |
| 1935 | dev->dma_mask = mask; |
| 1936 | |
| 1937 | return 0; |
| 1938 | } |
| 1939 | |
| 1940 | int |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1941 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
| 1942 | { |
| 1943 | if (!pci_dma_supported(dev, mask)) |
| 1944 | return -EIO; |
| 1945 | |
| 1946 | dev->dev.coherent_dma_mask = mask; |
| 1947 | |
| 1948 | return 0; |
| 1949 | } |
| 1950 | #endif |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 1951 | |
FUJITA Tomonori | 4d57cdf | 2008-02-04 22:27:55 -0800 | [diff] [blame] | 1952 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
| 1953 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) |
| 1954 | { |
| 1955 | return dma_set_max_seg_size(&dev->dev, size); |
| 1956 | } |
| 1957 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); |
| 1958 | #endif |
| 1959 | |
FUJITA Tomonori | 59fc67d | 2008-02-04 22:28:14 -0800 | [diff] [blame] | 1960 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
| 1961 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) |
| 1962 | { |
| 1963 | return dma_set_seg_boundary(&dev->dev, mask); |
| 1964 | } |
| 1965 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); |
| 1966 | #endif |
| 1967 | |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 1968 | static int __pcie_flr(struct pci_dev *dev, int probe) |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 1969 | { |
| 1970 | u16 status; |
| 1971 | u32 cap; |
| 1972 | int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 1973 | |
| 1974 | if (!exppos) |
| 1975 | return -ENOTTY; |
| 1976 | pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap); |
| 1977 | if (!(cap & PCI_EXP_DEVCAP_FLR)) |
| 1978 | return -ENOTTY; |
| 1979 | |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 1980 | if (probe) |
| 1981 | return 0; |
| 1982 | |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 1983 | pci_block_user_cfg_access(dev); |
| 1984 | |
| 1985 | /* Wait for Transaction Pending bit clean */ |
| 1986 | msleep(100); |
| 1987 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); |
| 1988 | if (status & PCI_EXP_DEVSTA_TRPND) { |
| 1989 | dev_info(&dev->dev, "Busy after 100ms while trying to reset; " |
| 1990 | "sleeping for 1 second\n"); |
| 1991 | ssleep(1); |
| 1992 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); |
| 1993 | if (status & PCI_EXP_DEVSTA_TRPND) |
| 1994 | dev_info(&dev->dev, "Still busy after 1s; " |
| 1995 | "proceeding with reset anyway\n"); |
| 1996 | } |
| 1997 | |
| 1998 | pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL, |
| 1999 | PCI_EXP_DEVCTL_BCR_FLR); |
| 2000 | mdelay(100); |
| 2001 | |
| 2002 | pci_unblock_user_cfg_access(dev); |
| 2003 | return 0; |
| 2004 | } |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 2005 | |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 2006 | static int __pci_af_flr(struct pci_dev *dev, int probe) |
| 2007 | { |
| 2008 | int cappos = pci_find_capability(dev, PCI_CAP_ID_AF); |
| 2009 | u8 status; |
| 2010 | u8 cap; |
| 2011 | |
| 2012 | if (!cappos) |
| 2013 | return -ENOTTY; |
| 2014 | pci_read_config_byte(dev, cappos + PCI_AF_CAP, &cap); |
| 2015 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
| 2016 | return -ENOTTY; |
| 2017 | |
| 2018 | if (probe) |
| 2019 | return 0; |
| 2020 | |
| 2021 | pci_block_user_cfg_access(dev); |
| 2022 | |
| 2023 | /* Wait for Transaction Pending bit clean */ |
| 2024 | msleep(100); |
| 2025 | pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status); |
| 2026 | if (status & PCI_AF_STATUS_TP) { |
| 2027 | dev_info(&dev->dev, "Busy after 100ms while trying to" |
| 2028 | " reset; sleeping for 1 second\n"); |
| 2029 | ssleep(1); |
| 2030 | pci_read_config_byte(dev, |
| 2031 | cappos + PCI_AF_STATUS, &status); |
| 2032 | if (status & PCI_AF_STATUS_TP) |
| 2033 | dev_info(&dev->dev, "Still busy after 1s; " |
| 2034 | "proceeding with reset anyway\n"); |
| 2035 | } |
| 2036 | pci_write_config_byte(dev, cappos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
| 2037 | mdelay(100); |
| 2038 | |
| 2039 | pci_unblock_user_cfg_access(dev); |
| 2040 | return 0; |
| 2041 | } |
| 2042 | |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 2043 | static int __pci_reset_function(struct pci_dev *pdev, int probe) |
| 2044 | { |
| 2045 | int res; |
| 2046 | |
| 2047 | res = __pcie_flr(pdev, probe); |
| 2048 | if (res != -ENOTTY) |
| 2049 | return res; |
| 2050 | |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 2051 | res = __pci_af_flr(pdev, probe); |
| 2052 | if (res != -ENOTTY) |
| 2053 | return res; |
| 2054 | |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 2055 | return res; |
| 2056 | } |
| 2057 | |
| 2058 | /** |
| 2059 | * pci_execute_reset_function() - Reset a PCI device function |
| 2060 | * @dev: Device function to reset |
| 2061 | * |
| 2062 | * Some devices allow an individual function to be reset without affecting |
| 2063 | * other functions in the same device. The PCI device must be responsive |
| 2064 | * to PCI config space in order to use this function. |
| 2065 | * |
| 2066 | * The device function is presumed to be unused when this function is called. |
| 2067 | * Resetting the device will make the contents of PCI configuration space |
| 2068 | * random, so any caller of this must be prepared to reinitialise the |
| 2069 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, |
| 2070 | * etc. |
| 2071 | * |
| 2072 | * Returns 0 if the device function was successfully reset or -ENOTTY if the |
| 2073 | * device doesn't support resetting a single function. |
| 2074 | */ |
| 2075 | int pci_execute_reset_function(struct pci_dev *dev) |
| 2076 | { |
| 2077 | return __pci_reset_function(dev, 0); |
| 2078 | } |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2079 | EXPORT_SYMBOL_GPL(pci_execute_reset_function); |
| 2080 | |
| 2081 | /** |
| 2082 | * pci_reset_function() - quiesce and reset a PCI device function |
| 2083 | * @dev: Device function to reset |
| 2084 | * |
| 2085 | * Some devices allow an individual function to be reset without affecting |
| 2086 | * other functions in the same device. The PCI device must be responsive |
| 2087 | * to PCI config space in order to use this function. |
| 2088 | * |
| 2089 | * This function does not just reset the PCI portion of a device, but |
| 2090 | * clears all the state associated with the device. This function differs |
| 2091 | * from pci_execute_reset_function in that it saves and restores device state |
| 2092 | * over the reset. |
| 2093 | * |
| 2094 | * Returns 0 if the device function was successfully reset or -ENOTTY if the |
| 2095 | * device doesn't support resetting a single function. |
| 2096 | */ |
| 2097 | int pci_reset_function(struct pci_dev *dev) |
| 2098 | { |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 2099 | int r = __pci_reset_function(dev, 1); |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2100 | |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 2101 | if (r < 0) |
| 2102 | return r; |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2103 | |
Sheng Yang | 1df8fb3 | 2008-11-11 17:17:45 +0800 | [diff] [blame] | 2104 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2105 | disable_irq(dev->irq); |
| 2106 | pci_save_state(dev); |
| 2107 | |
| 2108 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); |
| 2109 | |
| 2110 | r = pci_execute_reset_function(dev); |
| 2111 | |
| 2112 | pci_restore_state(dev); |
Sheng Yang | 1df8fb3 | 2008-11-11 17:17:45 +0800 | [diff] [blame] | 2113 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2114 | enable_irq(dev->irq); |
| 2115 | |
| 2116 | return r; |
| 2117 | } |
| 2118 | EXPORT_SYMBOL_GPL(pci_reset_function); |
| 2119 | |
| 2120 | /** |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 2121 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count |
| 2122 | * @dev: PCI device to query |
| 2123 | * |
| 2124 | * Returns mmrbc: maximum designed memory read count in bytes |
| 2125 | * or appropriate error value. |
| 2126 | */ |
| 2127 | int pcix_get_max_mmrbc(struct pci_dev *dev) |
| 2128 | { |
Andrew Morton | b7b095c | 2007-07-09 11:55:50 -0700 | [diff] [blame] | 2129 | int err, cap; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 2130 | u32 stat; |
| 2131 | |
| 2132 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 2133 | if (!cap) |
| 2134 | return -EINVAL; |
| 2135 | |
| 2136 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); |
| 2137 | if (err) |
| 2138 | return -EINVAL; |
| 2139 | |
Andrew Morton | b7b095c | 2007-07-09 11:55:50 -0700 | [diff] [blame] | 2140 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 2141 | } |
| 2142 | EXPORT_SYMBOL(pcix_get_max_mmrbc); |
| 2143 | |
| 2144 | /** |
| 2145 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count |
| 2146 | * @dev: PCI device to query |
| 2147 | * |
| 2148 | * Returns mmrbc: maximum memory read count in bytes |
| 2149 | * or appropriate error value. |
| 2150 | */ |
| 2151 | int pcix_get_mmrbc(struct pci_dev *dev) |
| 2152 | { |
| 2153 | int ret, cap; |
| 2154 | u32 cmd; |
| 2155 | |
| 2156 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 2157 | if (!cap) |
| 2158 | return -EINVAL; |
| 2159 | |
| 2160 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); |
| 2161 | if (!ret) |
| 2162 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
| 2163 | |
| 2164 | return ret; |
| 2165 | } |
| 2166 | EXPORT_SYMBOL(pcix_get_mmrbc); |
| 2167 | |
| 2168 | /** |
| 2169 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count |
| 2170 | * @dev: PCI device to query |
| 2171 | * @mmrbc: maximum memory read count in bytes |
| 2172 | * valid values are 512, 1024, 2048, 4096 |
| 2173 | * |
| 2174 | * If possible sets maximum memory read byte count, some bridges have erratas |
| 2175 | * that prevent this. |
| 2176 | */ |
| 2177 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) |
| 2178 | { |
| 2179 | int cap, err = -EINVAL; |
| 2180 | u32 stat, cmd, v, o; |
| 2181 | |
vignesh babu | 229f5af | 2007-08-13 18:23:14 +0530 | [diff] [blame] | 2182 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 2183 | goto out; |
| 2184 | |
| 2185 | v = ffs(mmrbc) - 10; |
| 2186 | |
| 2187 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 2188 | if (!cap) |
| 2189 | goto out; |
| 2190 | |
| 2191 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); |
| 2192 | if (err) |
| 2193 | goto out; |
| 2194 | |
| 2195 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) |
| 2196 | return -E2BIG; |
| 2197 | |
| 2198 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); |
| 2199 | if (err) |
| 2200 | goto out; |
| 2201 | |
| 2202 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; |
| 2203 | if (o != v) { |
| 2204 | if (v > o && dev->bus && |
| 2205 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
| 2206 | return -EIO; |
| 2207 | |
| 2208 | cmd &= ~PCI_X_CMD_MAX_READ; |
| 2209 | cmd |= v << 2; |
| 2210 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); |
| 2211 | } |
| 2212 | out: |
| 2213 | return err; |
| 2214 | } |
| 2215 | EXPORT_SYMBOL(pcix_set_mmrbc); |
| 2216 | |
| 2217 | /** |
| 2218 | * pcie_get_readrq - get PCI Express read request size |
| 2219 | * @dev: PCI device to query |
| 2220 | * |
| 2221 | * Returns maximum memory read request in bytes |
| 2222 | * or appropriate error value. |
| 2223 | */ |
| 2224 | int pcie_get_readrq(struct pci_dev *dev) |
| 2225 | { |
| 2226 | int ret, cap; |
| 2227 | u16 ctl; |
| 2228 | |
| 2229 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 2230 | if (!cap) |
| 2231 | return -EINVAL; |
| 2232 | |
| 2233 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); |
| 2234 | if (!ret) |
| 2235 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
| 2236 | |
| 2237 | return ret; |
| 2238 | } |
| 2239 | EXPORT_SYMBOL(pcie_get_readrq); |
| 2240 | |
| 2241 | /** |
| 2242 | * pcie_set_readrq - set PCI Express maximum memory read request |
| 2243 | * @dev: PCI device to query |
Randy Dunlap | 42e61f4 | 2007-07-23 21:42:11 -0700 | [diff] [blame] | 2244 | * @rq: maximum memory read count in bytes |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 2245 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
| 2246 | * |
| 2247 | * If possible sets maximum read byte count |
| 2248 | */ |
| 2249 | int pcie_set_readrq(struct pci_dev *dev, int rq) |
| 2250 | { |
| 2251 | int cap, err = -EINVAL; |
| 2252 | u16 ctl, v; |
| 2253 | |
vignesh babu | 229f5af | 2007-08-13 18:23:14 +0530 | [diff] [blame] | 2254 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 2255 | goto out; |
| 2256 | |
| 2257 | v = (ffs(rq) - 8) << 12; |
| 2258 | |
| 2259 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 2260 | if (!cap) |
| 2261 | goto out; |
| 2262 | |
| 2263 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); |
| 2264 | if (err) |
| 2265 | goto out; |
| 2266 | |
| 2267 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { |
| 2268 | ctl &= ~PCI_EXP_DEVCTL_READRQ; |
| 2269 | ctl |= v; |
| 2270 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); |
| 2271 | } |
| 2272 | |
| 2273 | out: |
| 2274 | return err; |
| 2275 | } |
| 2276 | EXPORT_SYMBOL(pcie_set_readrq); |
| 2277 | |
| 2278 | /** |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2279 | * pci_select_bars - Make BAR mask from the type of resource |
Randy Dunlap | f95d882 | 2007-02-10 14:41:56 -0800 | [diff] [blame] | 2280 | * @dev: the PCI device for which BAR mask is made |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2281 | * @flags: resource type mask to be selected |
| 2282 | * |
| 2283 | * This helper routine makes bar mask from the type of resource. |
| 2284 | */ |
| 2285 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) |
| 2286 | { |
| 2287 | int i, bars = 0; |
| 2288 | for (i = 0; i < PCI_NUM_RESOURCES; i++) |
| 2289 | if (pci_resource_flags(dev, i) & flags) |
| 2290 | bars |= (1 << i); |
| 2291 | return bars; |
| 2292 | } |
| 2293 | |
Yu Zhao | 613e7ed | 2008-11-22 02:41:27 +0800 | [diff] [blame] | 2294 | /** |
| 2295 | * pci_resource_bar - get position of the BAR associated with a resource |
| 2296 | * @dev: the PCI device |
| 2297 | * @resno: the resource number |
| 2298 | * @type: the BAR type to be filled in |
| 2299 | * |
| 2300 | * Returns BAR position in config space, or 0 if the BAR is invalid. |
| 2301 | */ |
| 2302 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) |
| 2303 | { |
| 2304 | if (resno < PCI_ROM_RESOURCE) { |
| 2305 | *type = pci_bar_unknown; |
| 2306 | return PCI_BASE_ADDRESS_0 + 4 * resno; |
| 2307 | } else if (resno == PCI_ROM_RESOURCE) { |
| 2308 | *type = pci_bar_mem32; |
| 2309 | return dev->rom_base_reg; |
| 2310 | } |
| 2311 | |
| 2312 | dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno); |
| 2313 | return 0; |
| 2314 | } |
| 2315 | |
Jeff Garzik | 32a2eea | 2007-10-11 16:57:27 -0400 | [diff] [blame] | 2316 | static void __devinit pci_no_domains(void) |
| 2317 | { |
| 2318 | #ifdef CONFIG_PCI_DOMAINS |
| 2319 | pci_domains_supported = 0; |
| 2320 | #endif |
| 2321 | } |
| 2322 | |
Andrew Patterson | 0ef5f8f | 2008-11-10 15:30:50 -0700 | [diff] [blame] | 2323 | /** |
| 2324 | * pci_ext_cfg_enabled - can we access extended PCI config space? |
| 2325 | * @dev: The PCI device of the root bridge. |
| 2326 | * |
| 2327 | * Returns 1 if we can access PCI extended config space (offsets |
| 2328 | * greater than 0xff). This is the default implementation. Architecture |
| 2329 | * implementations can override this. |
| 2330 | */ |
| 2331 | int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) |
| 2332 | { |
| 2333 | return 1; |
| 2334 | } |
| 2335 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2336 | static int __devinit pci_init(void) |
| 2337 | { |
| 2338 | struct pci_dev *dev = NULL; |
| 2339 | |
| 2340 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { |
| 2341 | pci_fixup_device(pci_fixup_final, dev); |
| 2342 | } |
Taku Izumi | d389fec | 2008-10-17 13:52:51 +0900 | [diff] [blame] | 2343 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2344 | return 0; |
| 2345 | } |
| 2346 | |
Al Viro | ad04d31 | 2008-11-22 17:37:14 +0000 | [diff] [blame] | 2347 | static int __init pci_setup(char *str) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2348 | { |
| 2349 | while (str) { |
| 2350 | char *k = strchr(str, ','); |
| 2351 | if (k) |
| 2352 | *k++ = 0; |
| 2353 | if (*str && (str = pcibios_setup(str)) && *str) { |
Matthew Wilcox | 309e57d | 2006-03-05 22:33:34 -0700 | [diff] [blame] | 2354 | if (!strcmp(str, "nomsi")) { |
| 2355 | pci_no_msi(); |
Randy Dunlap | 7f78576 | 2007-10-05 13:17:58 -0700 | [diff] [blame] | 2356 | } else if (!strcmp(str, "noaer")) { |
| 2357 | pci_no_aer(); |
Jeff Garzik | 32a2eea | 2007-10-11 16:57:27 -0400 | [diff] [blame] | 2358 | } else if (!strcmp(str, "nodomains")) { |
| 2359 | pci_no_domains(); |
Atsushi Nemoto | 4516a61 | 2007-02-05 16:36:06 -0800 | [diff] [blame] | 2360 | } else if (!strncmp(str, "cbiosize=", 9)) { |
| 2361 | pci_cardbus_io_size = memparse(str + 9, &str); |
| 2362 | } else if (!strncmp(str, "cbmemsize=", 10)) { |
| 2363 | pci_cardbus_mem_size = memparse(str + 10, &str); |
Matthew Wilcox | 309e57d | 2006-03-05 22:33:34 -0700 | [diff] [blame] | 2364 | } else { |
| 2365 | printk(KERN_ERR "PCI: Unknown option `%s'\n", |
| 2366 | str); |
| 2367 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2368 | } |
| 2369 | str = k; |
| 2370 | } |
Andi Kleen | 0637a70 | 2006-09-26 10:52:41 +0200 | [diff] [blame] | 2371 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2372 | } |
Andi Kleen | 0637a70 | 2006-09-26 10:52:41 +0200 | [diff] [blame] | 2373 | early_param("pci", pci_setup); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2374 | |
| 2375 | device_initcall(pci_init); |
| 2376 | |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 2377 | EXPORT_SYMBOL(pci_reenable_device); |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 2378 | EXPORT_SYMBOL(pci_enable_device_io); |
| 2379 | EXPORT_SYMBOL(pci_enable_device_mem); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2380 | EXPORT_SYMBOL(pci_enable_device); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 2381 | EXPORT_SYMBOL(pcim_enable_device); |
| 2382 | EXPORT_SYMBOL(pcim_pin_device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2383 | EXPORT_SYMBOL(pci_disable_device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2384 | EXPORT_SYMBOL(pci_find_capability); |
| 2385 | EXPORT_SYMBOL(pci_bus_find_capability); |
| 2386 | EXPORT_SYMBOL(pci_release_regions); |
| 2387 | EXPORT_SYMBOL(pci_request_regions); |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2388 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2389 | EXPORT_SYMBOL(pci_release_region); |
| 2390 | EXPORT_SYMBOL(pci_request_region); |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2391 | EXPORT_SYMBOL(pci_request_region_exclusive); |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2392 | EXPORT_SYMBOL(pci_release_selected_regions); |
| 2393 | EXPORT_SYMBOL(pci_request_selected_regions); |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2394 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2395 | EXPORT_SYMBOL(pci_set_master); |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 2396 | EXPORT_SYMBOL(pci_clear_master); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2397 | EXPORT_SYMBOL(pci_set_mwi); |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 2398 | EXPORT_SYMBOL(pci_try_set_mwi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2399 | EXPORT_SYMBOL(pci_clear_mwi); |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 2400 | EXPORT_SYMBOL_GPL(pci_intx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2401 | EXPORT_SYMBOL(pci_set_dma_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2402 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
| 2403 | EXPORT_SYMBOL(pci_assign_resource); |
| 2404 | EXPORT_SYMBOL(pci_find_parent_resource); |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2405 | EXPORT_SYMBOL(pci_select_bars); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2406 | |
| 2407 | EXPORT_SYMBOL(pci_set_power_state); |
| 2408 | EXPORT_SYMBOL(pci_save_state); |
| 2409 | EXPORT_SYMBOL(pci_restore_state); |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 2410 | EXPORT_SYMBOL(pci_pme_capable); |
Rafael J. Wysocki | 5a6c9b6 | 2008-08-08 00:14:24 +0200 | [diff] [blame] | 2411 | EXPORT_SYMBOL(pci_pme_active); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2412 | EXPORT_SYMBOL(pci_enable_wake); |
Rafael J. Wysocki | 0235c4f | 2008-08-18 21:38:00 +0200 | [diff] [blame] | 2413 | EXPORT_SYMBOL(pci_wake_from_d3); |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 2414 | EXPORT_SYMBOL(pci_target_state); |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 2415 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
| 2416 | EXPORT_SYMBOL(pci_back_from_sleep); |
Brian King | f7bdd12 | 2007-04-06 16:39:36 -0500 | [diff] [blame] | 2417 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2418 | |