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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
David Brownell075c1772007-04-26 00:12:06 -070014#include <linux/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/module.h>
16#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080017#include <linux/string.h>
vignesh babu229f5af2007-08-13 18:23:14 +053018#include <linux/log2.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080019#include <linux/pci-aspm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090021#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070022
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -070023unsigned int pci_pm_d3_delay = 10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070024
Jeff Garzik32a2eea2007-10-11 16:57:27 -040025#ifdef CONFIG_PCI_DOMAINS
26int pci_domains_supported = 1;
27#endif
28
Atsushi Nemoto4516a612007-02-05 16:36:06 -080029#define DEFAULT_CARDBUS_IO_SIZE (256)
30#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
31/* pci=cbmemsize=nnM,cbiosize=nn can override this */
32unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
33unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
34
Linus Torvalds1da177e2005-04-16 15:20:36 -070035/**
36 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
37 * @bus: pointer to PCI bus structure to search
38 *
39 * Given a PCI bus, returns the highest PCI bus number present in the set
40 * including the given PCI bus and its list of child PCI buses.
41 */
Sam Ravnborg96bde062007-03-26 21:53:30 -080042unsigned char pci_bus_max_busnr(struct pci_bus* bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070043{
44 struct list_head *tmp;
45 unsigned char max, n;
46
Kristen Accardib82db5c2006-01-17 16:56:56 -080047 max = bus->subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -070048 list_for_each(tmp, &bus->children) {
49 n = pci_bus_max_busnr(pci_bus_b(tmp));
50 if(n > max)
51 max = n;
52 }
53 return max;
54}
Kristen Accardib82db5c2006-01-17 16:56:56 -080055EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Kristen Accardib82db5c2006-01-17 16:56:56 -080057#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070058/**
59 * pci_max_busnr - returns maximum PCI bus number
60 *
61 * Returns the highest PCI bus number present in the system global list of
62 * PCI buses.
63 */
64unsigned char __devinit
65pci_max_busnr(void)
66{
67 struct pci_bus *bus = NULL;
68 unsigned char max, n;
69
70 max = 0;
71 while ((bus = pci_find_next_bus(bus)) != NULL) {
72 n = pci_bus_max_busnr(bus);
73 if(n > max)
74 max = n;
75 }
76 return max;
77}
78
Adrian Bunk54c762f2005-12-22 01:08:52 +010079#endif /* 0 */
80
Michael Ellerman687d5fe2006-11-22 18:26:18 +110081#define PCI_FIND_CAP_TTL 48
82
83static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
84 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -070085{
86 u8 id;
Roland Dreier24a4e372005-10-28 17:35:34 -070087
Michael Ellerman687d5fe2006-11-22 18:26:18 +110088 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -070089 pci_bus_read_config_byte(bus, devfn, pos, &pos);
90 if (pos < 0x40)
91 break;
92 pos &= ~3;
93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
94 &id);
95 if (id == 0xff)
96 break;
97 if (id == cap)
98 return pos;
99 pos += PCI_CAP_LIST_NEXT;
100 }
101 return 0;
102}
103
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100104static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
105 u8 pos, int cap)
106{
107 int ttl = PCI_FIND_CAP_TTL;
108
109 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
110}
111
Roland Dreier24a4e372005-10-28 17:35:34 -0700112int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
113{
114 return __pci_find_next_cap(dev->bus, dev->devfn,
115 pos + PCI_CAP_LIST_NEXT, cap);
116}
117EXPORT_SYMBOL_GPL(pci_find_next_capability);
118
Michael Ellermand3bac112006-11-22 18:26:16 +1100119static int __pci_bus_find_cap_start(struct pci_bus *bus,
120 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121{
122 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
124 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
125 if (!(status & PCI_STATUS_CAP_LIST))
126 return 0;
127
128 switch (hdr_type) {
129 case PCI_HEADER_TYPE_NORMAL:
130 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100131 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100133 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134 default:
135 return 0;
136 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100137
138 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139}
140
141/**
142 * pci_find_capability - query for devices' capabilities
143 * @dev: PCI device to query
144 * @cap: capability code
145 *
146 * Tell if a device supports a given PCI capability.
147 * Returns the address of the requested capability structure within the
148 * device's PCI configuration space or 0 in case the device does not
149 * support it. Possible values for @cap:
150 *
151 * %PCI_CAP_ID_PM Power Management
152 * %PCI_CAP_ID_AGP Accelerated Graphics Port
153 * %PCI_CAP_ID_VPD Vital Product Data
154 * %PCI_CAP_ID_SLOTID Slot Identification
155 * %PCI_CAP_ID_MSI Message Signalled Interrupts
156 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
157 * %PCI_CAP_ID_PCIX PCI-X
158 * %PCI_CAP_ID_EXP PCI Express
159 */
160int pci_find_capability(struct pci_dev *dev, int cap)
161{
Michael Ellermand3bac112006-11-22 18:26:16 +1100162 int pos;
163
164 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
165 if (pos)
166 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
167
168 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169}
170
171/**
172 * pci_bus_find_capability - query for devices' capabilities
173 * @bus: the PCI bus to query
174 * @devfn: PCI device to query
175 * @cap: capability code
176 *
177 * Like pci_find_capability() but works for pci devices that do not have a
178 * pci_dev structure set up yet.
179 *
180 * Returns the address of the requested capability structure within the
181 * device's PCI configuration space or 0 in case the device does not
182 * support it.
183 */
184int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
185{
Michael Ellermand3bac112006-11-22 18:26:16 +1100186 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187 u8 hdr_type;
188
189 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
190
Michael Ellermand3bac112006-11-22 18:26:16 +1100191 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
192 if (pos)
193 pos = __pci_find_next_cap(bus, devfn, pos, cap);
194
195 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196}
197
198/**
199 * pci_find_ext_capability - Find an extended capability
200 * @dev: PCI device to query
201 * @cap: capability code
202 *
203 * Returns the address of the requested extended capability structure
204 * within the device's PCI configuration space or 0 if the device does
205 * not support it. Possible values for @cap:
206 *
207 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
208 * %PCI_EXT_CAP_ID_VC Virtual Channel
209 * %PCI_EXT_CAP_ID_DSN Device Serial Number
210 * %PCI_EXT_CAP_ID_PWR Power Budgeting
211 */
212int pci_find_ext_capability(struct pci_dev *dev, int cap)
213{
214 u32 header;
215 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
216 int pos = 0x100;
217
218 if (dev->cfg_size <= 256)
219 return 0;
220
221 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
222 return 0;
223
224 /*
225 * If we have no capabilities, this is indicated by cap ID,
226 * cap version and next pointer all being 0.
227 */
228 if (header == 0)
229 return 0;
230
231 while (ttl-- > 0) {
232 if (PCI_EXT_CAP_ID(header) == cap)
233 return pos;
234
235 pos = PCI_EXT_CAP_NEXT(header);
236 if (pos < 0x100)
237 break;
238
239 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
240 break;
241 }
242
243 return 0;
244}
Brice Goglin3a720d72006-05-23 06:10:01 -0400245EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100247static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
248{
249 int rc, ttl = PCI_FIND_CAP_TTL;
250 u8 cap, mask;
251
252 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
253 mask = HT_3BIT_CAP_MASK;
254 else
255 mask = HT_5BIT_CAP_MASK;
256
257 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
258 PCI_CAP_ID_HT, &ttl);
259 while (pos) {
260 rc = pci_read_config_byte(dev, pos + 3, &cap);
261 if (rc != PCIBIOS_SUCCESSFUL)
262 return 0;
263
264 if ((cap & mask) == ht_cap)
265 return pos;
266
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800267 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
268 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100269 PCI_CAP_ID_HT, &ttl);
270 }
271
272 return 0;
273}
274/**
275 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
276 * @dev: PCI device to query
277 * @pos: Position from which to continue searching
278 * @ht_cap: Hypertransport capability code
279 *
280 * To be used in conjunction with pci_find_ht_capability() to search for
281 * all capabilities matching @ht_cap. @pos should always be a value returned
282 * from pci_find_ht_capability().
283 *
284 * NB. To be 100% safe against broken PCI devices, the caller should take
285 * steps to avoid an infinite loop.
286 */
287int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
288{
289 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
290}
291EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
292
293/**
294 * pci_find_ht_capability - query a device's Hypertransport capabilities
295 * @dev: PCI device to query
296 * @ht_cap: Hypertransport capability code
297 *
298 * Tell if a device supports a given Hypertransport capability.
299 * Returns an address within the device's PCI configuration space
300 * or 0 in case the device does not support the request capability.
301 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
302 * which has a Hypertransport capability matching @ht_cap.
303 */
304int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
305{
306 int pos;
307
308 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
309 if (pos)
310 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
311
312 return pos;
313}
314EXPORT_SYMBOL_GPL(pci_find_ht_capability);
315
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316/**
317 * pci_find_parent_resource - return resource region of parent bus of given region
318 * @dev: PCI device structure contains resources to be searched
319 * @res: child resource record for which parent is sought
320 *
321 * For given resource region of given device, return the resource
322 * region of parent bus the given region is contained in or where
323 * it should be allocated from.
324 */
325struct resource *
326pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
327{
328 const struct pci_bus *bus = dev->bus;
329 int i;
330 struct resource *best = NULL;
331
332 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
333 struct resource *r = bus->resource[i];
334 if (!r)
335 continue;
336 if (res->start && !(res->start >= r->start && res->end <= r->end))
337 continue; /* Not contained */
338 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
339 continue; /* Wrong type */
340 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
341 return r; /* Exact match */
342 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
343 best = r; /* Approximating prefetchable by non-prefetchable */
344 }
345 return best;
346}
347
348/**
John W. Linville064b53db2005-07-27 10:19:44 -0400349 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
350 * @dev: PCI device to have its BARs restored
351 *
352 * Restore the BAR values for a given device, so as to make it
353 * accessible by its driver.
354 */
Adrian Bunkad6685992007-10-27 03:06:22 +0200355static void
John W. Linville064b53db2005-07-27 10:19:44 -0400356pci_restore_bars(struct pci_dev *dev)
357{
358 int i, numres;
359
360 switch (dev->hdr_type) {
361 case PCI_HEADER_TYPE_NORMAL:
362 numres = 6;
363 break;
364 case PCI_HEADER_TYPE_BRIDGE:
365 numres = 2;
366 break;
367 case PCI_HEADER_TYPE_CARDBUS:
368 numres = 1;
369 break;
370 default:
371 /* Should never get here, but just in case... */
372 return;
373 }
374
375 for (i = 0; i < numres; i ++)
376 pci_update_resource(dev, &dev->resource[i], i);
377}
378
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200379static struct pci_platform_pm_ops *pci_platform_pm;
380
381int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
382{
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200383 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
384 || !ops->sleep_wake || !ops->can_wakeup)
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200385 return -EINVAL;
386 pci_platform_pm = ops;
387 return 0;
388}
389
390static inline bool platform_pci_power_manageable(struct pci_dev *dev)
391{
392 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
393}
394
395static inline int platform_pci_set_power_state(struct pci_dev *dev,
396 pci_power_t t)
397{
398 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
399}
400
401static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
402{
403 return pci_platform_pm ?
404 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
405}
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700406
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200407static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
408{
409 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
410}
411
412static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
413{
414 return pci_platform_pm ?
415 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
416}
417
John W. Linville064b53db2005-07-27 10:19:44 -0400418/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200419 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
420 * given PCI device
421 * @dev: PCI device to handle.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200422 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 *
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200424 * RETURN VALUE:
425 * -EINVAL if the requested state is invalid.
426 * -EIO if device does not support PCI PM or its PM capabilities register has a
427 * wrong version, or device doesn't support the requested state.
428 * 0 if device already is in the requested state.
429 * 0 if device's power state has been successfully changed.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 */
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200431static int
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200432pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200434 u16 pmcsr;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200435 bool need_restore = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200437 if (!dev->pm_cap)
Andrew Lunncca03de2007-07-09 11:55:58 -0700438 return -EIO;
439
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200440 if (state < PCI_D0 || state > PCI_D3hot)
441 return -EINVAL;
442
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 /* Validate current state:
444 * Can enter D0 from any state, but if we can only go deeper
445 * to sleep if we're already in a low power state
446 */
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200447 if (dev->current_state == state) {
448 /* we're already there */
449 return 0;
450 } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold
451 && dev->current_state > state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600452 dev_err(&dev->dev, "invalid power transition "
453 "(from state %d to %d)\n", dev->current_state, state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 return -EINVAL;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200455 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 /* check if this device supports the desired state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200458 if ((state == PCI_D1 && !dev->d1_support)
459 || (state == PCI_D2 && !dev->d2_support))
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700460 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200462 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
John W. Linville064b53db2005-07-27 10:19:44 -0400463
John W. Linville32a36582005-09-14 09:52:42 -0400464 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465 * This doesn't affect PME_Status, disables PME_En, and
466 * sets PowerState to 0.
467 */
John W. Linville32a36582005-09-14 09:52:42 -0400468 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400469 case PCI_D0:
470 case PCI_D1:
471 case PCI_D2:
472 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
473 pmcsr |= state;
474 break;
John W. Linville32a36582005-09-14 09:52:42 -0400475 case PCI_UNKNOWN: /* Boot-up */
476 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
477 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200478 need_restore = true;
John W. Linville32a36582005-09-14 09:52:42 -0400479 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400480 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400481 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400482 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483 }
484
485 /* enter specified state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200486 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487
488 /* Mandatory power management transition delays */
489 /* see PCI PM 1.1 5.6.1 table 18 */
490 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700491 msleep(pci_pm_d3_delay);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492 else if (state == PCI_D2 || dev->current_state == PCI_D2)
493 udelay(200);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494
David Shaohua Lib9131002005-03-19 00:16:18 -0500495 dev->current_state = state;
John W. Linville064b53db2005-07-27 10:19:44 -0400496
497 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
498 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
499 * from D3hot to D0 _may_ perform an internal reset, thereby
500 * going to "D0 Uninitialized" rather than "D0 Initialized".
501 * For example, at least some versions of the 3c905B and the
502 * 3c556B exhibit this behaviour.
503 *
504 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
505 * devices in a D3hot state at boot. Consequently, we need to
506 * restore at least the BARs so that the device will be
507 * accessible to its driver.
508 */
509 if (need_restore)
510 pci_restore_bars(dev);
511
Shaohua Li7d715a62008-02-25 09:46:41 +0800512 if (dev->bus->self)
513 pcie_aspm_pm_state_change(dev->bus->self);
514
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 return 0;
516}
517
518/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200519 * pci_update_current_state - Read PCI power state of given device from its
520 * PCI PM registers and cache it
521 * @dev: PCI device to handle.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200522 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200523static void pci_update_current_state(struct pci_dev *dev)
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200524{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200525 if (dev->pm_cap) {
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200526 u16 pmcsr;
527
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200528 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200529 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
530 }
531}
532
533/**
534 * pci_set_power_state - Set the power state of a PCI device
535 * @dev: PCI device to handle.
536 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
537 *
538 * Transition a device to a new power state, using the platform formware and/or
539 * the device's PCI PM registers.
540 *
541 * RETURN VALUE:
542 * -EINVAL if the requested state is invalid.
543 * -EIO if device does not support PCI PM or its PM capabilities register has a
544 * wrong version, or device doesn't support the requested state.
545 * 0 if device already is in the requested state.
546 * 0 if device's power state has been successfully changed.
547 */
548int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
549{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200550 int error;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200551
552 /* bound the state we're entering */
553 if (state > PCI_D3hot)
554 state = PCI_D3hot;
555 else if (state < PCI_D0)
556 state = PCI_D0;
557 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
558 /*
559 * If the device or the parent bridge do not support PCI PM,
560 * ignore the request if we're doing anything other than putting
561 * it into D0 (which would only happen on boot).
562 */
563 return 0;
564
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200565 if (state == PCI_D0 && platform_pci_power_manageable(dev)) {
566 /*
567 * Allow the platform to change the state, for example via ACPI
568 * _PR0, _PS0 and some such, but do not trust it.
569 */
570 int ret = platform_pci_set_power_state(dev, PCI_D0);
571 if (!ret)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200572 pci_update_current_state(dev);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200573 }
574
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200575 error = pci_raw_set_power_state(dev, state);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200576
577 if (state > PCI_D0 && platform_pci_power_manageable(dev)) {
578 /* Allow the platform to finalize the transition */
579 int ret = platform_pci_set_power_state(dev, state);
580 if (!ret) {
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200581 pci_update_current_state(dev);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200582 error = 0;
583 }
584 }
585
586 return error;
587}
588
589/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590 * pci_choose_state - Choose the power state of a PCI device
591 * @dev: PCI device to be suspended
592 * @state: target sleep state for the whole system. This is the value
593 * that is passed to suspend() function.
594 *
595 * Returns PCI power state suitable for given device and given system
596 * message.
597 */
598
599pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
600{
Shaohua Liab826ca2007-07-20 10:03:22 +0800601 pci_power_t ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500602
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
604 return PCI_D0;
605
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200606 ret = platform_pci_choose_state(dev);
607 if (ret != PCI_POWER_ERROR)
608 return ret;
Pavel Machekca078ba2005-09-03 15:56:57 -0700609
610 switch (state.event) {
611 case PM_EVENT_ON:
612 return PCI_D0;
613 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700614 case PM_EVENT_PRETHAW:
615 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700616 case PM_EVENT_SUSPEND:
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100617 case PM_EVENT_HIBERNATE:
Pavel Machekca078ba2005-09-03 15:56:57 -0700618 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600620 dev_info(&dev->dev, "unrecognized suspend event %d\n",
621 state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622 BUG();
623 }
624 return PCI_D0;
625}
626
627EXPORT_SYMBOL(pci_choose_state);
628
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300629static int pci_save_pcie_state(struct pci_dev *dev)
630{
631 int pos, i = 0;
632 struct pci_cap_saved_state *save_state;
633 u16 *cap;
Shaohua Li017fc482007-12-18 09:57:09 +0800634 int found = 0;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300635
636 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
637 if (pos <= 0)
638 return 0;
639
Eric W. Biederman9f355752007-03-08 13:06:13 -0700640 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
641 if (!save_state)
642 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
Shaohua Li017fc482007-12-18 09:57:09 +0800643 else
644 found = 1;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300645 if (!save_state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600646 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300647 return -ENOMEM;
648 }
649 cap = (u16 *)&save_state->data[0];
650
651 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
652 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
653 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
654 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
Shaohua Liec0a3a22007-12-18 09:56:56 +0800655 save_state->cap_nr = PCI_CAP_ID_EXP;
Shaohua Li017fc482007-12-18 09:57:09 +0800656 if (!found)
657 pci_add_saved_cap(dev, save_state);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300658 return 0;
659}
660
661static void pci_restore_pcie_state(struct pci_dev *dev)
662{
663 int i = 0, pos;
664 struct pci_cap_saved_state *save_state;
665 u16 *cap;
666
667 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
668 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
669 if (!save_state || pos <= 0)
670 return;
671 cap = (u16 *)&save_state->data[0];
672
673 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
674 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
675 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
676 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300677}
678
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800679
680static int pci_save_pcix_state(struct pci_dev *dev)
681{
682 int pos, i = 0;
683 struct pci_cap_saved_state *save_state;
684 u16 *cap;
Shaohua Li017fc482007-12-18 09:57:09 +0800685 int found = 0;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800686
687 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
688 if (pos <= 0)
689 return 0;
690
Shaohua Lif34303d2007-12-18 09:56:47 +0800691 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
Eric W. Biederman9f355752007-03-08 13:06:13 -0700692 if (!save_state)
693 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
Shaohua Li017fc482007-12-18 09:57:09 +0800694 else
695 found = 1;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800696 if (!save_state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600697 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800698 return -ENOMEM;
699 }
700 cap = (u16 *)&save_state->data[0];
701
702 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
Shaohua Liec0a3a22007-12-18 09:56:56 +0800703 save_state->cap_nr = PCI_CAP_ID_PCIX;
Shaohua Li017fc482007-12-18 09:57:09 +0800704 if (!found)
705 pci_add_saved_cap(dev, save_state);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800706 return 0;
707}
708
709static void pci_restore_pcix_state(struct pci_dev *dev)
710{
711 int i = 0, pos;
712 struct pci_cap_saved_state *save_state;
713 u16 *cap;
714
715 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
716 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
717 if (!save_state || pos <= 0)
718 return;
719 cap = (u16 *)&save_state->data[0];
720
721 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800722}
723
724
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725/**
726 * pci_save_state - save the PCI configuration space of a device before suspending
727 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728 */
729int
730pci_save_state(struct pci_dev *dev)
731{
732 int i;
733 /* XXX: 100% dword access ok here? */
734 for (i = 0; i < 16; i++)
735 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300736 if ((i = pci_save_pcie_state(dev)) != 0)
737 return i;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800738 if ((i = pci_save_pcix_state(dev)) != 0)
739 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700740 return 0;
741}
742
743/**
744 * pci_restore_state - Restore the saved state of a PCI device
745 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746 */
747int
748pci_restore_state(struct pci_dev *dev)
749{
750 int i;
Al Virob4482a42007-10-14 19:35:40 +0100751 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300753 /* PCI Express register must be restored first */
754 pci_restore_pcie_state(dev);
755
Yu, Luming8b8c8d22006-04-25 00:00:34 -0700756 /*
757 * The Base Address register should be programmed before the command
758 * register(s)
759 */
760 for (i = 15; i >= 0; i--) {
Dave Jones04d9c1a2006-04-18 21:06:51 -0700761 pci_read_config_dword(dev, i * 4, &val);
762 if (val != dev->saved_config_space[i]) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600763 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
764 "space at offset %#x (was %#x, writing %#x)\n",
765 i, val, (int)dev->saved_config_space[i]);
Dave Jones04d9c1a2006-04-18 21:06:51 -0700766 pci_write_config_dword(dev,i * 4,
767 dev->saved_config_space[i]);
768 }
769 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800770 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +0800771 pci_restore_msi_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +1100772
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773 return 0;
774}
775
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900776static int do_pci_enable_device(struct pci_dev *dev, int bars)
777{
778 int err;
779
780 err = pci_set_power_state(dev, PCI_D0);
781 if (err < 0 && err != -EIO)
782 return err;
783 err = pcibios_enable_device(dev, bars);
784 if (err < 0)
785 return err;
786 pci_fixup_device(pci_fixup_enable, dev);
787
788 return 0;
789}
790
791/**
Tejun Heo0b62e132007-07-27 14:43:35 +0900792 * pci_reenable_device - Resume abandoned device
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900793 * @dev: PCI device to be resumed
794 *
795 * Note this function is a backend of pci_default_resume and is not supposed
796 * to be called by normal code, write proper resume handler and use it instead.
797 */
Tejun Heo0b62e132007-07-27 14:43:35 +0900798int pci_reenable_device(struct pci_dev *dev)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900799{
800 if (atomic_read(&dev->enable_cnt))
801 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
802 return 0;
803}
804
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100805static int __pci_enable_device_flags(struct pci_dev *dev,
806 resource_size_t flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807{
808 int err;
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100809 int i, bars = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900811 if (atomic_add_return(1, &dev->enable_cnt) > 1)
812 return 0; /* already enabled */
813
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100814 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
815 if (dev->resource[i].flags & flags)
816 bars |= (1 << i);
817
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900818 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -0700819 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900820 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900821 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822}
823
824/**
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100825 * pci_enable_device_io - Initialize a device for use with IO space
826 * @dev: PCI device to be initialized
827 *
828 * Initialize device before it's used by a driver. Ask low-level code
829 * to enable I/O resources. Wake up the device if it was suspended.
830 * Beware, this function can fail.
831 */
832int pci_enable_device_io(struct pci_dev *dev)
833{
834 return __pci_enable_device_flags(dev, IORESOURCE_IO);
835}
836
837/**
838 * pci_enable_device_mem - Initialize a device for use with Memory space
839 * @dev: PCI device to be initialized
840 *
841 * Initialize device before it's used by a driver. Ask low-level code
842 * to enable Memory resources. Wake up the device if it was suspended.
843 * Beware, this function can fail.
844 */
845int pci_enable_device_mem(struct pci_dev *dev)
846{
847 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
848}
849
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850/**
851 * pci_enable_device - Initialize device before it's used by a driver.
852 * @dev: PCI device to be initialized
853 *
854 * Initialize device before it's used by a driver. Ask low-level code
855 * to enable I/O and memory. Wake up the device if it was suspended.
856 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800857 *
858 * Note we don't actually enable the device many times if we call
859 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800861int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862{
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100863 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864}
865
Tejun Heo9ac78492007-01-20 16:00:26 +0900866/*
867 * Managed PCI resources. This manages device on/off, intx/msi/msix
868 * on/off and BAR regions. pci_dev itself records msi/msix status, so
869 * there's no need to track it separately. pci_devres is initialized
870 * when a device is enabled using managed PCI device enable interface.
871 */
872struct pci_devres {
Tejun Heo7f375f32007-02-25 04:36:01 -0800873 unsigned int enabled:1;
874 unsigned int pinned:1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900875 unsigned int orig_intx:1;
876 unsigned int restore_intx:1;
877 u32 region_mask;
878};
879
880static void pcim_release(struct device *gendev, void *res)
881{
882 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
883 struct pci_devres *this = res;
884 int i;
885
886 if (dev->msi_enabled)
887 pci_disable_msi(dev);
888 if (dev->msix_enabled)
889 pci_disable_msix(dev);
890
891 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
892 if (this->region_mask & (1 << i))
893 pci_release_region(dev, i);
894
895 if (this->restore_intx)
896 pci_intx(dev, this->orig_intx);
897
Tejun Heo7f375f32007-02-25 04:36:01 -0800898 if (this->enabled && !this->pinned)
Tejun Heo9ac78492007-01-20 16:00:26 +0900899 pci_disable_device(dev);
900}
901
902static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
903{
904 struct pci_devres *dr, *new_dr;
905
906 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
907 if (dr)
908 return dr;
909
910 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
911 if (!new_dr)
912 return NULL;
913 return devres_get(&pdev->dev, new_dr, NULL, NULL);
914}
915
916static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
917{
918 if (pci_is_managed(pdev))
919 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
920 return NULL;
921}
922
923/**
924 * pcim_enable_device - Managed pci_enable_device()
925 * @pdev: PCI device to be initialized
926 *
927 * Managed pci_enable_device().
928 */
929int pcim_enable_device(struct pci_dev *pdev)
930{
931 struct pci_devres *dr;
932 int rc;
933
934 dr = get_pci_dr(pdev);
935 if (unlikely(!dr))
936 return -ENOMEM;
Tejun Heob95d58e2008-01-30 18:20:04 +0900937 if (dr->enabled)
938 return 0;
Tejun Heo9ac78492007-01-20 16:00:26 +0900939
940 rc = pci_enable_device(pdev);
941 if (!rc) {
942 pdev->is_managed = 1;
Tejun Heo7f375f32007-02-25 04:36:01 -0800943 dr->enabled = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900944 }
945 return rc;
946}
947
948/**
949 * pcim_pin_device - Pin managed PCI device
950 * @pdev: PCI device to pin
951 *
952 * Pin managed PCI device @pdev. Pinned device won't be disabled on
953 * driver detach. @pdev must have been enabled with
954 * pcim_enable_device().
955 */
956void pcim_pin_device(struct pci_dev *pdev)
957{
958 struct pci_devres *dr;
959
960 dr = find_pci_dr(pdev);
Tejun Heo7f375f32007-02-25 04:36:01 -0800961 WARN_ON(!dr || !dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +0900962 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -0800963 dr->pinned = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900964}
965
Linus Torvalds1da177e2005-04-16 15:20:36 -0700966/**
967 * pcibios_disable_device - disable arch specific PCI resources for device dev
968 * @dev: the PCI device to disable
969 *
970 * Disables architecture specific PCI resources for the device. This
971 * is the default implementation. Architecture implementations can
972 * override this.
973 */
974void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
975
976/**
977 * pci_disable_device - Disable PCI device after use
978 * @dev: PCI device to be disabled
979 *
980 * Signal to the system that the PCI device is not in use by the system
981 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800982 *
983 * Note we don't actually disable the device until all callers of
984 * pci_device_enable() have called pci_device_disable().
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985 */
986void
987pci_disable_device(struct pci_dev *dev)
988{
Tejun Heo9ac78492007-01-20 16:00:26 +0900989 struct pci_devres *dr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990 u16 pci_command;
Shaohua Li99dc8042006-05-26 10:58:27 +0800991
Tejun Heo9ac78492007-01-20 16:00:26 +0900992 dr = find_pci_dr(dev);
993 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -0800994 dr->enabled = 0;
Tejun Heo9ac78492007-01-20 16:00:26 +0900995
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800996 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
997 return;
998
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1000 if (pci_command & PCI_COMMAND_MASTER) {
1001 pci_command &= ~PCI_COMMAND_MASTER;
1002 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1003 }
Kenji Kaneshigeceb43742005-04-08 14:53:31 +09001004 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005
1006 pcibios_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007}
1008
1009/**
Brian Kingf7bdd122007-04-06 16:39:36 -05001010 * pcibios_set_pcie_reset_state - set reset state for device dev
1011 * @dev: the PCI-E device reset
1012 * @state: Reset state to enter into
1013 *
1014 *
1015 * Sets the PCI-E reset state for the device. This is the default
1016 * implementation. Architecture implementations can override this.
1017 */
1018int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1019 enum pcie_reset_state state)
1020{
1021 return -EINVAL;
1022}
1023
1024/**
1025 * pci_set_pcie_reset_state - set reset state for device dev
1026 * @dev: the PCI-E device reset
1027 * @state: Reset state to enter into
1028 *
1029 *
1030 * Sets the PCI reset state for the device.
1031 */
1032int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1033{
1034 return pcibios_set_pcie_reset_state(dev, state);
1035}
1036
1037/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001038 * pci_pme_capable - check the capability of PCI device to generate PME#
1039 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001040 * @state: PCI state from which device will issue PME#.
1041 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001042static bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001043{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001044 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001045 return false;
1046
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001047 return !!(dev->pme_support & (1 << state));
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001048}
1049
1050/**
1051 * pci_pme_active - enable or disable PCI device's PME# function
1052 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001053 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1054 *
1055 * The caller must verify that the device is capable of generating PME# before
1056 * calling this function with @enable equal to 'true'.
1057 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001058static void pci_pme_active(struct pci_dev *dev, bool enable)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001059{
1060 u16 pmcsr;
1061
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001062 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001063 return;
1064
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001065 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001066 /* Clear PME_Status by writing 1 to it and enable PME# */
1067 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1068 if (!enable)
1069 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1070
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001071 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001072
1073 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1074 enable ? "enabled" : "disabled");
1075}
1076
1077/**
David Brownell075c1772007-04-26 00:12:06 -07001078 * pci_enable_wake - enable PCI device as wakeup event source
1079 * @dev: PCI device affected
1080 * @state: PCI state from which device will issue wakeup events
1081 * @enable: True to enable event generation; false to disable
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082 *
David Brownell075c1772007-04-26 00:12:06 -07001083 * This enables the device as a wakeup event source, or disables it.
1084 * When such events involves platform-specific hooks, those hooks are
1085 * called automatically by this routine.
1086 *
1087 * Devices with legacy power management (no standard PCI PM capabilities)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001088 * always require such platform hooks.
David Brownell075c1772007-04-26 00:12:06 -07001089 *
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001090 * RETURN VALUE:
1091 * 0 is returned on success
1092 * -EINVAL is returned if device is not supposed to wake up the system
1093 * Error code depending on the platform is returned if both the platform and
1094 * the native mechanism fail to enable the generation of wake-up events
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 */
1096int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1097{
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001098 int error = 0;
1099 bool pme_done = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001101 if (!device_may_wakeup(&dev->dev))
1102 return -EINVAL;
1103
1104 /*
1105 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1106 * Anderson we should be doing PME# wake enable followed by ACPI wake
1107 * enable. To disable wake-up we call the platform first, for symmetry.
David Brownell075c1772007-04-26 00:12:06 -07001108 */
1109
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001110 if (!enable && platform_pci_can_wakeup(dev))
1111 error = platform_pci_sleep_wake(dev, false);
1112
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001113 if (!enable || pci_pme_capable(dev, state)) {
1114 pci_pme_active(dev, enable);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001115 pme_done = true;
1116 }
1117
1118 if (enable && platform_pci_can_wakeup(dev))
1119 error = platform_pci_sleep_wake(dev, true);
1120
1121 return pme_done ? 0 : error;
1122}
1123
1124/**
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001125 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into
1126 * a sleep state
1127 * @dev: Device to handle.
1128 *
1129 * Choose the power state appropriate for the device depending on whether
1130 * it can wake up the system and/or is power manageable by the platform
1131 * (PCI_D3hot is the default) and put the device into that state.
1132 */
1133int pci_prepare_to_sleep(struct pci_dev *dev)
1134{
1135 pci_power_t target_state = PCI_D3hot;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001136 int error;
1137
1138 if (platform_pci_power_manageable(dev)) {
1139 /*
1140 * Call the platform to choose the target state of the device
1141 * and enable wake-up from this state if supported.
1142 */
1143 pci_power_t state = platform_pci_choose_state(dev);
1144
1145 switch (state) {
1146 case PCI_POWER_ERROR:
1147 case PCI_UNKNOWN:
1148 break;
1149 case PCI_D1:
1150 case PCI_D2:
1151 if (pci_no_d1d2(dev))
1152 break;
1153 default:
1154 target_state = state;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001155 }
1156 } else if (device_may_wakeup(&dev->dev)) {
1157 /*
1158 * Find the deepest state from which the device can generate
1159 * wake-up events, make it the target state and enable device
1160 * to generate PME#.
1161 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001162 if (!dev->pm_cap)
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001163 return -EIO;
1164
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001165 if (dev->pme_support) {
1166 while (target_state
1167 && !(dev->pme_support & (1 << target_state)))
1168 target_state--;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001169 }
1170 }
1171
Rafael J. Wysockic157dfa2008-07-13 22:45:06 +02001172 pci_enable_wake(dev, target_state, true);
1173
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001174 error = pci_set_power_state(dev, target_state);
1175
1176 if (error)
1177 pci_enable_wake(dev, target_state, false);
1178
1179 return error;
1180}
1181
1182/**
1183 * pci_back_from_sleep - turn PCI device on during system-wide transition into
1184 * the working state a sleep state
1185 * @dev: Device to handle.
1186 *
1187 * Disable device's sytem wake-up capability and put it into D0.
1188 */
1189int pci_back_from_sleep(struct pci_dev *dev)
1190{
1191 pci_enable_wake(dev, PCI_D0, false);
1192 return pci_set_power_state(dev, PCI_D0);
1193}
1194
1195/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001196 * pci_pm_init - Initialize PM functions of given PCI device
1197 * @dev: PCI device to handle.
1198 */
1199void pci_pm_init(struct pci_dev *dev)
1200{
1201 int pm;
1202 u16 pmc;
David Brownell075c1772007-04-26 00:12:06 -07001203
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001204 dev->pm_cap = 0;
1205
Linus Torvalds1da177e2005-04-16 15:20:36 -07001206 /* find PCI PM capability in list */
1207 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
David Brownell075c1772007-04-26 00:12:06 -07001208 if (!pm)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001209 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210 /* Check device's ability to generate PME# */
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001211 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001213 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1214 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1215 pmc & PCI_PM_CAP_VER_MASK);
1216 return;
David Brownell075c1772007-04-26 00:12:06 -07001217 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001219 dev->pm_cap = pm;
1220
1221 dev->d1_support = false;
1222 dev->d2_support = false;
1223 if (!pci_no_d1d2(dev)) {
1224 if (pmc & PCI_PM_CAP_D1) {
1225 dev_printk(KERN_DEBUG, &dev->dev, "supports D1\n");
1226 dev->d1_support = true;
1227 }
1228 if (pmc & PCI_PM_CAP_D2) {
1229 dev_printk(KERN_DEBUG, &dev->dev, "supports D2\n");
1230 dev->d2_support = true;
1231 }
1232 }
1233
1234 pmc &= PCI_PM_CAP_PME_MASK;
1235 if (pmc) {
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001236 dev_printk(KERN_INFO, &dev->dev,
1237 "PME# supported from%s%s%s%s%s\n",
1238 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1239 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1240 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1241 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1242 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001243 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001244 /*
1245 * Make device's PM flags reflect the wake-up capability, but
1246 * let the user space enable it to wake up the system as needed.
1247 */
1248 device_set_wakeup_capable(&dev->dev, true);
1249 device_set_wakeup_enable(&dev->dev, false);
1250 /* Disable the PME# generation functionality */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001251 pci_pme_active(dev, false);
1252 } else {
1253 dev->pme_support = 0;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001254 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255}
1256
1257int
1258pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1259{
1260 u8 pin;
1261
Kristen Accardi514d2072005-11-02 16:24:39 -08001262 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001263 if (!pin)
1264 return -1;
1265 pin--;
1266 while (dev->bus->self) {
1267 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1268 dev = dev->bus->self;
1269 }
1270 *bridge = dev;
1271 return pin;
1272}
1273
1274/**
1275 * pci_release_region - Release a PCI bar
1276 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1277 * @bar: BAR to release
1278 *
1279 * Releases the PCI I/O and memory resources previously reserved by a
1280 * successful call to pci_request_region. Call this function only
1281 * after all use of the PCI regions has ceased.
1282 */
1283void pci_release_region(struct pci_dev *pdev, int bar)
1284{
Tejun Heo9ac78492007-01-20 16:00:26 +09001285 struct pci_devres *dr;
1286
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287 if (pci_resource_len(pdev, bar) == 0)
1288 return;
1289 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1290 release_region(pci_resource_start(pdev, bar),
1291 pci_resource_len(pdev, bar));
1292 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1293 release_mem_region(pci_resource_start(pdev, bar),
1294 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +09001295
1296 dr = find_pci_dr(pdev);
1297 if (dr)
1298 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299}
1300
1301/**
1302 * pci_request_region - Reserved PCI I/O and memory resource
1303 * @pdev: PCI device whose resources are to be reserved
1304 * @bar: BAR to be reserved
1305 * @res_name: Name to be associated with resource.
1306 *
1307 * Mark the PCI region associated with PCI device @pdev BR @bar as
1308 * being reserved by owner @res_name. Do not access any
1309 * address inside the PCI regions unless this call returns
1310 * successfully.
1311 *
1312 * Returns 0 on success, or %EBUSY on error. A warning
1313 * message is also printed on failure.
1314 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001315int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001316{
Tejun Heo9ac78492007-01-20 16:00:26 +09001317 struct pci_devres *dr;
1318
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319 if (pci_resource_len(pdev, bar) == 0)
1320 return 0;
1321
1322 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1323 if (!request_region(pci_resource_start(pdev, bar),
1324 pci_resource_len(pdev, bar), res_name))
1325 goto err_out;
1326 }
1327 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1328 if (!request_mem_region(pci_resource_start(pdev, bar),
1329 pci_resource_len(pdev, bar), res_name))
1330 goto err_out;
1331 }
Tejun Heo9ac78492007-01-20 16:00:26 +09001332
1333 dr = find_pci_dr(pdev);
1334 if (dr)
1335 dr->region_mask |= 1 << bar;
1336
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337 return 0;
1338
1339err_out:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001340 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region [%#llx-%#llx]\n",
Jesse Barnese4ec7a02008-06-25 16:12:25 -07001341 bar,
1342 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1343 (unsigned long long)pci_resource_start(pdev, bar),
1344 (unsigned long long)pci_resource_end(pdev, bar));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001345 return -EBUSY;
1346}
1347
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001348/**
1349 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1350 * @pdev: PCI device whose resources were previously reserved
1351 * @bars: Bitmask of BARs to be released
1352 *
1353 * Release selected PCI I/O and memory resources previously reserved.
1354 * Call this function only after all use of the PCI regions has ceased.
1355 */
1356void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1357{
1358 int i;
1359
1360 for (i = 0; i < 6; i++)
1361 if (bars & (1 << i))
1362 pci_release_region(pdev, i);
1363}
1364
1365/**
1366 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1367 * @pdev: PCI device whose resources are to be reserved
1368 * @bars: Bitmask of BARs to be requested
1369 * @res_name: Name to be associated with resource
1370 */
1371int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1372 const char *res_name)
1373{
1374 int i;
1375
1376 for (i = 0; i < 6; i++)
1377 if (bars & (1 << i))
1378 if(pci_request_region(pdev, i, res_name))
1379 goto err_out;
1380 return 0;
1381
1382err_out:
1383 while(--i >= 0)
1384 if (bars & (1 << i))
1385 pci_release_region(pdev, i);
1386
1387 return -EBUSY;
1388}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001389
1390/**
1391 * pci_release_regions - Release reserved PCI I/O and memory resources
1392 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1393 *
1394 * Releases all PCI I/O and memory resources previously reserved by a
1395 * successful call to pci_request_regions. Call this function only
1396 * after all use of the PCI regions has ceased.
1397 */
1398
1399void pci_release_regions(struct pci_dev *pdev)
1400{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001401 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402}
1403
1404/**
1405 * pci_request_regions - Reserved PCI I/O and memory resources
1406 * @pdev: PCI device whose resources are to be reserved
1407 * @res_name: Name to be associated with resource.
1408 *
1409 * Mark all PCI regions associated with PCI device @pdev as
1410 * being reserved by owner @res_name. Do not access any
1411 * address inside the PCI regions unless this call returns
1412 * successfully.
1413 *
1414 * Returns 0 on success, or %EBUSY on error. A warning
1415 * message is also printed on failure.
1416 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001417int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001419 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001420}
1421
1422/**
1423 * pci_set_master - enables bus-mastering for device dev
1424 * @dev: the PCI device to enable
1425 *
1426 * Enables bus-mastering on the device and calls pcibios_set_master()
1427 * to do the needed arch specific settings.
1428 */
1429void
1430pci_set_master(struct pci_dev *dev)
1431{
1432 u16 cmd;
1433
1434 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1435 if (! (cmd & PCI_COMMAND_MASTER)) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001436 dev_dbg(&dev->dev, "enabling bus mastering\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001437 cmd |= PCI_COMMAND_MASTER;
1438 pci_write_config_word(dev, PCI_COMMAND, cmd);
1439 }
1440 dev->is_busmaster = 1;
1441 pcibios_set_master(dev);
1442}
1443
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001444#ifdef PCI_DISABLE_MWI
1445int pci_set_mwi(struct pci_dev *dev)
1446{
1447 return 0;
1448}
1449
Randy Dunlap694625c2007-07-09 11:55:54 -07001450int pci_try_set_mwi(struct pci_dev *dev)
1451{
1452 return 0;
1453}
1454
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001455void pci_clear_mwi(struct pci_dev *dev)
1456{
1457}
1458
1459#else
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001460
1461#ifndef PCI_CACHE_LINE_BYTES
1462#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1463#endif
1464
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465/* This can be overridden by arch code. */
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001466/* Don't forget this is measured in 32-bit words, not bytes */
1467u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001468
1469/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001470 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1471 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07001472 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001473 * Helper function for pci_set_mwi.
1474 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1476 *
1477 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1478 */
1479static int
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001480pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481{
1482 u8 cacheline_size;
1483
1484 if (!pci_cache_line_size)
1485 return -EINVAL; /* The system doesn't support MWI. */
1486
1487 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1488 equal to or multiple of the right value. */
1489 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1490 if (cacheline_size >= pci_cache_line_size &&
1491 (cacheline_size % pci_cache_line_size) == 0)
1492 return 0;
1493
1494 /* Write the correct value. */
1495 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1496 /* Read it back. */
1497 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1498 if (cacheline_size == pci_cache_line_size)
1499 return 0;
1500
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001501 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1502 "supported\n", pci_cache_line_size << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001503
1504 return -EINVAL;
1505}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506
1507/**
1508 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1509 * @dev: the PCI device for which MWI is enabled
1510 *
Randy Dunlap694625c2007-07-09 11:55:54 -07001511 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001512 *
1513 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1514 */
1515int
1516pci_set_mwi(struct pci_dev *dev)
1517{
1518 int rc;
1519 u16 cmd;
1520
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001521 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522 if (rc)
1523 return rc;
1524
1525 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1526 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001527 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528 cmd |= PCI_COMMAND_INVALIDATE;
1529 pci_write_config_word(dev, PCI_COMMAND, cmd);
1530 }
1531
1532 return 0;
1533}
1534
1535/**
Randy Dunlap694625c2007-07-09 11:55:54 -07001536 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1537 * @dev: the PCI device for which MWI is enabled
1538 *
1539 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1540 * Callers are not required to check the return value.
1541 *
1542 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1543 */
1544int pci_try_set_mwi(struct pci_dev *dev)
1545{
1546 int rc = pci_set_mwi(dev);
1547 return rc;
1548}
1549
1550/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1552 * @dev: the PCI device to disable
1553 *
1554 * Disables PCI Memory-Write-Invalidate transaction on the device
1555 */
1556void
1557pci_clear_mwi(struct pci_dev *dev)
1558{
1559 u16 cmd;
1560
1561 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1562 if (cmd & PCI_COMMAND_INVALIDATE) {
1563 cmd &= ~PCI_COMMAND_INVALIDATE;
1564 pci_write_config_word(dev, PCI_COMMAND, cmd);
1565 }
1566}
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001567#endif /* ! PCI_DISABLE_MWI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568
Brett M Russa04ce0f2005-08-15 15:23:41 -04001569/**
1570 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001571 * @pdev: the PCI device to operate on
1572 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04001573 *
1574 * Enables/disables PCI INTx for device dev
1575 */
1576void
1577pci_intx(struct pci_dev *pdev, int enable)
1578{
1579 u16 pci_command, new;
1580
1581 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1582
1583 if (enable) {
1584 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1585 } else {
1586 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1587 }
1588
1589 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09001590 struct pci_devres *dr;
1591
Brett M Russ2fd9d742005-09-09 10:02:22 -07001592 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09001593
1594 dr = find_pci_dr(pdev);
1595 if (dr && !dr->restore_intx) {
1596 dr->restore_intx = 1;
1597 dr->orig_intx = !enable;
1598 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04001599 }
1600}
1601
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001602/**
1603 * pci_msi_off - disables any msi or msix capabilities
Randy Dunlap8d7d86e2007-03-16 19:55:52 -07001604 * @dev: the PCI device to operate on
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001605 *
1606 * If you want to use msi see pci_enable_msi and friends.
1607 * This is a lower level primitive that allows us to disable
1608 * msi operation at the device level.
1609 */
1610void pci_msi_off(struct pci_dev *dev)
1611{
1612 int pos;
1613 u16 control;
1614
1615 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1616 if (pos) {
1617 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1618 control &= ~PCI_MSI_FLAGS_ENABLE;
1619 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1620 }
1621 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1622 if (pos) {
1623 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1624 control &= ~PCI_MSIX_FLAGS_ENABLE;
1625 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1626 }
1627}
1628
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1630/*
1631 * These can be overridden by arch-specific implementations
1632 */
1633int
1634pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1635{
1636 if (!pci_dma_supported(dev, mask))
1637 return -EIO;
1638
1639 dev->dma_mask = mask;
1640
1641 return 0;
1642}
1643
1644int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001645pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1646{
1647 if (!pci_dma_supported(dev, mask))
1648 return -EIO;
1649
1650 dev->dev.coherent_dma_mask = mask;
1651
1652 return 0;
1653}
1654#endif
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001655
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001656#ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1657int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
1658{
1659 return dma_set_max_seg_size(&dev->dev, size);
1660}
1661EXPORT_SYMBOL(pci_set_dma_max_seg_size);
1662#endif
1663
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001664#ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1665int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
1666{
1667 return dma_set_seg_boundary(&dev->dev, mask);
1668}
1669EXPORT_SYMBOL(pci_set_dma_seg_boundary);
1670#endif
1671
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001672/**
Peter Orubad556ad42007-05-15 13:59:13 +02001673 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1674 * @dev: PCI device to query
1675 *
1676 * Returns mmrbc: maximum designed memory read count in bytes
1677 * or appropriate error value.
1678 */
1679int pcix_get_max_mmrbc(struct pci_dev *dev)
1680{
Andrew Mortonb7b095c2007-07-09 11:55:50 -07001681 int err, cap;
Peter Orubad556ad42007-05-15 13:59:13 +02001682 u32 stat;
1683
1684 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1685 if (!cap)
1686 return -EINVAL;
1687
1688 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1689 if (err)
1690 return -EINVAL;
1691
Andrew Mortonb7b095c2007-07-09 11:55:50 -07001692 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
Peter Orubad556ad42007-05-15 13:59:13 +02001693}
1694EXPORT_SYMBOL(pcix_get_max_mmrbc);
1695
1696/**
1697 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1698 * @dev: PCI device to query
1699 *
1700 * Returns mmrbc: maximum memory read count in bytes
1701 * or appropriate error value.
1702 */
1703int pcix_get_mmrbc(struct pci_dev *dev)
1704{
1705 int ret, cap;
1706 u32 cmd;
1707
1708 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1709 if (!cap)
1710 return -EINVAL;
1711
1712 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1713 if (!ret)
1714 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1715
1716 return ret;
1717}
1718EXPORT_SYMBOL(pcix_get_mmrbc);
1719
1720/**
1721 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1722 * @dev: PCI device to query
1723 * @mmrbc: maximum memory read count in bytes
1724 * valid values are 512, 1024, 2048, 4096
1725 *
1726 * If possible sets maximum memory read byte count, some bridges have erratas
1727 * that prevent this.
1728 */
1729int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1730{
1731 int cap, err = -EINVAL;
1732 u32 stat, cmd, v, o;
1733
vignesh babu229f5af2007-08-13 18:23:14 +05301734 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
Peter Orubad556ad42007-05-15 13:59:13 +02001735 goto out;
1736
1737 v = ffs(mmrbc) - 10;
1738
1739 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1740 if (!cap)
1741 goto out;
1742
1743 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1744 if (err)
1745 goto out;
1746
1747 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1748 return -E2BIG;
1749
1750 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1751 if (err)
1752 goto out;
1753
1754 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1755 if (o != v) {
1756 if (v > o && dev->bus &&
1757 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1758 return -EIO;
1759
1760 cmd &= ~PCI_X_CMD_MAX_READ;
1761 cmd |= v << 2;
1762 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1763 }
1764out:
1765 return err;
1766}
1767EXPORT_SYMBOL(pcix_set_mmrbc);
1768
1769/**
1770 * pcie_get_readrq - get PCI Express read request size
1771 * @dev: PCI device to query
1772 *
1773 * Returns maximum memory read request in bytes
1774 * or appropriate error value.
1775 */
1776int pcie_get_readrq(struct pci_dev *dev)
1777{
1778 int ret, cap;
1779 u16 ctl;
1780
1781 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1782 if (!cap)
1783 return -EINVAL;
1784
1785 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1786 if (!ret)
1787 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1788
1789 return ret;
1790}
1791EXPORT_SYMBOL(pcie_get_readrq);
1792
1793/**
1794 * pcie_set_readrq - set PCI Express maximum memory read request
1795 * @dev: PCI device to query
Randy Dunlap42e61f42007-07-23 21:42:11 -07001796 * @rq: maximum memory read count in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02001797 * valid values are 128, 256, 512, 1024, 2048, 4096
1798 *
1799 * If possible sets maximum read byte count
1800 */
1801int pcie_set_readrq(struct pci_dev *dev, int rq)
1802{
1803 int cap, err = -EINVAL;
1804 u16 ctl, v;
1805
vignesh babu229f5af2007-08-13 18:23:14 +05301806 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
Peter Orubad556ad42007-05-15 13:59:13 +02001807 goto out;
1808
1809 v = (ffs(rq) - 8) << 12;
1810
1811 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1812 if (!cap)
1813 goto out;
1814
1815 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1816 if (err)
1817 goto out;
1818
1819 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1820 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1821 ctl |= v;
1822 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1823 }
1824
1825out:
1826 return err;
1827}
1828EXPORT_SYMBOL(pcie_set_readrq);
1829
1830/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001831 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08001832 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001833 * @flags: resource type mask to be selected
1834 *
1835 * This helper routine makes bar mask from the type of resource.
1836 */
1837int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1838{
1839 int i, bars = 0;
1840 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1841 if (pci_resource_flags(dev, i) & flags)
1842 bars |= (1 << i);
1843 return bars;
1844}
1845
Jeff Garzik32a2eea2007-10-11 16:57:27 -04001846static void __devinit pci_no_domains(void)
1847{
1848#ifdef CONFIG_PCI_DOMAINS
1849 pci_domains_supported = 0;
1850#endif
1851}
1852
Linus Torvalds1da177e2005-04-16 15:20:36 -07001853static int __devinit pci_init(void)
1854{
1855 struct pci_dev *dev = NULL;
1856
1857 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1858 pci_fixup_device(pci_fixup_final, dev);
1859 }
1860 return 0;
1861}
1862
1863static int __devinit pci_setup(char *str)
1864{
1865 while (str) {
1866 char *k = strchr(str, ',');
1867 if (k)
1868 *k++ = 0;
1869 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001870 if (!strcmp(str, "nomsi")) {
1871 pci_no_msi();
Randy Dunlap7f785762007-10-05 13:17:58 -07001872 } else if (!strcmp(str, "noaer")) {
1873 pci_no_aer();
Jeff Garzik32a2eea2007-10-11 16:57:27 -04001874 } else if (!strcmp(str, "nodomains")) {
1875 pci_no_domains();
Atsushi Nemoto4516a612007-02-05 16:36:06 -08001876 } else if (!strncmp(str, "cbiosize=", 9)) {
1877 pci_cardbus_io_size = memparse(str + 9, &str);
1878 } else if (!strncmp(str, "cbmemsize=", 10)) {
1879 pci_cardbus_mem_size = memparse(str + 10, &str);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07001880 } else {
1881 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1882 str);
1883 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884 }
1885 str = k;
1886 }
Andi Kleen0637a702006-09-26 10:52:41 +02001887 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001888}
Andi Kleen0637a702006-09-26 10:52:41 +02001889early_param("pci", pci_setup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001890
1891device_initcall(pci_init);
1892
Tejun Heo0b62e132007-07-27 14:43:35 +09001893EXPORT_SYMBOL(pci_reenable_device);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001894EXPORT_SYMBOL(pci_enable_device_io);
1895EXPORT_SYMBOL(pci_enable_device_mem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896EXPORT_SYMBOL(pci_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09001897EXPORT_SYMBOL(pcim_enable_device);
1898EXPORT_SYMBOL(pcim_pin_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001900EXPORT_SYMBOL(pci_find_capability);
1901EXPORT_SYMBOL(pci_bus_find_capability);
1902EXPORT_SYMBOL(pci_release_regions);
1903EXPORT_SYMBOL(pci_request_regions);
1904EXPORT_SYMBOL(pci_release_region);
1905EXPORT_SYMBOL(pci_request_region);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001906EXPORT_SYMBOL(pci_release_selected_regions);
1907EXPORT_SYMBOL(pci_request_selected_regions);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001908EXPORT_SYMBOL(pci_set_master);
1909EXPORT_SYMBOL(pci_set_mwi);
Randy Dunlap694625c2007-07-09 11:55:54 -07001910EXPORT_SYMBOL(pci_try_set_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001911EXPORT_SYMBOL(pci_clear_mwi);
Brett M Russa04ce0f2005-08-15 15:23:41 -04001912EXPORT_SYMBOL_GPL(pci_intx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913EXPORT_SYMBOL(pci_set_dma_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001914EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1915EXPORT_SYMBOL(pci_assign_resource);
1916EXPORT_SYMBOL(pci_find_parent_resource);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001917EXPORT_SYMBOL(pci_select_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001918
1919EXPORT_SYMBOL(pci_set_power_state);
1920EXPORT_SYMBOL(pci_save_state);
1921EXPORT_SYMBOL(pci_restore_state);
1922EXPORT_SYMBOL(pci_enable_wake);
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001923EXPORT_SYMBOL(pci_prepare_to_sleep);
1924EXPORT_SYMBOL(pci_back_from_sleep);
Brian Kingf7bdd122007-04-06 16:39:36 -05001925EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001926