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Santosh Shilimkar367cd312009-04-28 20:51:52 +05301/*
2 * OMAP4 SMP source file. It contains platform specific fucntions
3 * needed for the linux smp kernel.
4 *
5 * Copyright (C) 2009 Texas Instruments, Inc.
6 *
7 * Author:
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#include <linux/init.h>
19#include <linux/device.h>
Santosh Shilimkar367cd312009-04-28 20:51:52 +053020#include <linux/smp.h>
21#include <linux/io.h>
22
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080023#include <asm/cacheflush.h>
Russell King0f7b3322011-04-03 13:01:30 +010024#include <asm/hardware/gic.h>
Santosh Shilimkar367cd312009-04-28 20:51:52 +053025#include <asm/smp_scu.h>
26#include <mach/hardware.h>
Santosh Shilimkarfbc9be12010-05-14 12:05:26 -070027#include <mach/omap4-common.h>
Santosh Shilimkar367cd312009-04-28 20:51:52 +053028
Santosh Shilimkar367cd312009-04-28 20:51:52 +053029/* SCU base address */
Tony Lindgrene4e7a132009-10-19 15:25:26 -070030static void __iomem *scu_base;
Santosh Shilimkar367cd312009-04-28 20:51:52 +053031
Santosh Shilimkar367cd312009-04-28 20:51:52 +053032static DEFINE_SPINLOCK(boot_lock);
33
34void __cpuinit platform_secondary_init(unsigned int cpu)
35{
Santosh Shilimkar367cd312009-04-28 20:51:52 +053036 /*
37 * If any interrupts are already enabled for the primary
38 * core (e.g. timer irq), then they will not have been enabled
39 * for us: do so
40 */
Russell King38489532010-12-04 16:01:03 +000041 gic_secondary_init(0);
Santosh Shilimkar367cd312009-04-28 20:51:52 +053042
43 /*
44 * Synchronise with the boot thread.
45 */
46 spin_lock(&boot_lock);
47 spin_unlock(&boot_lock);
48}
49
50int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
51{
Santosh Shilimkar367cd312009-04-28 20:51:52 +053052 /*
53 * Set synchronisation state between this boot processor
54 * and the secondary one
55 */
56 spin_lock(&boot_lock);
57
58 /*
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080059 * Update the AuxCoreBoot0 with boot state for secondary core.
Santosh Shilimkar367cd312009-04-28 20:51:52 +053060 * omap_secondary_startup() routine will hold the secondary core till
61 * the AuxCoreBoot1 register is updated with cpu state
62 * A barrier is added to ensure that write buffer is drained
63 */
Santosh Shilimkar7d35b8d2010-08-02 13:18:19 +030064 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080065 flush_cache_all();
Santosh Shilimkar367cd312009-04-28 20:51:52 +053066 smp_wmb();
Russell King0f7b3322011-04-03 13:01:30 +010067 gic_raise_softirq(cpumask_of(cpu), 1);
Santosh Shilimkar367cd312009-04-28 20:51:52 +053068
Santosh Shilimkar367cd312009-04-28 20:51:52 +053069 /*
70 * Now the secondary core is starting up let it run its
71 * calibrations, then wait for it to finish
72 */
73 spin_unlock(&boot_lock);
74
75 return 0;
76}
77
78static void __init wakeup_secondary(void)
79{
80 /*
81 * Write the address of secondary startup routine into the
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080082 * AuxCoreBoot1 where ROM code will jump and start executing
Santosh Shilimkar367cd312009-04-28 20:51:52 +053083 * on secondary core once out of WFE
84 * A barrier is added to ensure that write buffer is drained
85 */
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080086 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
Santosh Shilimkar367cd312009-04-28 20:51:52 +053087 smp_wmb();
88
89 /*
90 * Send a 'sev' to wake the secondary core from WFE.
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080091 * Drain the outstanding writes to memory
Santosh Shilimkar367cd312009-04-28 20:51:52 +053092 */
Tony Lindgrena4192d32010-08-16 09:21:20 +030093 dsb_sev();
Santosh Shilimkar367cd312009-04-28 20:51:52 +053094 mb();
95}
96
97/*
98 * Initialise the CPU possible map early - this describes the CPUs
99 * which may be present or become present in the system.
100 */
101void __init smp_init_cpus(void)
102{
Tony Lindgrene4e7a132009-10-19 15:25:26 -0700103 unsigned int i, ncores;
104
105 /* Never released */
106 scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
107 BUG_ON(!scu_base);
108
Russell Kingfd778f02010-12-02 18:09:37 +0000109 ncores = scu_get_core_count(scu_base);
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530110
111 /* sanity check */
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530112 if (ncores > NR_CPUS) {
113 printk(KERN_WARNING
114 "OMAP4: no. of cores (%d) greater than configured "
115 "maximum of %d - clipping\n",
116 ncores, NR_CPUS);
117 ncores = NR_CPUS;
118 }
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530119
Russell Kingbbc3d142010-12-03 10:42:58 +0000120 for (i = 0; i < ncores; i++)
121 set_cpu_possible(i, true);
Russell King0f7b3322011-04-03 13:01:30 +0100122
123 set_smp_cross_call(gic_raise_softirq);
Russell Kingbbc3d142010-12-03 10:42:58 +0000124}
125
Russell King05c74a62010-12-03 11:09:48 +0000126void __init platform_smp_prepare_cpus(unsigned int max_cpus)
Russell Kingbbc3d142010-12-03 10:42:58 +0000127{
Russell Kingbbc3d142010-12-03 10:42:58 +0000128 int i;
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530129
130 /*
131 * Initialise the present map, which describes the set of CPUs
132 * actually populated at the present time.
133 */
134 for (i = 0; i < max_cpus; i++)
135 set_cpu_present(i, true);
136
Russell King05c74a62010-12-03 11:09:48 +0000137 /*
138 * Initialise the SCU and wake up the secondary core using
139 * wakeup_secondary().
140 */
141 scu_enable(scu_base);
142 wakeup_secondary();
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530143}