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wanzongshun7ec80dd2008-12-03 03:55:38 +01001/*
2 * linux/arch/arm/mach-w90x900/time.c
3 *
4 * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
5 *
wanzongshun58b53692009-08-14 15:36:44 +01006 * Copyright (c) 2009 Nuvoton technology corporation
wanzongshun7ec80dd2008-12-03 03:55:38 +01007 * All rights reserved.
8 *
9 * Wan ZongShun <mcuos.com@gmail.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/leds.h>
wanzongshun58b53692009-08-14 15:36:44 +010026#include <linux/clocksource.h>
27#include <linux/clockchips.h>
wanzongshun7ec80dd2008-12-03 03:55:38 +010028
29#include <asm/mach-types.h>
30#include <asm/mach/irq.h>
31#include <asm/mach/time.h>
32
wanzongshun7ec80dd2008-12-03 03:55:38 +010033#include <mach/map.h>
34#include <mach/regs-timer.h>
35
wanzongshun58b53692009-08-14 15:36:44 +010036#define RESETINT 0x1f
37#define PERIOD (0x01 << 27)
38#define ONESHOT (0x00 << 27)
39#define COUNTEN (0x01 << 30)
40#define INTEN (0x01 << 29)
41
42#define TICKS_PER_SEC 100
43#define PRESCALE 0x63 /* Divider = prescale + 1 */
44
Li Jie1368c512009-12-31 15:57:53 +010045#define TDR_SHIFT 24
46#define TDR_MASK ((1 << TDR_SHIFT) - 1)
47
48static unsigned int timer0_load;
wanzongshun58b53692009-08-14 15:36:44 +010049
wanzongshun35c92212009-08-21 07:07:46 +010050static void nuc900_clockevent_setmode(enum clock_event_mode mode,
wanzongshun58b53692009-08-14 15:36:44 +010051 struct clock_event_device *clk)
wanzongshun7ec80dd2008-12-03 03:55:38 +010052{
wanzongshun58b53692009-08-14 15:36:44 +010053 unsigned int val;
54
55 val = __raw_readl(REG_TCSR0);
56 val &= ~(0x03 << 27);
57
58 switch (mode) {
59 case CLOCK_EVT_MODE_PERIODIC:
60 __raw_writel(timer0_load, REG_TICR0);
61 val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
62 break;
63
64 case CLOCK_EVT_MODE_ONESHOT:
65 val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
66 break;
67
68 case CLOCK_EVT_MODE_UNUSED:
69 case CLOCK_EVT_MODE_SHUTDOWN:
70 case CLOCK_EVT_MODE_RESUME:
71 break;
72 }
73
74 __raw_writel(val, REG_TCSR0);
75}
76
wanzongshun35c92212009-08-21 07:07:46 +010077static int nuc900_clockevent_setnextevent(unsigned long evt,
wanzongshun58b53692009-08-14 15:36:44 +010078 struct clock_event_device *clk)
79{
80 unsigned int val;
81
82 __raw_writel(evt, REG_TICR0);
83
84 val = __raw_readl(REG_TCSR0);
85 val |= (COUNTEN | INTEN | PRESCALE);
86 __raw_writel(val, REG_TCSR0);
87
wanzongshun7ec80dd2008-12-03 03:55:38 +010088 return 0;
89}
90
wanzongshun35c92212009-08-21 07:07:46 +010091static struct clock_event_device nuc900_clockevent_device = {
92 .name = "nuc900-timer0",
wanzongshun58b53692009-08-14 15:36:44 +010093 .shift = 32,
Li Jie1368c512009-12-31 15:57:53 +010094 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
wanzongshun35c92212009-08-21 07:07:46 +010095 .set_mode = nuc900_clockevent_setmode,
96 .set_next_event = nuc900_clockevent_setnextevent,
wanzongshun58b53692009-08-14 15:36:44 +010097 .rating = 300,
98};
99
wanzongshun7ec80dd2008-12-03 03:55:38 +0100100/*IRQ handler for the timer*/
101
wanzongshun35c92212009-08-21 07:07:46 +0100102static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
wanzongshun7ec80dd2008-12-03 03:55:38 +0100103{
wanzongshun35c92212009-08-21 07:07:46 +0100104 struct clock_event_device *evt = &nuc900_clockevent_device;
wanzongshun58b53692009-08-14 15:36:44 +0100105
wanzongshun7ec80dd2008-12-03 03:55:38 +0100106 __raw_writel(0x01, REG_TISR); /* clear TIF0 */
wanzongshun58b53692009-08-14 15:36:44 +0100107
108 evt->event_handler(evt);
wanzongshun7ec80dd2008-12-03 03:55:38 +0100109 return IRQ_HANDLED;
110}
111
wanzongshun35c92212009-08-21 07:07:46 +0100112static struct irqaction nuc900_timer0_irq = {
113 .name = "nuc900-timer0",
wanzongshun7ec80dd2008-12-03 03:55:38 +0100114 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
wanzongshun35c92212009-08-21 07:07:46 +0100115 .handler = nuc900_timer0_interrupt,
wanzongshun7ec80dd2008-12-03 03:55:38 +0100116};
117
Li Jie1368c512009-12-31 15:57:53 +0100118static void __init nuc900_clockevents_init(void)
wanzongshun7ec80dd2008-12-03 03:55:38 +0100119{
Li Jie1368c512009-12-31 15:57:53 +0100120 unsigned int rate;
121 struct clk *clk = clk_get(NULL, "timer0");
122
123 BUG_ON(IS_ERR(clk));
124
125 __raw_writel(0x00, REG_TCSR0);
126
127 clk_enable(clk);
128 rate = clk_get_rate(clk) / (PRESCALE + 1);
129
130 timer0_load = (rate / TICKS_PER_SEC);
131
132 __raw_writel(RESETINT, REG_TISR);
133 setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
134
wanzongshun35c92212009-08-21 07:07:46 +0100135 nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
136 nuc900_clockevent_device.shift);
137 nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
138 &nuc900_clockevent_device);
139 nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
140 &nuc900_clockevent_device);
141 nuc900_clockevent_device.cpumask = cpumask_of(0);
wanzongshun58b53692009-08-14 15:36:44 +0100142
wanzongshun35c92212009-08-21 07:07:46 +0100143 clockevents_register_device(&nuc900_clockevent_device);
wanzongshun7ec80dd2008-12-03 03:55:38 +0100144}
145
wanzongshun35c92212009-08-21 07:07:46 +0100146static cycle_t nuc900_get_cycles(struct clocksource *cs)
wanzongshun7ec80dd2008-12-03 03:55:38 +0100147{
Li Jie1368c512009-12-31 15:57:53 +0100148 return (~__raw_readl(REG_TDR1)) & TDR_MASK;
wanzongshun58b53692009-08-14 15:36:44 +0100149}
150
wanzongshun35c92212009-08-21 07:07:46 +0100151static struct clocksource clocksource_nuc900 = {
152 .name = "nuc900-timer1",
wanzongshun58b53692009-08-14 15:36:44 +0100153 .rating = 200,
wanzongshun35c92212009-08-21 07:07:46 +0100154 .read = nuc900_get_cycles,
Li Jie1368c512009-12-31 15:57:53 +0100155 .mask = CLOCKSOURCE_MASK(TDR_SHIFT),
156 .shift = 10,
wanzongshun58b53692009-08-14 15:36:44 +0100157 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
158};
159
Li Jie1368c512009-12-31 15:57:53 +0100160static void __init nuc900_clocksource_init(void)
wanzongshun58b53692009-08-14 15:36:44 +0100161{
162 unsigned int val;
Li Jie1368c512009-12-31 15:57:53 +0100163 unsigned int rate;
164 struct clk *clk = clk_get(NULL, "timer1");
165
166 BUG_ON(IS_ERR(clk));
167
168 __raw_writel(0x00, REG_TCSR1);
169
170 clk_enable(clk);
171 rate = clk_get_rate(clk) / (PRESCALE + 1);
wanzongshun58b53692009-08-14 15:36:44 +0100172
173 __raw_writel(0xffffffff, REG_TICR1);
174
175 val = __raw_readl(REG_TCSR1);
Li Jie1368c512009-12-31 15:57:53 +0100176 val |= (COUNTEN | PERIOD | PRESCALE);
wanzongshun58b53692009-08-14 15:36:44 +0100177 __raw_writel(val, REG_TCSR1);
178
wanzongshun35c92212009-08-21 07:07:46 +0100179 clocksource_nuc900.mult =
180 clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift);
181 clocksource_register(&clocksource_nuc900);
wanzongshun58b53692009-08-14 15:36:44 +0100182}
183
wanzongshun35c92212009-08-21 07:07:46 +0100184static void __init nuc900_timer_init(void)
wanzongshun58b53692009-08-14 15:36:44 +0100185{
Li Jie1368c512009-12-31 15:57:53 +0100186 nuc900_clocksource_init();
187 nuc900_clockevents_init();
wanzongshun7ec80dd2008-12-03 03:55:38 +0100188}
189
wanzongshun35c92212009-08-21 07:07:46 +0100190struct sys_timer nuc900_timer = {
191 .init = nuc900_timer_init,
wanzongshun7ec80dd2008-12-03 03:55:38 +0100192};