blob: 091fe398676dc82b0e9ad51290a410a19af9f41e [file] [log] [blame]
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001/*
Ivo van Doorn811aa9c2008-02-03 15:42:53 +01002 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
Ivo van Doorn95ea3622007-09-25 17:57:13 -07003 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
Ivo van Doorn95ea3622007-09-25 17:57:13 -070027#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt61pci.h"
38
39/*
40 * Register access.
41 * BBP and RF register require indirect register access,
42 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
43 * These indirect registers work with busy bits,
44 * and we will try maximal REGISTER_BUSY_COUNT times to access
45 * the register while taking a REGISTER_BUSY_DELAY us delay
46 * between each attampt. When the busy bit is still set at that time,
47 * the access attempt is considered to have failed,
48 * and we will print an error.
49 */
Adam Baker0e14f6d2007-10-27 13:41:25 +020050static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
Ivo van Doorn95ea3622007-09-25 17:57:13 -070051{
52 u32 reg;
53 unsigned int i;
54
55 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
56 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
57 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
58 break;
59 udelay(REGISTER_BUSY_DELAY);
60 }
61
62 return reg;
63}
64
Adam Baker0e14f6d2007-10-27 13:41:25 +020065static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -070066 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
70 /*
71 * Wait until the BBP becomes ready.
72 */
73 reg = rt61pci_bbp_check(rt2x00dev);
74 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
75 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
76 return;
77 }
78
79 /*
80 * Write the data into the BBP.
81 */
82 reg = 0;
83 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
84 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
85 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
86 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
87
88 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
89}
90
Adam Baker0e14f6d2007-10-27 13:41:25 +020091static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -070092 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
96 /*
97 * Wait until the BBP becomes ready.
98 */
99 reg = rt61pci_bbp_check(rt2x00dev);
100 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
101 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
102 return;
103 }
104
105 /*
106 * Write the request into the BBP.
107 */
108 reg = 0;
109 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
110 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
112
113 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
114
115 /*
116 * Wait until the BBP becomes ready.
117 */
118 reg = rt61pci_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
121 *value = 0xff;
122 return;
123 }
124
125 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
126}
127
Adam Baker0e14f6d2007-10-27 13:41:25 +0200128static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700129 const unsigned int word, const u32 value)
130{
131 u32 reg;
132 unsigned int i;
133
134 if (!word)
135 return;
136
137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
138 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
139 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
140 goto rf_write;
141 udelay(REGISTER_BUSY_DELAY);
142 }
143
144 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
145 return;
146
147rf_write:
148 reg = 0;
149 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
150 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
151 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
152 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
153
154 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
155 rt2x00_rf_write(rt2x00dev, word, value);
156}
157
Ivo van Doorna9450b72008-02-03 15:53:40 +0100158#ifdef CONFIG_RT61PCI_LEDS
159/*
160 * This function is only called from rt61pci_led_brightness()
161 * make gcc happy by placing this function inside the
162 * same ifdef statement as the caller.
163 */
Adam Baker0e14f6d2007-10-27 13:41:25 +0200164static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700165 const u8 command, const u8 token,
166 const u8 arg0, const u8 arg1)
167{
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
171
172 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
173 ERROR(rt2x00dev, "mcu request error. "
174 "Request 0x%02x failed for token 0x%02x.\n",
175 command, token);
176 return;
177 }
178
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
182 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
183 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
184
185 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
186 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
187 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
188 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
189}
Ivo van Doorna9450b72008-02-03 15:53:40 +0100190#endif /* CONFIG_RT61PCI_LEDS */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700191
192static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
193{
194 struct rt2x00_dev *rt2x00dev = eeprom->data;
195 u32 reg;
196
197 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
198
199 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
200 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
201 eeprom->reg_data_clock =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
203 eeprom->reg_chip_select =
204 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
205}
206
207static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
208{
209 struct rt2x00_dev *rt2x00dev = eeprom->data;
210 u32 reg = 0;
211
212 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
213 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
214 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
215 !!eeprom->reg_data_clock);
216 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
217 !!eeprom->reg_chip_select);
218
219 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
220}
221
222#ifdef CONFIG_RT2X00_LIB_DEBUGFS
223#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
224
Adam Baker0e14f6d2007-10-27 13:41:25 +0200225static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700226 const unsigned int word, u32 *data)
227{
228 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
229}
230
Adam Baker0e14f6d2007-10-27 13:41:25 +0200231static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700232 const unsigned int word, u32 data)
233{
234 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
235}
236
237static const struct rt2x00debug rt61pci_rt2x00debug = {
238 .owner = THIS_MODULE,
239 .csr = {
240 .read = rt61pci_read_csr,
241 .write = rt61pci_write_csr,
242 .word_size = sizeof(u32),
243 .word_count = CSR_REG_SIZE / sizeof(u32),
244 },
245 .eeprom = {
246 .read = rt2x00_eeprom_read,
247 .write = rt2x00_eeprom_write,
248 .word_size = sizeof(u16),
249 .word_count = EEPROM_SIZE / sizeof(u16),
250 },
251 .bbp = {
252 .read = rt61pci_bbp_read,
253 .write = rt61pci_bbp_write,
254 .word_size = sizeof(u8),
255 .word_count = BBP_SIZE / sizeof(u8),
256 },
257 .rf = {
258 .read = rt2x00_rf_read,
259 .write = rt61pci_rf_write,
260 .word_size = sizeof(u32),
261 .word_count = RF_SIZE / sizeof(u32),
262 },
263};
264#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
265
266#ifdef CONFIG_RT61PCI_RFKILL
267static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
268{
269 u32 reg;
270
271 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500272 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700273}
Ivo van Doorn81873e92007-10-06 14:14:06 +0200274#else
275#define rt61pci_rfkill_poll NULL
Ivo van Doorndcf54752007-09-25 20:57:25 +0200276#endif /* CONFIG_RT61PCI_RFKILL */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700277
Ivo van Doorna9450b72008-02-03 15:53:40 +0100278#ifdef CONFIG_RT61PCI_LEDS
279static void rt61pci_led_brightness(struct led_classdev *led_cdev,
280 enum led_brightness brightness)
281{
282 struct rt2x00_led *led =
283 container_of(led_cdev, struct rt2x00_led, led_dev);
284 unsigned int enabled = brightness != LED_OFF;
285 unsigned int a_mode =
286 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
287 unsigned int bg_mode =
288 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
289
290 if (led->type == LED_TYPE_RADIO) {
291 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
292 MCU_LEDCS_RADIO_STATUS, enabled);
293
294 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
295 (led->rt2x00dev->led_mcu_reg & 0xff),
296 ((led->rt2x00dev->led_mcu_reg >> 8)));
297 } else if (led->type == LED_TYPE_ASSOC) {
298 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
299 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
300 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
301 MCU_LEDCS_LINK_A_STATUS, a_mode);
302
303 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
304 (led->rt2x00dev->led_mcu_reg & 0xff),
305 ((led->rt2x00dev->led_mcu_reg >> 8)));
306 } else if (led->type == LED_TYPE_QUALITY) {
307 /*
308 * The brightness is divided into 6 levels (0 - 5),
309 * this means we need to convert the brightness
310 * argument into the matching level within that range.
311 */
312 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
313 brightness / (LED_FULL / 6), 0);
314 }
315}
316#else
317#define rt61pci_led_brightness NULL
318#endif /* CONFIG_RT61PCI_LEDS */
319
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700320/*
321 * Configuration handlers.
322 */
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100323static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
324 struct rt2x00_intf *intf,
325 struct rt2x00intf_conf *conf,
326 const unsigned int flags)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700327{
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100328 unsigned int beacon_base;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700329 u32 reg;
330
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100331 if (flags & CONFIG_UPDATE_TYPE) {
332 /*
333 * Clear current synchronisation setup.
334 * For the Beacon base registers we only need to clear
335 * the first byte since that byte contains the VALID and OWNER
336 * bits which (when set to 0) will invalidate the entire beacon.
337 */
338 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
339 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
340 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700341
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100342 /*
343 * Enable synchronisation.
344 */
345 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
346 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
347 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE,
348 (conf->sync == TSF_SYNC_BEACON));
349 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
350 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
351 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
352 }
353
354 if (flags & CONFIG_UPDATE_MAC) {
355 reg = le32_to_cpu(conf->mac[1]);
356 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
357 conf->mac[1] = cpu_to_le32(reg);
358
359 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
360 conf->mac, sizeof(conf->mac));
361 }
362
363 if (flags & CONFIG_UPDATE_BSSID) {
364 reg = le32_to_cpu(conf->bssid[1]);
365 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
366 conf->bssid[1] = cpu_to_le32(reg);
367
368 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
369 conf->bssid, sizeof(conf->bssid));
370 }
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700371}
372
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100373static int rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
374 const int short_preamble,
375 const int ack_timeout,
376 const int ack_consume_time)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700377{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700378 u32 reg;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700379
380 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200381 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700382 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
383
384 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
Ivo van Doorn4f5af6eb2007-10-06 14:16:30 +0200385 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200386 !!short_preamble);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700387 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100388
389 return 0;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700390}
391
392static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200393 const int basic_rate_mask)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700394{
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200395 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700396}
397
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200398static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
399 struct rf_channel *rf, const int txpower)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700400{
401 u8 r3;
402 u8 r94;
403 u8 smart;
404
405 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
406 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
407
408 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
409 rt2x00_rf(&rt2x00dev->chip, RF2527));
410
411 rt61pci_bbp_read(rt2x00dev, 3, &r3);
412 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
413 rt61pci_bbp_write(rt2x00dev, 3, r3);
414
415 r94 = 6;
416 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
417 r94 += txpower - MAX_TXPOWER;
418 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
419 r94 += txpower;
420 rt61pci_bbp_write(rt2x00dev, 94, r94);
421
422 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
423 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
424 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
425 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
426
427 udelay(200);
428
429 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
430 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
431 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
432 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
433
434 udelay(200);
435
436 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
437 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
438 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
439 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
440
441 msleep(1);
442}
443
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700444static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
445 const int txpower)
446{
447 struct rf_channel rf;
448
449 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
450 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
451 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
452 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
453
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200454 rt61pci_config_channel(rt2x00dev, &rf, txpower);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700455}
456
457static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200458 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700459{
460 u8 r3;
461 u8 r4;
462 u8 r77;
463
464 rt61pci_bbp_read(rt2x00dev, 3, &r3);
465 rt61pci_bbp_read(rt2x00dev, 4, &r4);
466 rt61pci_bbp_read(rt2x00dev, 77, &r77);
467
468 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
Mattias Nissleracaa4102007-10-27 13:41:53 +0200469 rt2x00_rf(&rt2x00dev->chip, RF5325));
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200470
471 /*
472 * Configure the RX antenna.
473 */
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200474 switch (ant->rx) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700475 case ANTENNA_HW_DIVERSITY:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200476 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700477 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
Johannes Berg8318d782008-01-24 19:38:38 +0100478 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700479 break;
480 case ANTENNA_A:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200481 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700482 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
Johannes Berg8318d782008-01-24 19:38:38 +0100483 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
Mattias Nissleracaa4102007-10-27 13:41:53 +0200484 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
485 else
486 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700487 break;
Ivo van Doorn39e75852007-10-13 16:26:27 +0200488 case ANTENNA_SW_DIVERSITY:
489 /*
490 * NOTE: We should never come here because rt2x00lib is
491 * supposed to catch this and send us the correct antenna
492 * explicitely. However we are nog going to bug about this.
493 * Instead, just default to antenna B.
494 */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700495 case ANTENNA_B:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200496 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700497 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
Johannes Berg8318d782008-01-24 19:38:38 +0100498 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
Mattias Nissleracaa4102007-10-27 13:41:53 +0200499 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
500 else
501 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700502 break;
503 }
504
505 rt61pci_bbp_write(rt2x00dev, 77, r77);
506 rt61pci_bbp_write(rt2x00dev, 3, r3);
507 rt61pci_bbp_write(rt2x00dev, 4, r4);
508}
509
510static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200511 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700512{
513 u8 r3;
514 u8 r4;
515 u8 r77;
516
517 rt61pci_bbp_read(rt2x00dev, 3, &r3);
518 rt61pci_bbp_read(rt2x00dev, 4, &r4);
519 rt61pci_bbp_read(rt2x00dev, 77, &r77);
520
521 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
Mattias Nissleracaa4102007-10-27 13:41:53 +0200522 rt2x00_rf(&rt2x00dev->chip, RF2529));
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700523 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
524 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
525
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200526 /*
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200527 * Configure the RX antenna.
528 */
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200529 switch (ant->rx) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700530 case ANTENNA_HW_DIVERSITY:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200531 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700532 break;
533 case ANTENNA_A:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
535 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700536 break;
Ivo van Doorn39e75852007-10-13 16:26:27 +0200537 case ANTENNA_SW_DIVERSITY:
538 /*
539 * NOTE: We should never come here because rt2x00lib is
540 * supposed to catch this and send us the correct antenna
541 * explicitely. However we are nog going to bug about this.
542 * Instead, just default to antenna B.
543 */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700544 case ANTENNA_B:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200545 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
546 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700547 break;
548 }
549
550 rt61pci_bbp_write(rt2x00dev, 77, r77);
551 rt61pci_bbp_write(rt2x00dev, 3, r3);
552 rt61pci_bbp_write(rt2x00dev, 4, r4);
553}
554
555static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
556 const int p1, const int p2)
557{
558 u32 reg;
559
560 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
561
Mattias Nissleracaa4102007-10-27 13:41:53 +0200562 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
563 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
564
565 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
566 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
567
568 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700569}
570
571static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200572 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700573{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700574 u8 r3;
575 u8 r4;
576 u8 r77;
577
578 rt61pci_bbp_read(rt2x00dev, 3, &r3);
579 rt61pci_bbp_read(rt2x00dev, 4, &r4);
580 rt61pci_bbp_read(rt2x00dev, 77, &r77);
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200581
Mattias Nissleracaa4102007-10-27 13:41:53 +0200582 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
583 * legacy driver. The code below should be ok for non-diversity setups.
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200584 */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700585
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200586 /*
587 * Configure the RX antenna.
588 */
589 switch (ant->rx) {
590 case ANTENNA_A:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200591 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
592 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
593 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200594 break;
595 case ANTENNA_SW_DIVERSITY:
596 case ANTENNA_HW_DIVERSITY:
597 /*
598 * NOTE: We should never come here because rt2x00lib is
599 * supposed to catch this and send us the correct antenna
600 * explicitely. However we are nog going to bug about this.
601 * Instead, just default to antenna B.
602 */
603 case ANTENNA_B:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200604 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
605 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
606 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200607 break;
608 }
609
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200610 rt61pci_bbp_write(rt2x00dev, 77, r77);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700611 rt61pci_bbp_write(rt2x00dev, 3, r3);
612 rt61pci_bbp_write(rt2x00dev, 4, r4);
613}
614
615struct antenna_sel {
616 u8 word;
617 /*
618 * value[0] -> non-LNA
619 * value[1] -> LNA
620 */
621 u8 value[2];
622};
623
624static const struct antenna_sel antenna_sel_a[] = {
625 { 96, { 0x58, 0x78 } },
626 { 104, { 0x38, 0x48 } },
627 { 75, { 0xfe, 0x80 } },
628 { 86, { 0xfe, 0x80 } },
629 { 88, { 0xfe, 0x80 } },
630 { 35, { 0x60, 0x60 } },
631 { 97, { 0x58, 0x58 } },
632 { 98, { 0x58, 0x58 } },
633};
634
635static const struct antenna_sel antenna_sel_bg[] = {
636 { 96, { 0x48, 0x68 } },
637 { 104, { 0x2c, 0x3c } },
638 { 75, { 0xfe, 0x80 } },
639 { 86, { 0xfe, 0x80 } },
640 { 88, { 0xfe, 0x80 } },
641 { 35, { 0x50, 0x50 } },
642 { 97, { 0x48, 0x48 } },
643 { 98, { 0x48, 0x48 } },
644};
645
646static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200647 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700648{
649 const struct antenna_sel *sel;
650 unsigned int lna;
651 unsigned int i;
652 u32 reg;
653
Johannes Berg8318d782008-01-24 19:38:38 +0100654 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700655 sel = antenna_sel_a;
656 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700657 } else {
658 sel = antenna_sel_bg;
659 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700660 }
661
Mattias Nissleracaa4102007-10-27 13:41:53 +0200662 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
663 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
664
665 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
666
Ivo van Doornddc827f2007-10-13 16:26:42 +0200667 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
Johannes Berg8318d782008-01-24 19:38:38 +0100668 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
Ivo van Doornddc827f2007-10-13 16:26:42 +0200669 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
Johannes Berg8318d782008-01-24 19:38:38 +0100670 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
Ivo van Doornddc827f2007-10-13 16:26:42 +0200671
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700672 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
673
674 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
675 rt2x00_rf(&rt2x00dev->chip, RF5325))
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200676 rt61pci_config_antenna_5x(rt2x00dev, ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700677 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200678 rt61pci_config_antenna_2x(rt2x00dev, ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700679 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
680 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200681 rt61pci_config_antenna_2x(rt2x00dev, ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700682 else
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200683 rt61pci_config_antenna_2529(rt2x00dev, ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700684 }
685}
686
687static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200688 struct rt2x00lib_conf *libconf)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700689{
690 u32 reg;
691
692 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200693 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700694 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
695
696 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200697 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700698 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200699 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700700 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
701
702 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
703 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
704 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
705
706 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
707 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
708 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
709
710 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200711 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
712 libconf->conf->beacon_int * 16);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700713 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
714}
715
716static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100717 struct rt2x00lib_conf *libconf,
718 const unsigned int flags)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700719{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700720 if (flags & CONFIG_UPDATE_PHYMODE)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200721 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700722 if (flags & CONFIG_UPDATE_CHANNEL)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200723 rt61pci_config_channel(rt2x00dev, &libconf->rf,
724 libconf->conf->power_level);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700725 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200726 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700727 if (flags & CONFIG_UPDATE_ANTENNA)
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200728 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700729 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200730 rt61pci_config_duration(rt2x00dev, libconf);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700731}
732
733/*
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700734 * Link tuning
735 */
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200736static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
737 struct link_qual *qual)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700738{
739 u32 reg;
740
741 /*
742 * Update FCS error count from register.
743 */
744 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200745 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700746
747 /*
748 * Update False CCA count from register.
749 */
750 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200751 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700752}
753
754static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
755{
756 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
757 rt2x00dev->link.vgc_level = 0x20;
758}
759
760static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
761{
762 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
763 u8 r17;
764 u8 up_bound;
765 u8 low_bound;
766
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700767 rt61pci_bbp_read(rt2x00dev, 17, &r17);
768
769 /*
770 * Determine r17 bounds.
771 */
Ivo van Doorn14970742008-02-25 23:20:33 +0100772 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700773 low_bound = 0x28;
774 up_bound = 0x48;
775 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
776 low_bound += 0x10;
777 up_bound += 0x10;
778 }
779 } else {
780 low_bound = 0x20;
781 up_bound = 0x40;
782 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
783 low_bound += 0x10;
784 up_bound += 0x10;
785 }
786 }
787
788 /*
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100789 * If we are not associated, we should go straight to the
790 * dynamic CCA tuning.
791 */
792 if (!rt2x00dev->intf_associated)
793 goto dynamic_cca_tune;
794
795 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700796 * Special big-R17 for very short distance
797 */
798 if (rssi >= -35) {
799 if (r17 != 0x60)
800 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
801 return;
802 }
803
804 /*
805 * Special big-R17 for short distance
806 */
807 if (rssi >= -58) {
808 if (r17 != up_bound)
809 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
810 return;
811 }
812
813 /*
814 * Special big-R17 for middle-short distance
815 */
816 if (rssi >= -66) {
817 low_bound += 0x10;
818 if (r17 != low_bound)
819 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
820 return;
821 }
822
823 /*
824 * Special mid-R17 for middle distance
825 */
826 if (rssi >= -74) {
827 low_bound += 0x08;
828 if (r17 != low_bound)
829 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
830 return;
831 }
832
833 /*
834 * Special case: Change up_bound based on the rssi.
835 * Lower up_bound when rssi is weaker then -74 dBm.
836 */
837 up_bound -= 2 * (-74 - rssi);
838 if (low_bound > up_bound)
839 up_bound = low_bound;
840
841 if (r17 > up_bound) {
842 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
843 return;
844 }
845
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100846dynamic_cca_tune:
847
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700848 /*
849 * r17 does not yet exceed upper limit, continue and base
850 * the r17 tuning on the false CCA count.
851 */
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200852 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700853 if (++r17 > up_bound)
854 r17 = up_bound;
855 rt61pci_bbp_write(rt2x00dev, 17, r17);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200856 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700857 if (--r17 < low_bound)
858 r17 = low_bound;
859 rt61pci_bbp_write(rt2x00dev, 17, r17);
860 }
861}
862
863/*
864 * Firmware name function.
865 */
866static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
867{
868 char *fw_name;
869
870 switch (rt2x00dev->chip.rt) {
871 case RT2561:
872 fw_name = FIRMWARE_RT2561;
873 break;
874 case RT2561s:
875 fw_name = FIRMWARE_RT2561s;
876 break;
877 case RT2661:
878 fw_name = FIRMWARE_RT2661;
879 break;
880 default:
881 fw_name = NULL;
882 break;
883 }
884
885 return fw_name;
886}
887
888/*
889 * Initialization functions.
890 */
891static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
892 const size_t len)
893{
894 int i;
895 u32 reg;
896
897 /*
898 * Wait for stable hardware.
899 */
900 for (i = 0; i < 100; i++) {
901 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
902 if (reg)
903 break;
904 msleep(1);
905 }
906
907 if (!reg) {
908 ERROR(rt2x00dev, "Unstable hardware.\n");
909 return -EBUSY;
910 }
911
912 /*
913 * Prepare MCU and mailbox for firmware loading.
914 */
915 reg = 0;
916 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
917 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
918 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
919 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
920 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
921
922 /*
923 * Write firmware to device.
924 */
925 reg = 0;
926 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
927 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
928 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
929
930 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
931 data, len);
932
933 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
934 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
935
936 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
937 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
938
939 for (i = 0; i < 100; i++) {
940 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
941 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
942 break;
943 msleep(1);
944 }
945
946 if (i == 100) {
947 ERROR(rt2x00dev, "MCU Control register not ready.\n");
948 return -EBUSY;
949 }
950
951 /*
952 * Reset MAC and BBP registers.
953 */
954 reg = 0;
955 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
956 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
957 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
958
959 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
960 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
961 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
962 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
963
964 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
965 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
966 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
967
968 return 0;
969}
970
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100971static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn181d6902008-02-05 16:42:23 -0500972 struct queue_entry *entry)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700973{
Ivo van Doorn181d6902008-02-05 16:42:23 -0500974 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700975 u32 word;
976
Ivo van Doorn181d6902008-02-05 16:42:23 -0500977 rt2x00_desc_read(priv_rx->desc, 5, &word);
Ivo van Doorn30b3a232008-02-17 17:33:24 +0100978 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
979 priv_rx->data_dma);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500980 rt2x00_desc_write(priv_rx->desc, 5, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700981
Ivo van Doorn181d6902008-02-05 16:42:23 -0500982 rt2x00_desc_read(priv_rx->desc, 0, &word);
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100983 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500984 rt2x00_desc_write(priv_rx->desc, 0, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700985}
986
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100987static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn181d6902008-02-05 16:42:23 -0500988 struct queue_entry *entry)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700989{
Ivo van Doorn181d6902008-02-05 16:42:23 -0500990 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700991 u32 word;
992
Ivo van Doorn181d6902008-02-05 16:42:23 -0500993 rt2x00_desc_read(priv_tx->desc, 1, &word);
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100994 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500995 rt2x00_desc_write(priv_tx->desc, 1, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700996
Ivo van Doorn181d6902008-02-05 16:42:23 -0500997 rt2x00_desc_read(priv_tx->desc, 5, &word);
998 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100999 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001000 rt2x00_desc_write(priv_tx->desc, 5, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001001
Ivo van Doorn181d6902008-02-05 16:42:23 -05001002 rt2x00_desc_read(priv_tx->desc, 6, &word);
Ivo van Doorn30b3a232008-02-17 17:33:24 +01001003 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1004 priv_tx->data_dma);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001005 rt2x00_desc_write(priv_tx->desc, 6, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001006
Ivo van Doorn181d6902008-02-05 16:42:23 -05001007 rt2x00_desc_read(priv_tx->desc, 0, &word);
Ivo van Doorn837e7f22008-01-06 23:41:45 +01001008 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1009 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001010 rt2x00_desc_write(priv_tx->desc, 0, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001011}
1012
Ivo van Doorn181d6902008-02-05 16:42:23 -05001013static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001014{
Ivo van Doorn181d6902008-02-05 16:42:23 -05001015 struct queue_entry_priv_pci_rx *priv_rx;
1016 struct queue_entry_priv_pci_tx *priv_tx;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001017 u32 reg;
1018
1019 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001020 * Initialize registers.
1021 */
1022 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1023 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001024 rt2x00dev->tx[0].limit);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001025 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001026 rt2x00dev->tx[1].limit);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001027 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001028 rt2x00dev->tx[2].limit);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001029 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001030 rt2x00dev->tx[3].limit);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001031 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1032
1033 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001034 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001035 rt2x00dev->tx[0].desc_size / 4);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001036 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1037
Ivo van Doorn181d6902008-02-05 16:42:23 -05001038 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001039 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
Ivo van Doorn30b3a232008-02-17 17:33:24 +01001040 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1041 priv_tx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001042 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1043
Ivo van Doorn181d6902008-02-05 16:42:23 -05001044 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001045 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
Ivo van Doorn30b3a232008-02-17 17:33:24 +01001046 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1047 priv_tx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001048 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1049
Ivo van Doorn181d6902008-02-05 16:42:23 -05001050 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001051 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
Ivo van Doorn30b3a232008-02-17 17:33:24 +01001052 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1053 priv_tx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001054 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1055
Ivo van Doorn181d6902008-02-05 16:42:23 -05001056 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001057 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
Ivo van Doorn30b3a232008-02-17 17:33:24 +01001058 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1059 priv_tx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001060 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1061
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001062 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001063 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001064 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1065 rt2x00dev->rx->desc_size / 4);
1066 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1067 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1068
Ivo van Doorn181d6902008-02-05 16:42:23 -05001069 priv_rx = rt2x00dev->rx->entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001070 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
Ivo van Doorn30b3a232008-02-17 17:33:24 +01001071 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1072 priv_rx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001073 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1074
1075 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1076 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1077 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1078 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1079 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001080 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1081
1082 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1083 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1084 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1085 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1086 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001087 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1088
1089 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1090 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1091 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1092
1093 return 0;
1094}
1095
1096static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1097{
1098 u32 reg;
1099
1100 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1101 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1102 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1103 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1104 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1105
1106 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1107 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1108 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1109 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1110 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1111 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1112 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1113 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1114 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1115 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1116
1117 /*
1118 * CCK TXD BBP registers
1119 */
1120 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1121 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1122 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1123 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1124 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1125 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1126 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1127 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1128 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1129 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1130
1131 /*
1132 * OFDM TXD BBP registers
1133 */
1134 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1135 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1136 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1137 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1138 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1139 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1140 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1141 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1142
1143 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1144 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1145 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1146 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1147 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1148 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1149
1150 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1151 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1152 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1153 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1154 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1155 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1156
1157 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1158
1159 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1160
1161 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1162 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1163 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1164
1165 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1166
1167 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1168 return -EBUSY;
1169
1170 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1171
Ivo van Doorna9450b72008-02-03 15:53:40 +01001172 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1173 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1174 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1175 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1176
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001177 /*
1178 * Invalidate all Shared Keys (SEC_CSR0),
1179 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1180 */
1181 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1182 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1183 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1184
1185 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1186 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1187 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1188 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1189
1190 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1191
1192 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1193
1194 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1195
1196 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1197 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1198 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1199 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1200
1201 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1202 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1203 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1204 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1205
1206 /*
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01001207 * Clear all beacons
1208 * For the Beacon base registers we only need to clear
1209 * the first byte since that byte contains the VALID and OWNER
1210 * bits which (when set to 0) will invalidate the entire beacon.
1211 */
1212 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1213 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1214 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1215 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1216
1217 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001218 * We must clear the error counters.
1219 * These registers are cleared on read,
1220 * so we may pass a useless variable to store the value.
1221 */
1222 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1223 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1224 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1225
1226 /*
1227 * Reset MAC and BBP registers.
1228 */
1229 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1230 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1231 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1232 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1233
1234 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1235 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1236 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1237 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1238
1239 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1240 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1241 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1242
1243 return 0;
1244}
1245
1246static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1247{
1248 unsigned int i;
1249 u16 eeprom;
1250 u8 reg_id;
1251 u8 value;
1252
1253 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1254 rt61pci_bbp_read(rt2x00dev, 0, &value);
1255 if ((value != 0xff) && (value != 0x00))
1256 goto continue_csr_init;
1257 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1258 udelay(REGISTER_BUSY_DELAY);
1259 }
1260
1261 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1262 return -EACCES;
1263
1264continue_csr_init:
1265 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1266 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1267 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1268 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1269 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1270 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1271 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1272 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1273 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1274 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1275 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1276 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1277 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1278 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1279 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1280 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1281 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1282 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1283 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1284 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1285 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1286 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1287 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1288 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1289
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001290 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1291 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1292
1293 if (eeprom != 0xffff && eeprom != 0x0000) {
1294 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1295 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001296 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1297 }
1298 }
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001299
1300 return 0;
1301}
1302
1303/*
1304 * Device state switch handlers.
1305 */
1306static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1307 enum dev_state state)
1308{
1309 u32 reg;
1310
1311 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1312 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1313 state == STATE_RADIO_RX_OFF);
1314 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1315}
1316
1317static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1318 enum dev_state state)
1319{
1320 int mask = (state == STATE_RADIO_IRQ_OFF);
1321 u32 reg;
1322
1323 /*
1324 * When interrupts are being enabled, the interrupt registers
1325 * should clear the register to assure a clean state.
1326 */
1327 if (state == STATE_RADIO_IRQ_ON) {
1328 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1329 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1330
1331 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1332 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1333 }
1334
1335 /*
1336 * Only toggle the interrupts bits we are going to use.
1337 * Non-checked interrupt bits are disabled by default.
1338 */
1339 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1340 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1341 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1342 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1343 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1344 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1345
1346 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1347 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1348 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1349 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1350 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1351 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1352 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1353 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1354 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1355 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1356}
1357
1358static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1359{
1360 u32 reg;
1361
1362 /*
1363 * Initialize all registers.
1364 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001365 if (rt61pci_init_queues(rt2x00dev) ||
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001366 rt61pci_init_registers(rt2x00dev) ||
1367 rt61pci_init_bbp(rt2x00dev)) {
1368 ERROR(rt2x00dev, "Register initialization failed.\n");
1369 return -EIO;
1370 }
1371
1372 /*
1373 * Enable interrupts.
1374 */
1375 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1376
1377 /*
1378 * Enable RX.
1379 */
1380 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1381 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1382 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1383
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001384 return 0;
1385}
1386
1387static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1388{
1389 u32 reg;
1390
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001391 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1392
1393 /*
1394 * Disable synchronisation.
1395 */
1396 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1397
1398 /*
1399 * Cancel RX and TX.
1400 */
1401 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1402 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1403 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1404 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1405 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001406 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1407
1408 /*
1409 * Disable interrupts.
1410 */
1411 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1412}
1413
1414static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1415{
1416 u32 reg;
1417 unsigned int i;
1418 char put_to_sleep;
1419 char current_state;
1420
1421 put_to_sleep = (state != STATE_AWAKE);
1422
1423 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1424 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1425 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1426 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1427
1428 /*
1429 * Device is not guaranteed to be in the requested state yet.
1430 * We must wait until the register indicates that the
1431 * device has entered the correct state.
1432 */
1433 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1434 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1435 current_state =
1436 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1437 if (current_state == !put_to_sleep)
1438 return 0;
1439 msleep(10);
1440 }
1441
1442 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1443 "current device state %d.\n", !put_to_sleep, current_state);
1444
1445 return -EBUSY;
1446}
1447
1448static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1449 enum dev_state state)
1450{
1451 int retval = 0;
1452
1453 switch (state) {
1454 case STATE_RADIO_ON:
1455 retval = rt61pci_enable_radio(rt2x00dev);
1456 break;
1457 case STATE_RADIO_OFF:
1458 rt61pci_disable_radio(rt2x00dev);
1459 break;
1460 case STATE_RADIO_RX_ON:
Ivo van Doorn61667d82008-02-25 23:15:05 +01001461 case STATE_RADIO_RX_ON_LINK:
1462 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1463 break;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001464 case STATE_RADIO_RX_OFF:
Ivo van Doorn61667d82008-02-25 23:15:05 +01001465 case STATE_RADIO_RX_OFF_LINK:
1466 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001467 break;
1468 case STATE_DEEP_SLEEP:
1469 case STATE_SLEEP:
1470 case STATE_STANDBY:
1471 case STATE_AWAKE:
1472 retval = rt61pci_set_state(rt2x00dev, state);
1473 break;
1474 default:
1475 retval = -ENOTSUPP;
1476 break;
1477 }
1478
1479 return retval;
1480}
1481
1482/*
1483 * TX descriptor initialization
1484 */
1485static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
Ivo van Doorndd3193e2008-01-06 23:41:10 +01001486 struct sk_buff *skb,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001487 struct txentry_desc *txdesc,
Ivo van Doorndd3193e2008-01-06 23:41:10 +01001488 struct ieee80211_tx_control *control)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001489{
Ivo van Doorn181d6902008-02-05 16:42:23 -05001490 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
Ivo van Doorndd3193e2008-01-06 23:41:10 +01001491 __le32 *txd = skbdesc->desc;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001492 u32 word;
1493
1494 /*
1495 * Start writing the descriptor words.
1496 */
1497 rt2x00_desc_read(txd, 1, &word);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001498 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1499 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1500 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1501 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001502 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1503 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1504 rt2x00_desc_write(txd, 1, word);
1505
1506 rt2x00_desc_read(txd, 2, &word);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001507 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1508 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1509 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1510 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001511 rt2x00_desc_write(txd, 2, word);
1512
1513 rt2x00_desc_read(txd, 5, &word);
1514 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
Ivo van Doornac1aa7e2008-02-17 17:31:48 +01001515 TXPOWER_TO_DEV(rt2x00dev->tx_power));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001516 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1517 rt2x00_desc_write(txd, 5, word);
1518
Adam Bakerd7bafff2008-02-03 15:46:24 +01001519 if (skbdesc->desc_len > TXINFO_SIZE) {
1520 rt2x00_desc_read(txd, 11, &word);
1521 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1522 rt2x00_desc_write(txd, 11, word);
1523 }
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001524
1525 rt2x00_desc_read(txd, 0, &word);
1526 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1527 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1528 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001529 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001530 rt2x00_set_field32(&word, TXD_W0_ACK,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001531 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001532 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001533 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001534 rt2x00_set_field32(&word, TXD_W0_OFDM,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001535 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1536 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001537 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1538 !!(control->flags &
1539 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1540 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
Ivo van Doorndd3193e2008-01-06 23:41:10 +01001541 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001542 rt2x00_set_field32(&word, TXD_W0_BURST,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001543 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001544 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1545 rt2x00_desc_write(txd, 0, word);
1546}
1547
1548/*
1549 * TX data initialization
1550 */
1551static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5957da42008-02-03 15:54:57 +01001552 const unsigned int queue)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001553{
1554 u32 reg;
1555
Ivo van Doorn5957da42008-02-03 15:54:57 +01001556 if (queue == RT2X00_BCN_QUEUE_BEACON) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001557 /*
1558 * For Wi-Fi faily generated beacons between participating
1559 * stations. Set TBTT phase adaptive adjustment step to 8us.
1560 */
1561 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1562
1563 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1564 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1565 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1566 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1567 }
1568 return;
1569 }
1570
1571 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
Ivo van Doornddc827f2007-10-13 16:26:42 +02001572 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1573 (queue == IEEE80211_TX_QUEUE_DATA0));
1574 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1575 (queue == IEEE80211_TX_QUEUE_DATA1));
1576 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1577 (queue == IEEE80211_TX_QUEUE_DATA2));
1578 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1579 (queue == IEEE80211_TX_QUEUE_DATA3));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001580 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1581}
1582
1583/*
1584 * RX control handlers
1585 */
1586static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1587{
1588 u16 eeprom;
1589 u8 offset;
1590 u8 lna;
1591
1592 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1593 switch (lna) {
1594 case 3:
1595 offset = 90;
1596 break;
1597 case 2:
1598 offset = 74;
1599 break;
1600 case 1:
1601 offset = 64;
1602 break;
1603 default:
1604 return 0;
1605 }
1606
Johannes Berg8318d782008-01-24 19:38:38 +01001607 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001608 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1609 offset += 14;
1610
1611 if (lna == 3 || lna == 2)
1612 offset += 10;
1613
1614 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1615 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1616 } else {
1617 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1618 offset += 14;
1619
1620 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1621 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1622 }
1623
1624 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1625}
1626
Ivo van Doorn181d6902008-02-05 16:42:23 -05001627static void rt61pci_fill_rxdone(struct queue_entry *entry,
1628 struct rxdone_entry_desc *rxdesc)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001629{
Ivo van Doorn181d6902008-02-05 16:42:23 -05001630 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001631 u32 word0;
1632 u32 word1;
1633
Ivo van Doorn181d6902008-02-05 16:42:23 -05001634 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1635 rt2x00_desc_read(priv_rx->desc, 1, &word1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001636
Ivo van Doorn181d6902008-02-05 16:42:23 -05001637 rxdesc->flags = 0;
Johannes Berg4150c572007-09-17 01:29:23 -04001638 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
Ivo van Doorn181d6902008-02-05 16:42:23 -05001639 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001640
1641 /*
1642 * Obtain the status about this packet.
1643 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001644 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1645 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1646 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1647 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1648 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001649}
1650
1651/*
1652 * Interrupt functions.
1653 */
1654static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1655{
Ivo van Doorn181d6902008-02-05 16:42:23 -05001656 struct data_queue *queue;
1657 struct queue_entry *entry;
1658 struct queue_entry *entry_done;
1659 struct queue_entry_priv_pci_tx *priv_tx;
1660 struct txdone_entry_desc txdesc;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001661 u32 word;
1662 u32 reg;
1663 u32 old_reg;
1664 int type;
1665 int index;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001666
1667 /*
1668 * During each loop we will compare the freshly read
1669 * STA_CSR4 register value with the value read from
1670 * the previous loop. If the 2 values are equal then
1671 * we should stop processing because the chance it
1672 * quite big that the device has been unplugged and
1673 * we risk going into an endless loop.
1674 */
1675 old_reg = 0;
1676
1677 while (1) {
1678 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1679 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1680 break;
1681
1682 if (old_reg == reg)
1683 break;
1684 old_reg = reg;
1685
1686 /*
1687 * Skip this entry when it contains an invalid
Ivo van Doorn181d6902008-02-05 16:42:23 -05001688 * queue identication number.
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001689 */
1690 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001691 queue = rt2x00queue_get_queue(rt2x00dev, type);
1692 if (unlikely(!queue))
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001693 continue;
1694
1695 /*
1696 * Skip this entry when it contains an invalid
1697 * index number.
1698 */
1699 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001700 if (unlikely(index >= queue->limit))
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001701 continue;
1702
Ivo van Doorn181d6902008-02-05 16:42:23 -05001703 entry = &queue->entries[index];
1704 priv_tx = entry->priv_data;
1705 rt2x00_desc_read(priv_tx->desc, 0, &word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001706
1707 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1708 !rt2x00_get_field32(word, TXD_W0_VALID))
1709 return;
1710
Ivo van Doorn181d6902008-02-05 16:42:23 -05001711 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
Mattias Nissler62bc0602007-11-12 15:03:12 +01001712 while (entry != entry_done) {
Ivo van Doorn181d6902008-02-05 16:42:23 -05001713 /* Catch up.
1714 * Just report any entries we missed as failed.
1715 */
Mattias Nissler62bc0602007-11-12 15:03:12 +01001716 WARNING(rt2x00dev,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001717 "TX status report missed for entry %d\n",
1718 entry_done->entry_idx);
1719
1720 txdesc.status = TX_FAIL_OTHER;
1721 txdesc.retry = 0;
1722
1723 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1724 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
Mattias Nissler62bc0602007-11-12 15:03:12 +01001725 }
1726
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001727 /*
1728 * Obtain the status about this packet.
1729 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001730 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1731 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001732
Ivo van Doorn181d6902008-02-05 16:42:23 -05001733 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001734 }
1735}
1736
1737static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1738{
1739 struct rt2x00_dev *rt2x00dev = dev_instance;
1740 u32 reg_mcu;
1741 u32 reg;
1742
1743 /*
1744 * Get the interrupt sources & saved to local variable.
1745 * Write register value back to clear pending interrupts.
1746 */
1747 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1748 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1749
1750 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1751 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1752
1753 if (!reg && !reg_mcu)
1754 return IRQ_NONE;
1755
1756 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1757 return IRQ_HANDLED;
1758
1759 /*
1760 * Handle interrupts, walk through all bits
1761 * and run the tasks, the bits are checked in order of
1762 * priority.
1763 */
1764
1765 /*
1766 * 1 - Rx ring done interrupt.
1767 */
1768 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1769 rt2x00pci_rxdone(rt2x00dev);
1770
1771 /*
1772 * 2 - Tx ring done interrupt.
1773 */
1774 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1775 rt61pci_txdone(rt2x00dev);
1776
1777 /*
1778 * 3 - Handle MCU command done.
1779 */
1780 if (reg_mcu)
1781 rt2x00pci_register_write(rt2x00dev,
1782 M2H_CMD_DONE_CSR, 0xffffffff);
1783
1784 return IRQ_HANDLED;
1785}
1786
1787/*
1788 * Device probe functions.
1789 */
1790static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1791{
1792 struct eeprom_93cx6 eeprom;
1793 u32 reg;
1794 u16 word;
1795 u8 *mac;
1796 s8 value;
1797
1798 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1799
1800 eeprom.data = rt2x00dev;
1801 eeprom.register_read = rt61pci_eepromregister_read;
1802 eeprom.register_write = rt61pci_eepromregister_write;
1803 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1804 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1805 eeprom.reg_data_in = 0;
1806 eeprom.reg_data_out = 0;
1807 eeprom.reg_data_clock = 0;
1808 eeprom.reg_chip_select = 0;
1809
1810 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1811 EEPROM_SIZE / sizeof(u16));
1812
1813 /*
1814 * Start validation of the data that has been read.
1815 */
1816 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1817 if (!is_valid_ether_addr(mac)) {
Joe Perches0795af52007-10-03 17:59:30 -07001818 DECLARE_MAC_BUF(macbuf);
1819
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001820 random_ether_addr(mac);
Joe Perches0795af52007-10-03 17:59:30 -07001821 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001822 }
1823
1824 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1825 if (word == 0xffff) {
1826 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
Ivo van Doorn362f3b62007-10-13 16:26:18 +02001827 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1828 ANTENNA_B);
1829 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1830 ANTENNA_B);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001831 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1832 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1833 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1834 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1835 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1836 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1837 }
1838
1839 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1840 if (word == 0xffff) {
1841 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1842 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1843 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1844 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1845 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1846 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1847 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1848 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1849 }
1850
1851 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1852 if (word == 0xffff) {
1853 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1854 LED_MODE_DEFAULT);
1855 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1856 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1857 }
1858
1859 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1860 if (word == 0xffff) {
1861 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1862 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1863 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1864 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1865 }
1866
1867 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1868 if (word == 0xffff) {
1869 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1870 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1871 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1872 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1873 } else {
1874 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1875 if (value < -10 || value > 10)
1876 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1877 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1878 if (value < -10 || value > 10)
1879 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1880 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1881 }
1882
1883 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1884 if (word == 0xffff) {
1885 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1886 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1887 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
Ivo van Doorn417f4122008-02-10 22:50:58 +01001888 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001889 } else {
1890 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1891 if (value < -10 || value > 10)
1892 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1893 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1894 if (value < -10 || value > 10)
1895 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1896 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1897 }
1898
1899 return 0;
1900}
1901
1902static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1903{
1904 u32 reg;
1905 u16 value;
1906 u16 eeprom;
1907 u16 device;
1908
1909 /*
1910 * Read EEPROM word for configuration.
1911 */
1912 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1913
1914 /*
1915 * Identify RF chipset.
1916 * To determine the RT chip we have to read the
1917 * PCI header of the device.
1918 */
1919 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1920 PCI_CONFIG_HEADER_DEVICE, &device);
1921 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1922 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1923 rt2x00_set_chip(rt2x00dev, device, value, reg);
1924
1925 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1926 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1927 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1928 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1929 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1930 return -ENODEV;
1931 }
1932
1933 /*
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +02001934 * Determine number of antenna's.
1935 */
1936 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1937 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1938
1939 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001940 * Identify default antenna configuration.
1941 */
Ivo van Doornaddc81bd2007-10-13 16:26:23 +02001942 rt2x00dev->default_ant.tx =
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001943 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
Ivo van Doornaddc81bd2007-10-13 16:26:23 +02001944 rt2x00dev->default_ant.rx =
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001945 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1946
1947 /*
1948 * Read the Frame type.
1949 */
1950 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1951 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1952
1953 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001954 * Detect if this device has an hardware controlled radio.
1955 */
Ivo van Doorn81873e92007-10-06 14:14:06 +02001956#ifdef CONFIG_RT61PCI_RFKILL
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001957 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
Ivo van Doorn066cb632007-09-25 20:55:39 +02001958 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
Ivo van Doorn81873e92007-10-06 14:14:06 +02001959#endif /* CONFIG_RT61PCI_RFKILL */
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001960
1961 /*
1962 * Read frequency offset and RF programming sequence.
1963 */
1964 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1965 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1966 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1967
1968 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1969
1970 /*
1971 * Read external LNA informations.
1972 */
1973 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1974
1975 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1976 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1977 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1978 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1979
1980 /*
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +02001981 * When working with a RF2529 chip without double antenna
1982 * the antenna settings should be gathered from the NIC
1983 * eeprom word.
1984 */
1985 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
1986 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
1987 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
1988 case 0:
1989 rt2x00dev->default_ant.tx = ANTENNA_B;
1990 rt2x00dev->default_ant.rx = ANTENNA_A;
1991 break;
1992 case 1:
1993 rt2x00dev->default_ant.tx = ANTENNA_B;
1994 rt2x00dev->default_ant.rx = ANTENNA_B;
1995 break;
1996 case 2:
1997 rt2x00dev->default_ant.tx = ANTENNA_A;
1998 rt2x00dev->default_ant.rx = ANTENNA_A;
1999 break;
2000 case 3:
2001 rt2x00dev->default_ant.tx = ANTENNA_A;
2002 rt2x00dev->default_ant.rx = ANTENNA_B;
2003 break;
2004 }
2005
2006 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2007 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2008 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2009 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2010 }
2011
2012 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002013 * Store led settings, for correct led behaviour.
2014 * If the eeprom value is invalid,
2015 * switch to default led mode.
2016 */
Ivo van Doorna9450b72008-02-03 15:53:40 +01002017#ifdef CONFIG_RT61PCI_LEDS
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002018 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2019
Ivo van Doorna9450b72008-02-03 15:53:40 +01002020 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002021
Ivo van Doorna9450b72008-02-03 15:53:40 +01002022 switch (value) {
2023 case LED_MODE_TXRX_ACTIVITY:
2024 case LED_MODE_ASUS:
2025 case LED_MODE_ALPHA:
2026 case LED_MODE_DEFAULT:
2027 rt2x00dev->led_flags =
2028 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2029 break;
2030 case LED_MODE_SIGNAL_STRENGTH:
2031 rt2x00dev->led_flags =
2032 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2033 LED_SUPPORT_QUALITY;
2034 break;
2035 }
2036
2037 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2038 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002039 rt2x00_get_field16(eeprom,
2040 EEPROM_LED_POLARITY_GPIO_0));
Ivo van Doorna9450b72008-02-03 15:53:40 +01002041 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002042 rt2x00_get_field16(eeprom,
2043 EEPROM_LED_POLARITY_GPIO_1));
Ivo van Doorna9450b72008-02-03 15:53:40 +01002044 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002045 rt2x00_get_field16(eeprom,
2046 EEPROM_LED_POLARITY_GPIO_2));
Ivo van Doorna9450b72008-02-03 15:53:40 +01002047 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002048 rt2x00_get_field16(eeprom,
2049 EEPROM_LED_POLARITY_GPIO_3));
Ivo van Doorna9450b72008-02-03 15:53:40 +01002050 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002051 rt2x00_get_field16(eeprom,
2052 EEPROM_LED_POLARITY_GPIO_4));
Ivo van Doorna9450b72008-02-03 15:53:40 +01002053 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002054 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
Ivo van Doorna9450b72008-02-03 15:53:40 +01002055 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002056 rt2x00_get_field16(eeprom,
2057 EEPROM_LED_POLARITY_RDY_G));
Ivo van Doorna9450b72008-02-03 15:53:40 +01002058 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002059 rt2x00_get_field16(eeprom,
2060 EEPROM_LED_POLARITY_RDY_A));
Ivo van Doorna9450b72008-02-03 15:53:40 +01002061#endif /* CONFIG_RT61PCI_LEDS */
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002062
2063 return 0;
2064}
2065
2066/*
2067 * RF value list for RF5225 & RF5325
2068 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2069 */
2070static const struct rf_channel rf_vals_noseq[] = {
2071 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2072 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2073 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2074 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2075 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2076 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2077 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2078 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2079 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2080 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2081 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2082 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2083 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2084 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2085
2086 /* 802.11 UNI / HyperLan 2 */
2087 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2088 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2089 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2090 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2091 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2092 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2093 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2094 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2095
2096 /* 802.11 HyperLan 2 */
2097 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2098 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2099 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2100 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2101 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2102 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2103 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2104 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2105 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2106 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2107
2108 /* 802.11 UNII */
2109 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2110 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2111 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2112 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2113 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2114 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2115
2116 /* MMAC(Japan)J52 ch 34,38,42,46 */
2117 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2118 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2119 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2120 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2121};
2122
2123/*
2124 * RF value list for RF5225 & RF5325
2125 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2126 */
2127static const struct rf_channel rf_vals_seq[] = {
2128 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2129 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2130 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2131 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2132 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2133 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2134 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2135 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2136 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2137 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2138 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2139 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2140 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2141 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2142
2143 /* 802.11 UNI / HyperLan 2 */
2144 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2145 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2146 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2147 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2148 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2149 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2150 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2151 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2152
2153 /* 802.11 HyperLan 2 */
2154 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2155 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2156 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2157 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2158 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2159 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2160 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2161 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2162 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2163 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2164
2165 /* 802.11 UNII */
2166 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2167 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2168 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2169 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2170 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2171 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2172
2173 /* MMAC(Japan)J52 ch 34,38,42,46 */
2174 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2175 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2176 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2177 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2178};
2179
2180static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2181{
2182 struct hw_mode_spec *spec = &rt2x00dev->spec;
2183 u8 *txpower;
2184 unsigned int i;
2185
2186 /*
2187 * Initialize all hw fields.
2188 */
2189 rt2x00dev->hw->flags =
2190 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
Johannes Berg4150c572007-09-17 01:29:23 -04002191 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002192 rt2x00dev->hw->extra_tx_headroom = 0;
2193 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2194 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
Ivo van Doorn871ff6e2008-02-03 15:51:47 +01002195 rt2x00dev->hw->queues = 4;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002196
2197 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2198 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2199 rt2x00_eeprom_addr(rt2x00dev,
2200 EEPROM_MAC_ADDR_0));
2201
2202 /*
2203 * Convert tx_power array in eeprom.
2204 */
2205 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2206 for (i = 0; i < 14; i++)
2207 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2208
2209 /*
2210 * Initialize hw_mode information.
2211 */
Ivo van Doorn31562e82008-02-17 17:35:05 +01002212 spec->supported_bands = SUPPORT_BAND_2GHZ;
2213 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002214 spec->tx_power_a = NULL;
2215 spec->tx_power_bg = txpower;
2216 spec->tx_power_default = DEFAULT_TXPOWER;
2217
2218 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2219 spec->num_channels = 14;
2220 spec->channels = rf_vals_noseq;
2221 } else {
2222 spec->num_channels = 14;
2223 spec->channels = rf_vals_seq;
2224 }
2225
2226 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2227 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
Ivo van Doorn31562e82008-02-17 17:35:05 +01002228 spec->supported_bands |= SUPPORT_BAND_5GHZ;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002229 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2230
2231 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2232 for (i = 0; i < 14; i++)
2233 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2234
2235 spec->tx_power_a = txpower;
2236 }
2237}
2238
2239static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2240{
2241 int retval;
2242
2243 /*
2244 * Allocate eeprom data.
2245 */
2246 retval = rt61pci_validate_eeprom(rt2x00dev);
2247 if (retval)
2248 return retval;
2249
2250 retval = rt61pci_init_eeprom(rt2x00dev);
2251 if (retval)
2252 return retval;
2253
2254 /*
2255 * Initialize hw specifications.
2256 */
2257 rt61pci_probe_hw_mode(rt2x00dev);
2258
2259 /*
Ivo van Doorn9404ef32008-02-03 15:48:38 +01002260 * This device requires firmware.
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002261 */
Ivo van Doorn066cb632007-09-25 20:55:39 +02002262 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
Ivo van Doorn9404ef32008-02-03 15:48:38 +01002263 __set_bit(DRIVER_REQUIRE_FIRMWARE_CRC_ITU_T, &rt2x00dev->flags);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002264
2265 /*
2266 * Set the rssi offset.
2267 */
2268 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2269
2270 return 0;
2271}
2272
2273/*
2274 * IEEE80211 stack callback functions.
2275 */
Johannes Berg4150c572007-09-17 01:29:23 -04002276static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2277 unsigned int changed_flags,
2278 unsigned int *total_flags,
2279 int mc_count,
2280 struct dev_addr_list *mc_list)
2281{
2282 struct rt2x00_dev *rt2x00dev = hw->priv;
Johannes Berg4150c572007-09-17 01:29:23 -04002283 u32 reg;
2284
2285 /*
2286 * Mask off any flags we are going to ignore from
2287 * the total_flags field.
2288 */
2289 *total_flags &=
2290 FIF_ALLMULTI |
2291 FIF_FCSFAIL |
2292 FIF_PLCPFAIL |
2293 FIF_CONTROL |
2294 FIF_OTHER_BSS |
2295 FIF_PROMISC_IN_BSS;
2296
2297 /*
2298 * Apply some rules to the filters:
2299 * - Some filters imply different filters to be set.
2300 * - Some things we can't filter out at all.
Johannes Berg4150c572007-09-17 01:29:23 -04002301 */
2302 if (mc_count)
2303 *total_flags |= FIF_ALLMULTI;
Ivo van Doorn5886d0d2007-10-06 14:13:38 +02002304 if (*total_flags & FIF_OTHER_BSS ||
2305 *total_flags & FIF_PROMISC_IN_BSS)
Johannes Berg4150c572007-09-17 01:29:23 -04002306 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
Johannes Berg4150c572007-09-17 01:29:23 -04002307
2308 /*
2309 * Check if there is any work left for us.
2310 */
Ivo van Doorn3c4f2082008-01-06 23:40:49 +01002311 if (rt2x00dev->packet_filter == *total_flags)
Johannes Berg4150c572007-09-17 01:29:23 -04002312 return;
Ivo van Doorn3c4f2082008-01-06 23:40:49 +01002313 rt2x00dev->packet_filter = *total_flags;
Johannes Berg4150c572007-09-17 01:29:23 -04002314
2315 /*
2316 * Start configuration steps.
2317 * Note that the version error will always be dropped
2318 * and broadcast frames will always be accepted since
2319 * there is no filter for it at this time.
2320 */
2321 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2322 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2323 !(*total_flags & FIF_FCSFAIL));
2324 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2325 !(*total_flags & FIF_PLCPFAIL));
2326 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2327 !(*total_flags & FIF_CONTROL));
2328 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2329 !(*total_flags & FIF_PROMISC_IN_BSS));
2330 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2331 !(*total_flags & FIF_PROMISC_IN_BSS));
2332 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2333 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2334 !(*total_flags & FIF_ALLMULTI));
Ivo van Doorne5422392008-02-17 17:33:13 +01002335 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
2336 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
2337 !(*total_flags & FIF_CONTROL));
Johannes Berg4150c572007-09-17 01:29:23 -04002338 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2339}
2340
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002341static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2342 u32 short_retry, u32 long_retry)
2343{
2344 struct rt2x00_dev *rt2x00dev = hw->priv;
2345 u32 reg;
2346
2347 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2348 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2349 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2350 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2351
2352 return 0;
2353}
2354
2355static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2356{
2357 struct rt2x00_dev *rt2x00dev = hw->priv;
2358 u64 tsf;
2359 u32 reg;
2360
2361 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2362 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2363 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2364 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2365
2366 return tsf;
2367}
2368
Ivo van Doorn24845912007-09-25 20:53:43 +02002369static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002370 struct ieee80211_tx_control *control)
2371{
2372 struct rt2x00_dev *rt2x00dev = hw->priv;
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002373 struct rt2x00_intf *intf = vif_to_intf(control->vif);
Ivo van Doorn181d6902008-02-05 16:42:23 -05002374 struct skb_frame_desc *skbdesc;
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002375 unsigned int beacon_base;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002376
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002377 if (unlikely(!intf->beacon))
2378 return -ENOBUFS;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002379
2380 /*
2381 * We need to append the descriptor in front of the
2382 * beacon frame.
2383 */
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002384 if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2385 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2386 0, GFP_ATOMIC)) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002387 dev_kfree_skb(skb);
2388 return -ENOMEM;
2389 }
2390 }
2391
2392 /*
Ivo van Doorn08992f72008-01-24 01:56:25 -08002393 * Add the descriptor in front of the skb.
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002394 */
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002395 skb_push(skb, intf->beacon->queue->desc_size);
2396 memset(skb->data, 0, intf->beacon->queue->desc_size);
Ivo van Doornc22eb872007-10-06 14:18:22 +02002397
Ivo van Doorn08992f72008-01-24 01:56:25 -08002398 /*
2399 * Fill in skb descriptor
2400 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05002401 skbdesc = get_skb_frame_desc(skb);
2402 memset(skbdesc, 0, sizeof(*skbdesc));
Ivo van Doornbaf26a72008-02-17 17:32:08 +01002403 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002404 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2405 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
Ivo van Doorn181d6902008-02-05 16:42:23 -05002406 skbdesc->desc = skb->data;
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002407 skbdesc->desc_len = intf->beacon->queue->desc_size;
2408 skbdesc->entry = intf->beacon;
Ivo van Doorn08992f72008-01-24 01:56:25 -08002409
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002410 /*
Ivo van Doorn5957da42008-02-03 15:54:57 +01002411 * mac80211 doesn't provide the control->queue variable
2412 * for beacons. Set our own queue identification so
2413 * it can be used during descriptor initialization.
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002414 */
Ivo van Doorn5957da42008-02-03 15:54:57 +01002415 control->queue = RT2X00_BCN_QUEUE_BEACON;
Ivo van Doorn08992f72008-01-24 01:56:25 -08002416 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002417
2418 /*
2419 * Write entire beacon with descriptor to register,
2420 * and kick the beacon generator.
2421 */
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002422 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2423 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
Ivo van Doorn9ee8f572007-10-06 14:15:20 +02002424 skb->data, skb->len);
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002425 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002426
2427 return 0;
2428}
2429
2430static const struct ieee80211_ops rt61pci_mac80211_ops = {
2431 .tx = rt2x00mac_tx,
Johannes Berg4150c572007-09-17 01:29:23 -04002432 .start = rt2x00mac_start,
2433 .stop = rt2x00mac_stop,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002434 .add_interface = rt2x00mac_add_interface,
2435 .remove_interface = rt2x00mac_remove_interface,
2436 .config = rt2x00mac_config,
2437 .config_interface = rt2x00mac_config_interface,
Johannes Berg4150c572007-09-17 01:29:23 -04002438 .configure_filter = rt61pci_configure_filter,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002439 .get_stats = rt2x00mac_get_stats,
2440 .set_retry_limit = rt61pci_set_retry_limit,
Johannes Berg471b3ef2007-12-28 14:32:58 +01002441 .bss_info_changed = rt2x00mac_bss_info_changed,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002442 .conf_tx = rt2x00mac_conf_tx,
2443 .get_tx_stats = rt2x00mac_get_tx_stats,
2444 .get_tsf = rt61pci_get_tsf,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002445 .beacon_update = rt61pci_beacon_update,
2446};
2447
2448static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2449 .irq_handler = rt61pci_interrupt,
2450 .probe_hw = rt61pci_probe_hw,
2451 .get_firmware_name = rt61pci_get_firmware_name,
2452 .load_firmware = rt61pci_load_firmware,
2453 .initialize = rt2x00pci_initialize,
2454 .uninitialize = rt2x00pci_uninitialize,
Ivo van Doorn837e7f22008-01-06 23:41:45 +01002455 .init_rxentry = rt61pci_init_rxentry,
2456 .init_txentry = rt61pci_init_txentry,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002457 .set_device_state = rt61pci_set_device_state,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002458 .rfkill_poll = rt61pci_rfkill_poll,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002459 .link_stats = rt61pci_link_stats,
2460 .reset_tuner = rt61pci_reset_tuner,
2461 .link_tuner = rt61pci_link_tuner,
Ivo van Doorna9450b72008-02-03 15:53:40 +01002462 .led_brightness = rt61pci_led_brightness,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002463 .write_tx_desc = rt61pci_write_tx_desc,
2464 .write_tx_data = rt2x00pci_write_tx_data,
2465 .kick_tx_queue = rt61pci_kick_tx_queue,
2466 .fill_rxdone = rt61pci_fill_rxdone,
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002467 .config_intf = rt61pci_config_intf,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +02002468 .config_preamble = rt61pci_config_preamble,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002469 .config = rt61pci_config,
2470};
2471
Ivo van Doorn181d6902008-02-05 16:42:23 -05002472static const struct data_queue_desc rt61pci_queue_rx = {
2473 .entry_num = RX_ENTRIES,
2474 .data_size = DATA_FRAME_SIZE,
2475 .desc_size = RXD_DESC_SIZE,
2476 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2477};
2478
2479static const struct data_queue_desc rt61pci_queue_tx = {
2480 .entry_num = TX_ENTRIES,
2481 .data_size = DATA_FRAME_SIZE,
2482 .desc_size = TXD_DESC_SIZE,
2483 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2484};
2485
2486static const struct data_queue_desc rt61pci_queue_bcn = {
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002487 .entry_num = 4 * BEACON_ENTRIES,
Ivo van Doorn181d6902008-02-05 16:42:23 -05002488 .data_size = MGMT_FRAME_SIZE,
2489 .desc_size = TXINFO_SIZE,
2490 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2491};
2492
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002493static const struct rt2x00_ops rt61pci_ops = {
Ivo van Doorn23601572007-11-27 21:47:34 +01002494 .name = KBUILD_MODNAME,
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01002495 .max_sta_intf = 1,
2496 .max_ap_intf = 4,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002497 .eeprom_size = EEPROM_SIZE,
2498 .rf_size = RF_SIZE,
Ivo van Doorn181d6902008-02-05 16:42:23 -05002499 .rx = &rt61pci_queue_rx,
2500 .tx = &rt61pci_queue_tx,
2501 .bcn = &rt61pci_queue_bcn,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002502 .lib = &rt61pci_rt2x00_ops,
2503 .hw = &rt61pci_mac80211_ops,
2504#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2505 .debugfs = &rt61pci_rt2x00debug,
2506#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2507};
2508
2509/*
2510 * RT61pci module information.
2511 */
2512static struct pci_device_id rt61pci_device_table[] = {
2513 /* RT2561s */
2514 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2515 /* RT2561 v2 */
2516 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2517 /* RT2661 */
2518 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2519 { 0, }
2520};
2521
2522MODULE_AUTHOR(DRV_PROJECT);
2523MODULE_VERSION(DRV_VERSION);
2524MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2525MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2526 "PCI & PCMCIA chipset based cards");
2527MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2528MODULE_FIRMWARE(FIRMWARE_RT2561);
2529MODULE_FIRMWARE(FIRMWARE_RT2561s);
2530MODULE_FIRMWARE(FIRMWARE_RT2661);
2531MODULE_LICENSE("GPL");
2532
2533static struct pci_driver rt61pci_driver = {
Ivo van Doorn23601572007-11-27 21:47:34 +01002534 .name = KBUILD_MODNAME,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002535 .id_table = rt61pci_device_table,
2536 .probe = rt2x00pci_probe,
2537 .remove = __devexit_p(rt2x00pci_remove),
2538 .suspend = rt2x00pci_suspend,
2539 .resume = rt2x00pci_resume,
2540};
2541
2542static int __init rt61pci_init(void)
2543{
2544 return pci_register_driver(&rt61pci_driver);
2545}
2546
2547static void __exit rt61pci_exit(void)
2548{
2549 pci_unregister_driver(&rt61pci_driver);
2550}
2551
2552module_init(rt61pci_init);
2553module_exit(rt61pci_exit);