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Kim Phillips18a1e4c2007-01-30 16:09:13 -06001/*
2 * MPC8323E EMDS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
Timur Tabi845cf502008-01-09 17:35:05 -060010
11 * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
12 * this:
13 *
14 * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
15 * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
16 * next to the serial ports.
17 * 3) Solder a wire from U61-22 to P19K-22.
18 *
19 * Note that there's a typo in the schematic. The board labels the last column
20 * of pins "P19K", but in the schematic, that column is called "P19J". So if
21 * you're going by the schematic, the pin is called "P19J-K22".
Kim Phillips18a1e4c2007-01-30 16:09:13 -060022 */
23
Paul Gortmakercda13dd2008-01-28 16:09:36 -050024/dts-v1/;
25
Kim Phillips18a1e4c2007-01-30 16:09:13 -060026/ {
27 model = "MPC8323EMDS";
Kumar Galad71a1dc2007-02-16 09:57:22 -060028 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
Kim Phillips18a1e4c2007-01-30 16:09:13 -060029 #address-cells = <1>;
30 #size-cells = <1>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060031
Kumar Galaea082fa2007-12-12 01:46:12 -060032 aliases {
33 ethernet0 = &enet0;
34 ethernet1 = &enet1;
35 serial0 = &serial0;
36 serial1 = &serial1;
37 pci0 = &pci0;
38 };
39
Kim Phillips18a1e4c2007-01-30 16:09:13 -060040 cpus {
Kim Phillips18a1e4c2007-01-30 16:09:13 -060041 #address-cells = <1>;
42 #size-cells = <0>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060043
44 PowerPC,8323@0 {
45 device_type = "cpu";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050046 reg = <0x0>;
47 d-cache-line-size = <32>; // 32 bytes
48 i-cache-line-size = <32>; // 32 bytes
49 d-cache-size = <16384>; // L1, 16K
50 i-cache-size = <16384>; // L1, 16K
Kim Phillips18a1e4c2007-01-30 16:09:13 -060051 timebase-frequency = <0>;
52 bus-frequency = <0>;
53 clock-frequency = <0>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060054 };
55 };
56
57 memory {
58 device_type = "memory";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050059 reg = <0x00000000 0x08000000>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060060 };
61
62 bcsr@f8000000 {
Anton Vorontsovfd657ef2008-10-18 04:23:52 +040063 compatible = "fsl,mpc8323mds-bcsr";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050064 reg = <0xf8000000 0x8000>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060065 };
66
67 soc8323@e0000000 {
68 #address-cells = <1>;
69 #size-cells = <1>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060070 device_type = "soc";
Kim Phillipscf0d19f2008-07-29 15:29:24 -050071 compatible = "simple-bus";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050072 ranges = <0x0 0xe0000000 0x00100000>;
73 reg = <0xe0000000 0x00000200>;
74 bus-frequency = <132000000>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060075
76 wdt@200 {
77 device_type = "watchdog";
78 compatible = "mpc83xx_wdt";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050079 reg = <0x200 0x100>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060080 };
81
Anton Vorontsov1f8a25d2009-09-16 01:44:02 +040082 pmc: power@b00 {
83 compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
84 reg = <0xb00 0x100 0xa00 0x100>;
85 interrupts = <80 0x8>;
86 interrupt-parent = <&ipic>;
87 };
88
Kim Phillips18a1e4c2007-01-30 16:09:13 -060089 i2c@3000 {
Kim Phillips27f498072007-11-08 13:37:06 -060090 #address-cells = <1>;
91 #size-cells = <0>;
Kumar Galaec9686c2007-12-11 23:17:24 -060092 cell-index = <0>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060093 compatible = "fsl-i2c";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050094 reg = <0x3000 0x100>;
95 interrupts = <14 0x8>;
96 interrupt-parent = <&ipic>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -060097 dfsrr;
Kim Phillips27f498072007-11-08 13:37:06 -060098
99 rtc@68 {
100 compatible = "dallas,ds1374";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500101 reg = <0x68>;
Kim Phillips27f498072007-11-08 13:37:06 -0600102 };
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600103 };
104
Kumar Galaea082fa2007-12-12 01:46:12 -0600105 serial0: serial@4500 {
106 cell-index = <0>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600107 device_type = "serial";
Kumar Galaf706bed2011-11-28 13:58:53 -0600108 compatible = "fsl,ns16550", "ns16550";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500109 reg = <0x4500 0x100>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600110 clock-frequency = <0>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500111 interrupts = <9 0x8>;
112 interrupt-parent = <&ipic>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600113 };
114
Kumar Galaea082fa2007-12-12 01:46:12 -0600115 serial1: serial@4600 {
116 cell-index = <1>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600117 device_type = "serial";
Kumar Galaf706bed2011-11-28 13:58:53 -0600118 compatible = "fsl,ns16550", "ns16550";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500119 reg = <0x4600 0x100>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600120 clock-frequency = <0>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500121 interrupts = <10 0x8>;
122 interrupt-parent = <&ipic>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600123 };
124
Kumar Galadee80552008-06-27 13:45:19 -0500125 dma@82a8 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
129 reg = <0x82a8 4>;
130 ranges = <0 0x8100 0x1a8>;
131 interrupt-parent = <&ipic>;
132 interrupts = <71 8>;
133 cell-index = <0>;
134 dma-channel@0 {
135 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
136 reg = <0 0x80>;
Kumar Galaaeb42762008-09-23 22:05:10 -0500137 cell-index = <0>;
Kumar Galadee80552008-06-27 13:45:19 -0500138 interrupt-parent = <&ipic>;
139 interrupts = <71 8>;
140 };
141 dma-channel@80 {
142 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
143 reg = <0x80 0x80>;
Kumar Galaaeb42762008-09-23 22:05:10 -0500144 cell-index = <1>;
Kumar Galadee80552008-06-27 13:45:19 -0500145 interrupt-parent = <&ipic>;
146 interrupts = <71 8>;
147 };
148 dma-channel@100 {
149 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
150 reg = <0x100 0x80>;
Kumar Galaaeb42762008-09-23 22:05:10 -0500151 cell-index = <2>;
Kumar Galadee80552008-06-27 13:45:19 -0500152 interrupt-parent = <&ipic>;
153 interrupts = <71 8>;
154 };
155 dma-channel@180 {
156 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
157 reg = <0x180 0x28>;
Kumar Galaaeb42762008-09-23 22:05:10 -0500158 cell-index = <3>;
Kumar Galadee80552008-06-27 13:45:19 -0500159 interrupt-parent = <&ipic>;
160 interrupts = <71 8>;
161 };
162 };
163
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600164 crypto@30000 {
Kim Phillips3fd44732008-07-08 19:13:33 -0500165 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
166 reg = <0x30000 0x10000>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500167 interrupts = <11 0x8>;
168 interrupt-parent = <&ipic>;
Kim Phillips3fd44732008-07-08 19:13:33 -0500169 fsl,num-channels = <1>;
170 fsl,channel-fifo-len = <24>;
171 fsl,exec-units-mask = <0x4c>;
172 fsl,descriptor-types-mask = <0x0122003f>;
Anton Vorontsov1f8a25d2009-09-16 01:44:02 +0400173 sleep = <&pmc 0x03000000>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600174 };
175
Kumar Galad71a1dc2007-02-16 09:57:22 -0600176 ipic: pic@700 {
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600177 interrupt-controller;
178 #address-cells = <0>;
179 #interrupt-cells = <2>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500180 reg = <0x700 0x100>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600181 device_type = "ipic";
182 };
Kim Phillips4a2adca2007-11-13 17:26:31 -0600183
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600184 par_io@1400 {
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500185 reg = <0x1400 0x100>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600186 device_type = "par_io";
187 num-ports = <7>;
188
Kumar Galad71a1dc2007-02-16 09:57:22 -0600189 pio3: ucc_pin@03 {
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600190 pio-map = <
191 /* port pin dir open_drain assignment has_irq */
192 3 4 3 0 2 0 /* MDIO */
193 3 5 1 0 2 0 /* MDC */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500194 0 13 2 0 1 0 /* RX_CLK (CLK9) */
195 3 24 2 0 1 0 /* TX_CLK (CLK10) */
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600196 1 0 1 0 1 0 /* TxD0 */
197 1 1 1 0 1 0 /* TxD1 */
198 1 2 1 0 1 0 /* TxD2 */
199 1 3 1 0 1 0 /* TxD3 */
200 1 4 2 0 1 0 /* RxD0 */
201 1 5 2 0 1 0 /* RxD1 */
202 1 6 2 0 1 0 /* RxD2 */
203 1 7 2 0 1 0 /* RxD3 */
204 1 8 2 0 1 0 /* RX_ER */
205 1 9 1 0 1 0 /* TX_ER */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500206 1 10 2 0 1 0 /* RX_DV */
207 1 11 2 0 1 0 /* COL */
208 1 12 1 0 1 0 /* TX_EN */
209 1 13 2 0 1 0>; /* CRS */
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600210 };
Kumar Galad71a1dc2007-02-16 09:57:22 -0600211 pio4: ucc_pin@04 {
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600212 pio-map = <
213 /* port pin dir open_drain assignment has_irq */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500214 3 31 2 0 1 0 /* RX_CLK (CLK7) */
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600215 3 6 2 0 1 0 /* TX_CLK (CLK8) */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500216 1 18 1 0 1 0 /* TxD0 */
217 1 19 1 0 1 0 /* TxD1 */
218 1 20 1 0 1 0 /* TxD2 */
219 1 21 1 0 1 0 /* TxD3 */
220 1 22 2 0 1 0 /* RxD0 */
221 1 23 2 0 1 0 /* RxD1 */
222 1 24 2 0 1 0 /* RxD2 */
223 1 25 2 0 1 0 /* RxD3 */
224 1 26 2 0 1 0 /* RX_ER */
225 1 27 1 0 1 0 /* TX_ER */
226 1 28 2 0 1 0 /* RX_DV */
227 1 29 2 0 1 0 /* COL */
228 1 30 1 0 1 0 /* TX_EN */
229 1 31 2 0 1 0>; /* CRS */
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600230 };
Timur Tabi845cf502008-01-09 17:35:05 -0600231 pio5: ucc_pin@05 {
232 pio-map = <
233 /*
234 * open has
235 * port pin dir drain sel irq
236 */
237 2 0 1 0 2 0 /* TxD5 */
238 2 8 2 0 2 0 /* RxD5 */
239
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500240 2 29 2 0 0 0 /* CTS5 */
241 2 31 1 0 2 0 /* RTS5 */
Timur Tabi845cf502008-01-09 17:35:05 -0600242
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500243 2 24 2 0 0 0 /* CD */
Timur Tabi845cf502008-01-09 17:35:05 -0600244
245 >;
246 };
247
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600248 };
249 };
250
251 qe@e0100000 {
252 #address-cells = <1>;
253 #size-cells = <1>;
254 device_type = "qe";
Timur Tabi845cf502008-01-09 17:35:05 -0600255 compatible = "fsl,qe";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500256 ranges = <0x0 0xe0100000 0x00100000>;
257 reg = <0xe0100000 0x480>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600258 brg-frequency = <0>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500259 bus-frequency = <198000000>;
Haiying Wang01b14a92009-05-01 15:40:51 -0400260 fsl,qe-num-riscs = <1>;
261 fsl,qe-num-snums = <28>;
Kim Phillips4a2adca2007-11-13 17:26:31 -0600262
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600263 muram@10000 {
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500264 #address-cells = <1>;
265 #size-cells = <1>;
Anton Vorontsova2dd70a2008-01-24 18:39:59 +0300266 compatible = "fsl,qe-muram", "fsl,cpm-muram";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500267 ranges = <0x0 0x00010000 0x00004000>;
Kim Phillips4a2adca2007-11-13 17:26:31 -0600268
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600269 data-only@0 {
Anton Vorontsova2dd70a2008-01-24 18:39:59 +0300270 compatible = "fsl,qe-muram-data",
271 "fsl,cpm-muram-data";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500272 reg = <0x0 0x4000>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600273 };
274 };
275
276 spi@4c0 {
Anton Vorontsovf3a2b292008-01-24 18:40:07 +0300277 cell-index = <0>;
278 compatible = "fsl,spi";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500279 reg = <0x4c0 0x40>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600280 interrupts = <2>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500281 interrupt-parent = <&qeic>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600282 mode = "cpu";
283 };
284
285 spi@500 {
Anton Vorontsovf3a2b292008-01-24 18:40:07 +0300286 cell-index = <1>;
287 compatible = "fsl,spi";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500288 reg = <0x500 0x40>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600289 interrupts = <1>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500290 interrupt-parent = <&qeic>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600291 mode = "cpu";
292 };
293
294 usb@6c0 {
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600295 compatible = "qe_udc";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500296 reg = <0x6c0 0x40 0x8b00 0x100>;
297 interrupts = <11>;
298 interrupt-parent = <&qeic>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600299 mode = "slave";
300 };
301
Kumar Galae77b28e2007-12-12 00:28:35 -0600302 enet0: ucc@2200 {
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600303 device_type = "network";
304 compatible = "ucc_geth";
Kumar Galae77b28e2007-12-12 00:28:35 -0600305 cell-index = <3>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500306 reg = <0x2200 0x200>;
307 interrupts = <34>;
308 interrupt-parent = <&qeic>;
Timur Tabieae98262007-06-22 14:33:15 -0500309 local-mac-address = [ 00 00 00 00 00 00 ];
Timur Tabi9fb1e352007-12-03 15:17:59 -0600310 rx-clock-name = "clk9";
311 tx-clock-name = "clk10";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500312 phy-handle = <&phy3>;
313 pio-handle = <&pio3>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600314 };
315
Kumar Galae77b28e2007-12-12 00:28:35 -0600316 enet1: ucc@3200 {
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600317 device_type = "network";
318 compatible = "ucc_geth";
Kumar Galae77b28e2007-12-12 00:28:35 -0600319 cell-index = <4>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500320 reg = <0x3200 0x200>;
321 interrupts = <35>;
322 interrupt-parent = <&qeic>;
Timur Tabieae98262007-06-22 14:33:15 -0500323 local-mac-address = [ 00 00 00 00 00 00 ];
Timur Tabi9fb1e352007-12-03 15:17:59 -0600324 rx-clock-name = "clk7";
325 tx-clock-name = "clk8";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500326 phy-handle = <&phy4>;
327 pio-handle = <&pio4>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600328 };
329
Timur Tabi845cf502008-01-09 17:35:05 -0600330 ucc@2400 {
331 device_type = "serial";
332 compatible = "ucc_uart";
Anton Vorontsov56626f32008-04-11 20:06:54 +0400333 cell-index = <5>; /* The UCC number, 1-7*/
Timur Tabi845cf502008-01-09 17:35:05 -0600334 port-number = <0>; /* Which ttyQEx device */
335 soft-uart; /* We need Soft-UART */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500336 reg = <0x2400 0x200>;
337 interrupts = <40>; /* From Table 18-12 */
Timur Tabi845cf502008-01-09 17:35:05 -0600338 interrupt-parent = < &qeic >;
339 /*
340 * For Soft-UART, we need to set TX to 1X, which
341 * means specifying separate clock sources.
342 */
343 rx-clock-name = "brg5";
344 tx-clock-name = "brg6";
345 pio-handle = < &pio5 >;
346 };
347
348
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600349 mdio@2320 {
350 #address-cells = <1>;
351 #size-cells = <0>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500352 reg = <0x2320 0x18>;
Anton Vorontsovd0a2f822008-01-24 18:40:01 +0300353 compatible = "fsl,ucc-mdio";
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600354
Kumar Galad71a1dc2007-02-16 09:57:22 -0600355 phy3: ethernet-phy@03 {
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500356 interrupt-parent = <&ipic>;
357 interrupts = <17 0x8>;
358 reg = <0x3>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600359 };
Kumar Galad71a1dc2007-02-16 09:57:22 -0600360 phy4: ethernet-phy@04 {
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500361 interrupt-parent = <&ipic>;
362 interrupts = <18 0x8>;
363 reg = <0x4>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600364 };
365 };
366
Anton Vorontsova2dd70a2008-01-24 18:39:59 +0300367 qeic: interrupt-controller@80 {
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600368 interrupt-controller;
Anton Vorontsova2dd70a2008-01-24 18:39:59 +0300369 compatible = "fsl,qe-ic";
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600370 #address-cells = <0>;
371 #interrupt-cells = <1>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500372 reg = <0x80 0x80>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600373 big-endian;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500374 interrupts = <32 0x8 33 0x8>; //high:32 low:33
375 interrupt-parent = <&ipic>;
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600376 };
377 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500378
Kumar Galaea082fa2007-12-12 01:46:12 -0600379 pci0: pci@e0008500 {
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500380 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500381 interrupt-map = <
382 /* IDSEL 0x11 AD17 */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500383 0x8800 0x0 0x0 0x1 &ipic 20 0x8
384 0x8800 0x0 0x0 0x2 &ipic 21 0x8
385 0x8800 0x0 0x0 0x3 &ipic 22 0x8
386 0x8800 0x0 0x0 0x4 &ipic 23 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500387
388 /* IDSEL 0x12 AD18 */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500389 0x9000 0x0 0x0 0x1 &ipic 22 0x8
390 0x9000 0x0 0x0 0x2 &ipic 23 0x8
391 0x9000 0x0 0x0 0x3 &ipic 20 0x8
392 0x9000 0x0 0x0 0x4 &ipic 21 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500393
394 /* IDSEL 0x13 AD19 */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500395 0x9800 0x0 0x0 0x1 &ipic 23 0x8
396 0x9800 0x0 0x0 0x2 &ipic 20 0x8
397 0x9800 0x0 0x0 0x3 &ipic 21 0x8
398 0x9800 0x0 0x0 0x4 &ipic 22 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500399
400 /* IDSEL 0x15 AD21*/
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500401 0xa800 0x0 0x0 0x1 &ipic 20 0x8
402 0xa800 0x0 0x0 0x2 &ipic 21 0x8
403 0xa800 0x0 0x0 0x3 &ipic 22 0x8
404 0xa800 0x0 0x0 0x4 &ipic 23 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500405
406 /* IDSEL 0x16 AD22*/
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500407 0xb000 0x0 0x0 0x1 &ipic 23 0x8
408 0xb000 0x0 0x0 0x2 &ipic 20 0x8
409 0xb000 0x0 0x0 0x3 &ipic 21 0x8
410 0xb000 0x0 0x0 0x4 &ipic 22 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500411
412 /* IDSEL 0x17 AD23*/
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500413 0xb800 0x0 0x0 0x1 &ipic 22 0x8
414 0xb800 0x0 0x0 0x2 &ipic 23 0x8
415 0xb800 0x0 0x0 0x3 &ipic 20 0x8
416 0xb800 0x0 0x0 0x4 &ipic 21 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500417
418 /* IDSEL 0x18 AD24*/
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500419 0xc000 0x0 0x0 0x1 &ipic 21 0x8
420 0xc000 0x0 0x0 0x2 &ipic 22 0x8
421 0xc000 0x0 0x0 0x3 &ipic 23 0x8
422 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
423 interrupt-parent = <&ipic>;
424 interrupts = <66 0x8>;
425 bus-range = <0x0 0x0>;
426 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
427 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
428 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500429 clock-frequency = <0>;
430 #interrupt-cells = <1>;
431 #size-cells = <2>;
432 #address-cells = <3>;
John Rigby5b70a092008-10-07 13:00:18 -0600433 reg = <0xe0008500 0x100 /* internal registers */
434 0xe0008300 0x8>; /* config space access registers */
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500435 compatible = "fsl,mpc8349-pci";
436 device_type = "pci";
Anton Vorontsov1f8a25d2009-09-16 01:44:02 +0400437 sleep = <&pmc 0x00010000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500438 };
Kim Phillips18a1e4c2007-01-30 16:09:13 -0600439};