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Ingo Molnar06fcb0c2006-06-29 02:24:40 -07001#ifndef _LINUX_IRQ_H
2#define _LINUX_IRQ_H
Linus Torvalds1da177e2005-04-16 15:20:36 -07003
4/*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
Adrian Bunk23f9b312005-12-21 02:27:50 +010012#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/linkage.h>
14#include <linux/cache.h>
15#include <linux/spinlock.h>
16#include <linux/cpumask.h>
Ralf Baechle503e5762009-03-29 12:59:50 +020017#include <linux/gfp.h>
Thomas Gleixner75ffc002014-11-11 21:58:34 +010018#include <linux/irqhandler.h>
Jan Beulich908dcec2006-06-23 02:06:00 -070019#include <linux/irqreturn.h>
Thomas Gleixnerdd3a1db2008-10-16 18:20:58 +020020#include <linux/irqnr.h>
David Howells77904fd2007-02-28 20:13:26 -080021#include <linux/errno.h>
Ralf Baechle503e5762009-03-29 12:59:50 +020022#include <linux/topology.h>
Thomas Gleixner3aa551c2009-03-23 18:28:15 +010023#include <linux/wait.h>
Kevin Cernekee332fd7c2014-11-06 22:44:17 -080024#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
26#include <asm/irq.h>
27#include <asm/ptrace.h>
David Howells7d12e782006-10-05 14:55:46 +010028#include <asm/irq_regs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Thomas Gleixnerab7798f2011-03-25 16:48:50 +010030struct seq_file;
Paul Gortmakerec53cf22011-09-19 20:33:19 -040031struct module;
Jiang Liu515085e2014-11-06 22:20:17 +080032struct msi_msg;
Marc Zyngier1b7047e2015-03-18 11:01:22 +000033enum irqchip_irq_state;
David Howells57a58a92006-10-05 13:06:34 +010034
Linus Torvalds1da177e2005-04-16 15:20:36 -070035/*
36 * IRQ line status.
Thomas Gleixner6e213612006-07-01 19:29:03 -070037 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010038 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
Thomas Gleixner6e213612006-07-01 19:29:03 -070039 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010040 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
Benjamin Herrenschmidt3fca40c2012-04-19 17:29:42 +000048 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
53 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010054 * IRQ_TYPE_PROBE - Special flag for probing in progress
55 *
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
Geert Uytterhoeven0911f122011-04-10 11:01:51 +020059 * bits are modified via irq_set_irq_type()
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010060 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
64 * request_irq()
Paul Mundt7f1b1242011-04-07 06:01:44 +090065 * IRQ_NOTHREAD - Interrupt cannot be threaded
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010066 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
67 * request/setup_irq()
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
70 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
Marc Zyngier31d9d9b2011-09-23 17:03:06 +010071 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
Thomas Gleixnerb39898c2013-11-06 12:30:07 +010072 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 */
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010076enum {
77 IRQ_TYPE_NONE = 0x00000000,
78 IRQ_TYPE_EDGE_RISING = 0x00000001,
79 IRQ_TYPE_EDGE_FALLING = 0x00000002,
80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
81 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
82 IRQ_TYPE_LEVEL_LOW = 0x00000008,
83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
84 IRQ_TYPE_SENSE_MASK = 0x0000000f,
Benjamin Herrenschmidt3fca40c2012-04-19 17:29:42 +000085 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
Thomas Gleixner876dbd42011-02-08 17:28:12 +010086
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010087 IRQ_TYPE_PROBE = 0x00000010,
Thomas Gleixner6e213612006-07-01 19:29:03 -070088
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010089 IRQ_LEVEL = (1 << 8),
90 IRQ_PER_CPU = (1 << 9),
91 IRQ_NOPROBE = (1 << 10),
92 IRQ_NOREQUEST = (1 << 11),
93 IRQ_NOAUTOEN = (1 << 12),
94 IRQ_NO_BALANCING = (1 << 13),
95 IRQ_MOVE_PCNTXT = (1 << 14),
96 IRQ_NESTED_THREAD = (1 << 15),
Paul Mundt7f1b1242011-04-07 06:01:44 +090097 IRQ_NOTHREAD = (1 << 16),
Marc Zyngier31d9d9b2011-09-23 17:03:06 +010098 IRQ_PER_CPU_DEVID = (1 << 17),
Thomas Gleixnerb39898c2013-11-06 12:30:07 +010099 IRQ_IS_POLLED = (1 << 18),
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +0100100};
Thomas Gleixner950f4422007-02-16 01:27:24 -0800101
Thomas Gleixner44247182010-09-28 10:40:18 +0200102#define IRQF_MODIFY_MASK \
103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
Thomas Gleixner872434d2011-02-05 16:25:25 +0100104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
Thomas Gleixnerb39898c2013-11-06 12:30:07 +0100105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
106 IRQ_IS_POLLED)
Thomas Gleixner44247182010-09-28 10:40:18 +0200107
Thomas Gleixner8f53f922011-02-08 16:50:00 +0100108#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
109
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100110/*
111 * Return value for chip->irq_set_affinity()
112 *
113 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
Jiang Liu2cb62542014-11-06 22:20:18 +0800115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
116 * support stacked irqchips, which indicates skipping
117 * all descendent irqchips.
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100118 */
119enum {
120 IRQ_SET_MASK_OK = 0,
121 IRQ_SET_MASK_OK_NOCOPY,
Jiang Liu2cb62542014-11-06 22:20:18 +0800122 IRQ_SET_MASK_OK_DONE,
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100123};
124
Eric W. Biederman5b912c12007-01-28 12:52:03 -0700125struct msi_desc;
Grant Likely08a543a2011-07-26 03:19:06 -0600126struct irq_domain;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700127
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700128/**
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800129 * struct irq_common_data - per irq data shared by all irqchips
130 * @state_use_accessors: status information for irq chip functions.
131 * Use accessor functions to deal with it
132 */
133struct irq_common_data {
134 unsigned int state_use_accessors;
135};
136
137/**
138 * struct irq_data - per irq chip data passed down to chip functions
Thomas Gleixner966dc732013-05-06 14:30:22 +0000139 * @mask: precomputed bitmask for accessing the chip registers
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000140 * @irq: interrupt number
Grant Likely08a543a2011-07-26 03:19:06 -0600141 * @hwirq: hardware interrupt number, local to the interrupt domain
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000142 * @node: node index useful for balancing
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800143 * @common: point to data shared by all irqchips
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000144 * @chip: low level interrupt hardware access
Grant Likely08a543a2011-07-26 03:19:06 -0600145 * @domain: Interrupt translation domain; responsible for mapping
146 * between hwirq number and linux irq number.
Jiang Liuf8264e32014-11-06 22:20:14 +0800147 * @parent_data: pointer to parent struct irq_data to support hierarchy
148 * irq_domain
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000149 * @handler_data: per-IRQ data for the irq_chip methods
150 * @chip_data: platform-specific per-chip private data for the chip
151 * methods, to allow shared chip implementations
152 * @msi_desc: MSI descriptor
153 * @affinity: IRQ affinity on SMP
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000154 *
155 * The fields here need to overlay the ones in irq_desc until we
156 * cleaned up the direct references and switched everything over to
157 * irq_data.
158 */
159struct irq_data {
Thomas Gleixner966dc732013-05-06 14:30:22 +0000160 u32 mask;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000161 unsigned int irq;
Grant Likely08a543a2011-07-26 03:19:06 -0600162 unsigned long hwirq;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000163 unsigned int node;
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800164 struct irq_common_data *common;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000165 struct irq_chip *chip;
Grant Likely08a543a2011-07-26 03:19:06 -0600166 struct irq_domain *domain;
Jiang Liuf8264e32014-11-06 22:20:14 +0800167#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
168 struct irq_data *parent_data;
169#endif
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000170 void *handler_data;
171 void *chip_data;
172 struct msi_desc *msi_desc;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000173 cpumask_var_t affinity;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000174};
175
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100176/*
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800177 * Bit masks for irq_common_data.state_use_accessors
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100178 *
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100179 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100180 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
Thomas Gleixnera0056772011-02-08 17:11:03 +0100181 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
182 * IRQD_PER_CPU - Interrupt is per cpu
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100183 * IRQD_AFFINITY_SET - Interrupt affinity was set
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100184 * IRQD_LEVEL - Interrupt is level triggered
Thomas Gleixner7f942262011-02-10 19:46:26 +0100185 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
186 * from suspend
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100187 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
188 * context
Thomas Gleixner32f41252011-03-28 14:10:52 +0200189 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
190 * IRQD_IRQ_MASKED - Masked state of the interrupt
191 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200192 * IRQD_WAKEUP_ARMED - Wakeup mode armed
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100193 */
194enum {
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100195 IRQD_TRIGGER_MASK = 0xf,
Thomas Gleixnera0056772011-02-08 17:11:03 +0100196 IRQD_SETAFFINITY_PENDING = (1 << 8),
197 IRQD_NO_BALANCING = (1 << 10),
198 IRQD_PER_CPU = (1 << 11),
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100199 IRQD_AFFINITY_SET = (1 << 12),
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100200 IRQD_LEVEL = (1 << 13),
Thomas Gleixner7f942262011-02-10 19:46:26 +0100201 IRQD_WAKEUP_STATE = (1 << 14),
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100202 IRQD_MOVE_PCNTXT = (1 << 15),
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200203 IRQD_IRQ_DISABLED = (1 << 16),
Thomas Gleixner32f41252011-03-28 14:10:52 +0200204 IRQD_IRQ_MASKED = (1 << 17),
205 IRQD_IRQ_INPROGRESS = (1 << 18),
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200206 IRQD_WAKEUP_ARMED = (1 << 19),
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100207};
208
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800209#define __irqd_to_state(d) ((d)->common->state_use_accessors)
210
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100211static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
212{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800213 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100214}
215
Thomas Gleixnera0056772011-02-08 17:11:03 +0100216static inline bool irqd_is_per_cpu(struct irq_data *d)
217{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800218 return __irqd_to_state(d) & IRQD_PER_CPU;
Thomas Gleixnera0056772011-02-08 17:11:03 +0100219}
220
221static inline bool irqd_can_balance(struct irq_data *d)
222{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800223 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
Thomas Gleixnera0056772011-02-08 17:11:03 +0100224}
225
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100226static inline bool irqd_affinity_was_set(struct irq_data *d)
227{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800228 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100229}
230
Thomas Gleixneree38c042011-03-28 17:11:13 +0200231static inline void irqd_mark_affinity_was_set(struct irq_data *d)
232{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800233 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
Thomas Gleixneree38c042011-03-28 17:11:13 +0200234}
235
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100236static inline u32 irqd_get_trigger_type(struct irq_data *d)
237{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800238 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100239}
240
241/*
242 * Must only be called inside irq_chip.irq_set_type() functions.
243 */
244static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
245{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800246 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
247 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100248}
249
250static inline bool irqd_is_level_type(struct irq_data *d)
251{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800252 return __irqd_to_state(d) & IRQD_LEVEL;
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100253}
254
Thomas Gleixner7f942262011-02-10 19:46:26 +0100255static inline bool irqd_is_wakeup_set(struct irq_data *d)
256{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800257 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
Thomas Gleixner7f942262011-02-10 19:46:26 +0100258}
259
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100260static inline bool irqd_can_move_in_process_context(struct irq_data *d)
261{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800262 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100263}
264
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200265static inline bool irqd_irq_disabled(struct irq_data *d)
266{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800267 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200268}
269
Thomas Gleixner32f41252011-03-28 14:10:52 +0200270static inline bool irqd_irq_masked(struct irq_data *d)
271{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800272 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
Thomas Gleixner32f41252011-03-28 14:10:52 +0200273}
274
275static inline bool irqd_irq_inprogress(struct irq_data *d)
276{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800277 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
Thomas Gleixner32f41252011-03-28 14:10:52 +0200278}
279
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200280static inline bool irqd_is_wakeup_armed(struct irq_data *d)
281{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800282 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200283}
284
285
Thomas Gleixner9cff60d2011-03-28 16:41:14 +0200286/*
287 * Functions for chained handlers which can be enabled/disabled by the
288 * standard disable_irq/enable_irq calls. Must be called with
289 * irq_desc->lock held.
290 */
291static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
292{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800293 __irqd_to_state(d) |= IRQD_IRQ_INPROGRESS;
Thomas Gleixner9cff60d2011-03-28 16:41:14 +0200294}
295
296static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
297{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800298 __irqd_to_state(d) &= ~IRQD_IRQ_INPROGRESS;
Thomas Gleixner9cff60d2011-03-28 16:41:14 +0200299}
300
Grant Likelya699e4e2012-04-03 07:11:04 -0600301static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
302{
303 return d->hwirq;
304}
305
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000306/**
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700307 * struct irq_chip - hardware interrupt chip descriptor
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700308 *
309 * @name: name for /proc/interrupts
Thomas Gleixnerf8822652010-09-27 12:44:32 +0000310 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
311 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
312 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
313 * @irq_disable: disable the interrupt
314 * @irq_ack: start of a new interrupt
315 * @irq_mask: mask an interrupt source
316 * @irq_mask_ack: ack and mask an interrupt source
317 * @irq_unmask: unmask an interrupt source
318 * @irq_eoi: end of interrupt
319 * @irq_set_affinity: set the CPU affinity on SMP machines
320 * @irq_retrigger: resend an IRQ to the CPU
321 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
322 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
323 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
324 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
David Daney0fdb4b22011-03-25 12:38:49 -0700325 * @irq_cpu_online: configure an interrupt source for a secondary CPU
326 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200327 * @irq_suspend: function called from core code on suspend once per chip
328 * @irq_resume: function called from core code on resume once per chip
329 * @irq_pm_shutdown: function called from core code on shutdown once per chip
Thomas Gleixnerd0051812013-05-06 14:30:24 +0000330 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100331 * @irq_print_chip: optional to print special chip info in show_interrupts
Thomas Gleixnerc1bacba2014-03-08 08:59:58 +0100332 * @irq_request_resources: optional to request resources before calling
333 * any other callback related to this irq
334 * @irq_release_resources: optional to release resources acquired with
335 * irq_request_resources
Jiang Liu515085e2014-11-06 22:20:17 +0800336 * @irq_compose_msi_msg: optional to compose message content for MSI
Jiang Liu9dde55b2014-11-09 23:10:28 +0800337 * @irq_write_msi_msg: optional to write message content for MSI
Marc Zyngier1b7047e2015-03-18 11:01:22 +0000338 * @irq_get_irqchip_state: return the internal state of an interrupt
339 * @irq_set_irqchip_state: set the internal state of a interrupt
Jiang Liu0a4377d2015-05-19 17:07:14 +0800340 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
Thomas Gleixner2bff17a2011-02-10 13:08:38 +0100341 * @flags: chip specific flags
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342 */
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700343struct irq_chip {
344 const char *name;
Thomas Gleixnerf8822652010-09-27 12:44:32 +0000345 unsigned int (*irq_startup)(struct irq_data *data);
346 void (*irq_shutdown)(struct irq_data *data);
347 void (*irq_enable)(struct irq_data *data);
348 void (*irq_disable)(struct irq_data *data);
349
350 void (*irq_ack)(struct irq_data *data);
351 void (*irq_mask)(struct irq_data *data);
352 void (*irq_mask_ack)(struct irq_data *data);
353 void (*irq_unmask)(struct irq_data *data);
354 void (*irq_eoi)(struct irq_data *data);
355
356 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
357 int (*irq_retrigger)(struct irq_data *data);
358 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
359 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
360
361 void (*irq_bus_lock)(struct irq_data *data);
362 void (*irq_bus_sync_unlock)(struct irq_data *data);
363
David Daney0fdb4b22011-03-25 12:38:49 -0700364 void (*irq_cpu_online)(struct irq_data *data);
365 void (*irq_cpu_offline)(struct irq_data *data);
366
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200367 void (*irq_suspend)(struct irq_data *data);
368 void (*irq_resume)(struct irq_data *data);
369 void (*irq_pm_shutdown)(struct irq_data *data);
370
Thomas Gleixnerd0051812013-05-06 14:30:24 +0000371 void (*irq_calc_mask)(struct irq_data *data);
372
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100373 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
Thomas Gleixnerc1bacba2014-03-08 08:59:58 +0100374 int (*irq_request_resources)(struct irq_data *data);
375 void (*irq_release_resources)(struct irq_data *data);
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100376
Jiang Liu515085e2014-11-06 22:20:17 +0800377 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
Jiang Liu9dde55b2014-11-09 23:10:28 +0800378 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
Jiang Liu515085e2014-11-06 22:20:17 +0800379
Marc Zyngier1b7047e2015-03-18 11:01:22 +0000380 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
381 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
382
Jiang Liu0a4377d2015-05-19 17:07:14 +0800383 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
384
Thomas Gleixner2bff17a2011-02-10 13:08:38 +0100385 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386};
387
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100388/*
389 * irq_chip specific flags
390 *
Thomas Gleixner77694b42011-02-15 10:33:57 +0100391 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
392 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
Thomas Gleixnerd209a692011-03-11 21:22:14 +0100393 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
Thomas Gleixnerb3d42232011-03-27 16:05:36 +0200394 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
395 * when irq enabled
Santosh Shilimkar60f96b42011-09-09 13:59:35 +0530396 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
Thomas Gleixner4f6e4f72014-03-13 15:32:47 +0100397 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
Thomas Gleixner328a4972014-03-13 19:03:51 +0100398 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100399 */
400enum {
401 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
Thomas Gleixner77694b42011-02-15 10:33:57 +0100402 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
Thomas Gleixnerd209a692011-03-11 21:22:14 +0100403 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
Thomas Gleixnerb3d42232011-03-27 16:05:36 +0200404 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
Santosh Shilimkar60f96b42011-09-09 13:59:35 +0530405 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
Thomas Gleixnerdc9b2292012-07-13 19:29:45 +0200406 IRQCHIP_ONESHOT_SAFE = (1 << 5),
Thomas Gleixner328a4972014-03-13 19:03:51 +0100407 IRQCHIP_EOI_THREADED = (1 << 6),
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100408};
409
Thomas Gleixnere1447102010-10-01 16:03:45 +0200410#include <linux/irqdesc.h>
Thomas Gleixnerc6b76742008-10-15 14:31:29 +0200411
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700412/*
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700413 * Pick up the arch-dependent methods:
414 */
415#include <asm/hw_irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416
Thomas Gleixnerb683de22010-09-27 20:55:03 +0200417#ifndef NR_IRQS_LEGACY
418# define NR_IRQS_LEGACY 0
419#endif
420
Thomas Gleixner1318a482010-09-27 21:01:37 +0200421#ifndef ARCH_IRQ_INIT_FLAGS
422# define ARCH_IRQ_INIT_FLAGS 0
423#endif
424
Thomas Gleixnerc1594b72011-02-07 22:11:30 +0100425#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
Thomas Gleixner1318a482010-09-27 21:01:37 +0200426
Thomas Gleixnere1447102010-10-01 16:03:45 +0200427struct irqaction;
Ingo Molnar06fcb0c2006-06-29 02:24:40 -0700428extern int setup_irq(unsigned int irq, struct irqaction *new);
Magnus Dammcbf94f02009-03-12 21:05:51 +0900429extern void remove_irq(unsigned int irq, struct irqaction *act);
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100430extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
431extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432
David Daney0fdb4b22011-03-25 12:38:49 -0700433extern void irq_cpu_online(void);
434extern void irq_cpu_offline(void);
Thomas Gleixner01f8fa42014-04-16 14:36:44 +0000435extern int irq_set_affinity_locked(struct irq_data *data,
436 const struct cpumask *cpumask, bool force);
Jiang Liu0a4377d2015-05-19 17:07:14 +0800437extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
David Daney0fdb4b22011-03-25 12:38:49 -0700438
Thomas Gleixner3a3856d02010-10-04 13:47:12 +0200439#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
Thomas Gleixnera4395202011-02-04 18:46:16 +0100440void irq_move_irq(struct irq_data *data);
441void irq_move_masked_irq(struct irq_data *data);
Thomas Gleixnere1447102010-10-01 16:03:45 +0200442#else
Thomas Gleixnera4395202011-02-04 18:46:16 +0100443static inline void irq_move_irq(struct irq_data *data) { }
444static inline void irq_move_masked_irq(struct irq_data *data) { }
Thomas Gleixnere1447102010-10-01 16:03:45 +0200445#endif
Ashok Raj54d5d422005-09-06 15:16:15 -0700446
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447extern int no_irq_affinity;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
Thomas Gleixner293a7a02012-10-16 15:07:49 -0700449#ifdef CONFIG_HARDIRQS_SW_RESEND
450int irq_set_parent(int irq, int parent_irq);
451#else
452static inline int irq_set_parent(int irq, int parent_irq)
453{
454 return 0;
455}
456#endif
457
Ingo Molnar2e60bbb2006-06-29 02:24:39 -0700458/*
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700459 * Built-in IRQ handlers for various IRQ types,
Krzysztof Halasabebd04c2009-11-15 18:57:24 +0100460 * callable via desc->handle_irq()
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700461 */
Harvey Harrisonec701582008-02-08 04:19:55 -0800462extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
463extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
464extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
Thomas Gleixner0521c8f2011-03-28 16:13:24 +0200465extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
Harvey Harrisonec701582008-02-08 04:19:55 -0800466extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
467extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100468extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
Harvey Harrisonec701582008-02-08 04:19:55 -0800469extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
Mark Brown31b47cf2009-08-24 20:28:04 +0100470extern void handle_nested_irq(unsigned int irq);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700471
Jiang Liu515085e2014-11-06 22:20:17 +0800472extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
Jiang Liu85f08c12014-11-06 22:20:16 +0800473#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
Stefan Agner3cfeffc2015-05-16 11:44:14 +0200474extern void irq_chip_enable_parent(struct irq_data *data);
475extern void irq_chip_disable_parent(struct irq_data *data);
Jiang Liu85f08c12014-11-06 22:20:16 +0800476extern void irq_chip_ack_parent(struct irq_data *data);
477extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
Yingjoe Chen56e8aba2014-11-13 23:37:05 +0800478extern void irq_chip_mask_parent(struct irq_data *data);
479extern void irq_chip_unmask_parent(struct irq_data *data);
480extern void irq_chip_eoi_parent(struct irq_data *data);
481extern int irq_chip_set_affinity_parent(struct irq_data *data,
482 const struct cpumask *dest,
483 bool force);
Marc Zyngier08b55e22015-03-11 15:43:43 +0000484extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
Jiang Liu0a4377d2015-05-19 17:07:14 +0800485extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
486 void *vcpu_info);
Jiang Liu85f08c12014-11-06 22:20:16 +0800487#endif
488
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700489/* Handling of unhandled and spurious interrupts: */
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700490extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
Thomas Gleixnerbedd30d2008-09-30 23:14:27 +0200491 irqreturn_t action_ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492
Thomas Gleixnera4633adc2006-06-29 02:24:48 -0700493
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700494/* Enable/disable irq debugging output: */
495extern int noirqdebug_setup(char *str);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700497/* Checks whether the interrupt can be requested by request_irq(): */
498extern int can_request_irq(unsigned int irq, unsigned long irqflags);
499
Thomas Gleixnerf8b54732006-07-01 22:30:08 +0100500/* Dummy irq-chip implementations: */
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700501extern struct irq_chip no_irq_chip;
Thomas Gleixnerf8b54732006-07-01 22:30:08 +0100502extern struct irq_chip dummy_irq_chip;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700503
504extern void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100505irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
Ingo Molnara460e742006-10-17 00:10:03 -0700506 irq_flow_handler_t handle, const char *name);
507
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100508static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
509 irq_flow_handler_t handle)
510{
511 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
512}
513
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100514extern int irq_set_percpu_devid(unsigned int irq);
515
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700516extern void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100517__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
Ingo Molnara460e742006-10-17 00:10:03 -0700518 const char *name);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700519
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700520static inline void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100521irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700522{
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100523 __irq_set_handler(irq, handle, 0, NULL);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700524}
525
526/*
527 * Set a highlevel chained flow handler for a given IRQ.
528 * (a chained handler is automatically enabled and set to
Paul Mundt7f1b1242011-04-07 06:01:44 +0900529 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700530 */
531static inline void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100532irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700533{
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100534 __irq_set_handler(irq, handle, 1, NULL);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700535}
536
Russell King3b0f95b2015-06-16 23:06:20 +0100537/*
538 * Set a highlevel chained flow handler and its data for a given IRQ.
539 * (a chained handler is automatically enabled and set to
540 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
541 */
542void
543irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
544 void *data);
545
Thomas Gleixner44247182010-09-28 10:40:18 +0200546void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
547
548static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
549{
550 irq_modify_status(irq, 0, set);
551}
552
553static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
554{
555 irq_modify_status(irq, clr, 0);
556}
557
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100558static inline void irq_set_noprobe(unsigned int irq)
Thomas Gleixner44247182010-09-28 10:40:18 +0200559{
560 irq_modify_status(irq, 0, IRQ_NOPROBE);
561}
562
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100563static inline void irq_set_probe(unsigned int irq)
Thomas Gleixner44247182010-09-28 10:40:18 +0200564{
565 irq_modify_status(irq, IRQ_NOPROBE, 0);
566}
Ralf Baechle46f4f8f2008-02-08 04:22:01 -0800567
Paul Mundt7f1b1242011-04-07 06:01:44 +0900568static inline void irq_set_nothread(unsigned int irq)
569{
570 irq_modify_status(irq, 0, IRQ_NOTHREAD);
571}
572
573static inline void irq_set_thread(unsigned int irq)
574{
575 irq_modify_status(irq, IRQ_NOTHREAD, 0);
576}
577
Thomas Gleixner6f91a522011-02-14 13:33:16 +0100578static inline void irq_set_nested_thread(unsigned int irq, bool nest)
579{
580 if (nest)
581 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
582 else
583 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
584}
585
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100586static inline void irq_set_percpu_devid_flags(unsigned int irq)
587{
588 irq_set_status_flags(irq,
589 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
590 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
591}
592
Eric W. Biederman3a16d712006-10-04 02:16:37 -0700593/* Set/get chip/data for an IRQ: */
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100594extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
595extern int irq_set_handler_data(unsigned int irq, void *data);
596extern int irq_set_chip_data(unsigned int irq, void *data);
597extern int irq_set_irq_type(unsigned int irq, unsigned int type);
598extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
Alexander Gordeev51906e72012-11-19 16:01:29 +0100599extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
600 struct msi_desc *entry);
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200601extern struct irq_data *irq_get_irq_data(unsigned int irq);
Thomas Gleixnerdd87eb32006-06-29 02:24:53 -0700602
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100603static inline struct irq_chip *irq_get_chip(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200604{
605 struct irq_data *d = irq_get_irq_data(irq);
606 return d ? d->chip : NULL;
607}
608
609static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
610{
611 return d->chip;
612}
613
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100614static inline void *irq_get_chip_data(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200615{
616 struct irq_data *d = irq_get_irq_data(irq);
617 return d ? d->chip_data : NULL;
618}
619
620static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
621{
622 return d->chip_data;
623}
624
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100625static inline void *irq_get_handler_data(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200626{
627 struct irq_data *d = irq_get_irq_data(irq);
628 return d ? d->handler_data : NULL;
629}
630
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100631static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200632{
633 return d->handler_data;
634}
635
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100636static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200637{
638 struct irq_data *d = irq_get_irq_data(irq);
639 return d ? d->msi_desc : NULL;
640}
641
642static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
643{
644 return d->msi_desc;
645}
646
Javier Martinez Canillas1f6236b2013-06-14 18:40:43 +0200647static inline u32 irq_get_trigger_type(unsigned int irq)
648{
649 struct irq_data *d = irq_get_irq_data(irq);
650 return d ? irqd_get_trigger_type(d) : 0;
651}
652
Jiang Liu67830112015-06-01 16:05:13 +0800653static inline int irq_data_get_node(struct irq_data *d)
654{
655 return d->node;
656}
657
Jiang Liuc64301a2015-06-01 16:05:23 +0800658static inline struct cpumask *irq_get_affinity_mask(int irq)
659{
660 struct irq_data *d = irq_get_irq_data(irq);
661
662 return d ? d->affinity : NULL;
663}
664
665static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
666{
667 return d->affinity;
668}
669
Thomas Gleixner62a08ae2014-04-24 09:50:53 +0200670unsigned int arch_dynirq_lower_bound(unsigned int from);
671
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200672int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
673 struct module *owner);
674
Paul Gortmakerec53cf22011-09-19 20:33:19 -0400675/* use macros to avoid needing export.h for THIS_MODULE */
676#define irq_alloc_descs(irq, from, cnt, node) \
677 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
678
679#define irq_alloc_desc(node) \
680 irq_alloc_descs(-1, 0, 1, node)
681
682#define irq_alloc_desc_at(at, node) \
683 irq_alloc_descs(at, at, 1, node)
684
685#define irq_alloc_desc_from(from, node) \
686 irq_alloc_descs(-1, from, 1, node)
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200687
Alexander Gordeev51906e72012-11-19 16:01:29 +0100688#define irq_alloc_descs_from(from, cnt, node) \
689 irq_alloc_descs(-1, from, cnt, node)
690
Thomas Gleixner1f5a5b82010-09-27 17:48:26 +0200691void irq_free_descs(unsigned int irq, unsigned int cnt);
Thomas Gleixner1f5a5b82010-09-27 17:48:26 +0200692static inline void irq_free_desc(unsigned int irq)
693{
694 irq_free_descs(irq, 1);
695}
696
Thomas Gleixner7b6ef122014-05-07 15:44:05 +0000697#ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
698unsigned int irq_alloc_hwirqs(int cnt, int node);
699static inline unsigned int irq_alloc_hwirq(int node)
700{
701 return irq_alloc_hwirqs(1, node);
702}
703void irq_free_hwirqs(unsigned int from, int cnt);
704static inline void irq_free_hwirq(unsigned int irq)
705{
706 return irq_free_hwirqs(irq, 1);
707}
708int arch_setup_hwirq(unsigned int irq, int node);
709void arch_teardown_hwirq(unsigned int irq);
710#endif
711
Thomas Gleixnerc940e012014-05-07 15:44:22 +0000712#ifdef CONFIG_GENERIC_IRQ_LEGACY
713void irq_init_desc(unsigned int irq);
714#endif
715
Thomas Gleixner7d828062011-04-03 11:42:53 +0200716/**
717 * struct irq_chip_regs - register offsets for struct irq_gci
718 * @enable: Enable register offset to reg_base
719 * @disable: Disable register offset to reg_base
720 * @mask: Mask register offset to reg_base
721 * @ack: Ack register offset to reg_base
722 * @eoi: Eoi register offset to reg_base
723 * @type: Type configuration register offset to reg_base
724 * @polarity: Polarity configuration register offset to reg_base
725 */
726struct irq_chip_regs {
727 unsigned long enable;
728 unsigned long disable;
729 unsigned long mask;
730 unsigned long ack;
731 unsigned long eoi;
732 unsigned long type;
733 unsigned long polarity;
734};
735
736/**
737 * struct irq_chip_type - Generic interrupt chip instance for a flow type
738 * @chip: The real interrupt chip which provides the callbacks
739 * @regs: Register offsets for this chip
740 * @handler: Flow handler associated with this chip
741 * @type: Chip can handle these flow types
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000742 * @mask_cache_priv: Cached mask register private to the chip type
743 * @mask_cache: Pointer to cached mask register
Thomas Gleixner7d828062011-04-03 11:42:53 +0200744 *
745 * A irq_generic_chip can have several instances of irq_chip_type when
746 * it requires different functions and register offsets for different
747 * flow types.
748 */
749struct irq_chip_type {
750 struct irq_chip chip;
751 struct irq_chip_regs regs;
752 irq_flow_handler_t handler;
753 u32 type;
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000754 u32 mask_cache_priv;
755 u32 *mask_cache;
Thomas Gleixner7d828062011-04-03 11:42:53 +0200756};
757
758/**
759 * struct irq_chip_generic - Generic irq chip data structure
760 * @lock: Lock to protect register and cache data access
761 * @reg_base: Register base address (virtual)
Kevin Cernekee2b280372014-11-06 22:44:18 -0800762 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
763 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
Thomas Gleixner7d828062011-04-03 11:42:53 +0200764 * @irq_base: Interrupt base nr for this chip
765 * @irq_cnt: Number of interrupts handled by this chip
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000766 * @mask_cache: Cached mask register shared between all chip types
Thomas Gleixner7d828062011-04-03 11:42:53 +0200767 * @type_cache: Cached type register
768 * @polarity_cache: Cached polarity register
769 * @wake_enabled: Interrupt can wakeup from suspend
770 * @wake_active: Interrupt is marked as an wakeup from suspend source
771 * @num_ct: Number of available irq_chip_type instances (usually 1)
772 * @private: Private data for non generic chip callbacks
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000773 * @installed: bitfield to denote installed interrupts
Grant Likelye8bd8342013-05-29 03:10:52 +0100774 * @unused: bitfield to denote unused interrupts
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000775 * @domain: irq domain pointer
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200776 * @list: List head for keeping track of instances
Thomas Gleixner7d828062011-04-03 11:42:53 +0200777 * @chip_types: Array of interrupt irq_chip_types
778 *
779 * Note, that irq_chip_generic can have multiple irq_chip_type
780 * implementations which can be associated to a particular irq line of
781 * an irq_chip_generic instance. That allows to share and protect
782 * state in an irq_chip_generic instance when we need to implement
783 * different flow mechanisms (level/edge) for it.
784 */
785struct irq_chip_generic {
786 raw_spinlock_t lock;
787 void __iomem *reg_base;
Kevin Cernekee2b280372014-11-06 22:44:18 -0800788 u32 (*reg_readl)(void __iomem *addr);
789 void (*reg_writel)(u32 val, void __iomem *addr);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200790 unsigned int irq_base;
791 unsigned int irq_cnt;
792 u32 mask_cache;
793 u32 type_cache;
794 u32 polarity_cache;
795 u32 wake_enabled;
796 u32 wake_active;
797 unsigned int num_ct;
798 void *private;
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000799 unsigned long installed;
Grant Likelye8bd8342013-05-29 03:10:52 +0100800 unsigned long unused;
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000801 struct irq_domain *domain;
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200802 struct list_head list;
Thomas Gleixner7d828062011-04-03 11:42:53 +0200803 struct irq_chip_type chip_types[0];
804};
805
806/**
807 * enum irq_gc_flags - Initialization flags for generic irq chips
808 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
809 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
810 * irq chips which need to call irq_set_wake() on
811 * the parent irq. Usually GPIO implementations
Gerlando Falautoaf80b0f2013-05-06 14:30:21 +0000812 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
Thomas Gleixner966dc732013-05-06 14:30:22 +0000813 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
Kevin Cernekeeb7905592014-11-06 22:44:19 -0800814 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
Thomas Gleixner7d828062011-04-03 11:42:53 +0200815 */
816enum irq_gc_flags {
817 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
818 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
Gerlando Falautoaf80b0f2013-05-06 14:30:21 +0000819 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
Thomas Gleixner966dc732013-05-06 14:30:22 +0000820 IRQ_GC_NO_MASK = 1 << 3,
Kevin Cernekeeb7905592014-11-06 22:44:19 -0800821 IRQ_GC_BE_IO = 1 << 4,
Thomas Gleixner7d828062011-04-03 11:42:53 +0200822};
823
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000824/*
825 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
826 * @irqs_per_chip: Number of interrupts per chip
827 * @num_chips: Number of chips
828 * @irq_flags_to_set: IRQ* flags to set on irq setup
829 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
830 * @gc_flags: Generic chip specific setup flags
831 * @gc: Array of pointers to generic interrupt chips
832 */
833struct irq_domain_chip_generic {
834 unsigned int irqs_per_chip;
835 unsigned int num_chips;
836 unsigned int irq_flags_to_clear;
837 unsigned int irq_flags_to_set;
838 enum irq_gc_flags gc_flags;
839 struct irq_chip_generic *gc[0];
840};
841
Thomas Gleixner7d828062011-04-03 11:42:53 +0200842/* Generic chip callback functions */
843void irq_gc_noop(struct irq_data *d);
844void irq_gc_mask_disable_reg(struct irq_data *d);
845void irq_gc_mask_set_bit(struct irq_data *d);
846void irq_gc_mask_clr_bit(struct irq_data *d);
847void irq_gc_unmask_enable_reg(struct irq_data *d);
Simon Guinot659fb322011-07-06 12:41:31 -0400848void irq_gc_ack_set_bit(struct irq_data *d);
849void irq_gc_ack_clr_bit(struct irq_data *d);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200850void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
851void irq_gc_eoi(struct irq_data *d);
852int irq_gc_set_wake(struct irq_data *d, unsigned int on);
853
854/* Setup functions for irq_chip_generic */
Boris BREZILLONa5152c82014-07-10 19:14:16 +0200855int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
856 irq_hw_number_t hw_irq);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200857struct irq_chip_generic *
858irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
859 void __iomem *reg_base, irq_flow_handler_t handler);
860void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
861 enum irq_gc_flags flags, unsigned int clr,
862 unsigned int set);
863int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200864void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
865 unsigned int clr, unsigned int set);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200866
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000867struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
868int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
869 int num_ct, const char *name,
870 irq_flow_handler_t handler,
871 unsigned int clr, unsigned int set,
872 enum irq_gc_flags flags);
873
874
Thomas Gleixner7d828062011-04-03 11:42:53 +0200875static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
876{
877 return container_of(d->chip, struct irq_chip_type, chip);
878}
879
880#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
881
882#ifdef CONFIG_SMP
883static inline void irq_gc_lock(struct irq_chip_generic *gc)
884{
885 raw_spin_lock(&gc->lock);
886}
887
888static inline void irq_gc_unlock(struct irq_chip_generic *gc)
889{
890 raw_spin_unlock(&gc->lock);
891}
892#else
893static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
894static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
895#endif
896
Kevin Cernekee332fd7c2014-11-06 22:44:17 -0800897static inline void irq_reg_writel(struct irq_chip_generic *gc,
898 u32 val, int reg_offset)
899{
Kevin Cernekee2b280372014-11-06 22:44:18 -0800900 if (gc->reg_writel)
901 gc->reg_writel(val, gc->reg_base + reg_offset);
902 else
903 writel(val, gc->reg_base + reg_offset);
Kevin Cernekee332fd7c2014-11-06 22:44:17 -0800904}
905
906static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
907 int reg_offset)
908{
Kevin Cernekee2b280372014-11-06 22:44:18 -0800909 if (gc->reg_readl)
910 return gc->reg_readl(gc->reg_base + reg_offset);
911 else
912 return readl(gc->reg_base + reg_offset);
Kevin Cernekee332fd7c2014-11-06 22:44:17 -0800913}
914
Ingo Molnar06fcb0c2006-06-29 02:24:40 -0700915#endif /* _LINUX_IRQ_H */