Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 28 | #include <linux/slab.h> |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 29 | #include <linux/seq_file.h> |
| 30 | #include <linux/firmware.h> |
| 31 | #include <linux/platform_device.h> |
Paul Gortmaker | e0cd360 | 2011-08-30 11:04:30 -0400 | [diff] [blame] | 32 | #include <linux/module.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drmP.h> |
| 34 | #include <drm/radeon_drm.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 35 | #include "radeon.h" |
Daniel Vetter | e699037 | 2010-03-11 21:19:17 +0000 | [diff] [blame] | 36 | #include "radeon_asic.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 37 | #include "radeon_mode.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 38 | #include "r600d.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 39 | #include "atom.h" |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 40 | #include "avivod.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 42 | #define PFP_UCODE_SIZE 576 |
| 43 | #define PM4_UCODE_SIZE 1792 |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 44 | #define RLC_UCODE_SIZE 768 |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 45 | #define R700_PFP_UCODE_SIZE 848 |
| 46 | #define R700_PM4_UCODE_SIZE 1360 |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 47 | #define R700_RLC_UCODE_SIZE 1024 |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 48 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
| 49 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 50 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
Alex Deucher | 1272780 | 2011-03-02 20:07:32 -0500 | [diff] [blame] | 51 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
Alex Deucher | c420c74 | 2012-03-20 17:18:39 -0400 | [diff] [blame] | 52 | #define ARUBA_RLC_UCODE_SIZE 1536 |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 53 | |
| 54 | /* Firmware Names */ |
| 55 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); |
| 56 | MODULE_FIRMWARE("radeon/R600_me.bin"); |
| 57 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); |
| 58 | MODULE_FIRMWARE("radeon/RV610_me.bin"); |
| 59 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); |
| 60 | MODULE_FIRMWARE("radeon/RV630_me.bin"); |
| 61 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); |
| 62 | MODULE_FIRMWARE("radeon/RV620_me.bin"); |
| 63 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); |
| 64 | MODULE_FIRMWARE("radeon/RV635_me.bin"); |
| 65 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); |
| 66 | MODULE_FIRMWARE("radeon/RV670_me.bin"); |
| 67 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); |
| 68 | MODULE_FIRMWARE("radeon/RS780_me.bin"); |
| 69 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); |
| 70 | MODULE_FIRMWARE("radeon/RV770_me.bin"); |
| 71 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); |
| 72 | MODULE_FIRMWARE("radeon/RV730_me.bin"); |
| 73 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); |
| 74 | MODULE_FIRMWARE("radeon/RV710_me.bin"); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 75 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
| 76 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 77 | MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); |
| 78 | MODULE_FIRMWARE("radeon/CEDAR_me.bin"); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 79 | MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 80 | MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); |
| 81 | MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 82 | MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 83 | MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); |
| 84 | MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 85 | MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); |
Dave Airlie | a743374 | 2010-04-09 15:31:09 +1000 | [diff] [blame] | 86 | MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 87 | MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 88 | MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); |
Alex Deucher | 439bd6c | 2010-11-22 17:56:31 -0500 | [diff] [blame] | 89 | MODULE_FIRMWARE("radeon/PALM_pfp.bin"); |
| 90 | MODULE_FIRMWARE("radeon/PALM_me.bin"); |
| 91 | MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); |
Alex Deucher | d5c5a72 | 2011-05-31 15:42:48 -0400 | [diff] [blame] | 92 | MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); |
| 93 | MODULE_FIRMWARE("radeon/SUMO_me.bin"); |
| 94 | MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); |
| 95 | MODULE_FIRMWARE("radeon/SUMO2_me.bin"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 96 | |
| 97 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 98 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 99 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 100 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 101 | static void r600_gpu_init(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 102 | void r600_fini(struct radeon_device *rdev); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 103 | void r600_irq_disable(struct radeon_device *rdev); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 104 | static void r600_pcie_gen2_enable(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 105 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 106 | /* get temperature in millidegrees */ |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 107 | int rv6xx_get_temp(struct radeon_device *rdev) |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 108 | { |
| 109 | u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> |
| 110 | ASIC_T_SHIFT; |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 111 | int actual_temp = temp & 0xff; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 112 | |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 113 | if (temp & 0x100) |
| 114 | actual_temp -= 256; |
| 115 | |
| 116 | return actual_temp * 1000; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 117 | } |
| 118 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 119 | void r600_pm_get_dynpm_state(struct radeon_device *rdev) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 120 | { |
| 121 | int i; |
| 122 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 123 | rdev->pm.dynpm_can_upclock = true; |
| 124 | rdev->pm.dynpm_can_downclock = true; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 125 | |
| 126 | /* power state array is low to high, default is first */ |
| 127 | if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { |
| 128 | int min_power_state_index = 0; |
| 129 | |
| 130 | if (rdev->pm.num_power_states > 2) |
| 131 | min_power_state_index = 1; |
| 132 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 133 | switch (rdev->pm.dynpm_planned_action) { |
| 134 | case DYNPM_ACTION_MINIMUM: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 135 | rdev->pm.requested_power_state_index = min_power_state_index; |
| 136 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 137 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 138 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 139 | case DYNPM_ACTION_DOWNCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 140 | if (rdev->pm.current_power_state_index == min_power_state_index) { |
| 141 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 142 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 143 | } else { |
| 144 | if (rdev->pm.active_crtc_count > 1) { |
| 145 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 146 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 147 | continue; |
| 148 | else if (i >= rdev->pm.current_power_state_index) { |
| 149 | rdev->pm.requested_power_state_index = |
| 150 | rdev->pm.current_power_state_index; |
| 151 | break; |
| 152 | } else { |
| 153 | rdev->pm.requested_power_state_index = i; |
| 154 | break; |
| 155 | } |
| 156 | } |
Alex Deucher | 773c3fa | 2010-06-25 16:21:27 -0400 | [diff] [blame] | 157 | } else { |
| 158 | if (rdev->pm.current_power_state_index == 0) |
| 159 | rdev->pm.requested_power_state_index = |
| 160 | rdev->pm.num_power_states - 1; |
| 161 | else |
| 162 | rdev->pm.requested_power_state_index = |
| 163 | rdev->pm.current_power_state_index - 1; |
| 164 | } |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 165 | } |
| 166 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 167 | /* don't use the power state if crtcs are active and no display flag is set */ |
| 168 | if ((rdev->pm.active_crtc_count > 0) && |
| 169 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 170 | clock_info[rdev->pm.requested_clock_mode_index].flags & |
| 171 | RADEON_PM_MODE_NO_DISPLAY)) { |
| 172 | rdev->pm.requested_power_state_index++; |
| 173 | } |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 174 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 175 | case DYNPM_ACTION_UPCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 176 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
| 177 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 178 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 179 | } else { |
| 180 | if (rdev->pm.active_crtc_count > 1) { |
| 181 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 182 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 183 | continue; |
| 184 | else if (i <= rdev->pm.current_power_state_index) { |
| 185 | rdev->pm.requested_power_state_index = |
| 186 | rdev->pm.current_power_state_index; |
| 187 | break; |
| 188 | } else { |
| 189 | rdev->pm.requested_power_state_index = i; |
| 190 | break; |
| 191 | } |
| 192 | } |
| 193 | } else |
| 194 | rdev->pm.requested_power_state_index = |
| 195 | rdev->pm.current_power_state_index + 1; |
| 196 | } |
| 197 | rdev->pm.requested_clock_mode_index = 0; |
| 198 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 199 | case DYNPM_ACTION_DEFAULT: |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 200 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
| 201 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 202 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 203 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 204 | case DYNPM_ACTION_NONE: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 205 | default: |
| 206 | DRM_ERROR("Requested mode for not defined action\n"); |
| 207 | return; |
| 208 | } |
| 209 | } else { |
| 210 | /* XXX select a power state based on AC/DC, single/dualhead, etc. */ |
| 211 | /* for now just select the first power state and switch between clock modes */ |
| 212 | /* power state array is low to high, default is first (0) */ |
| 213 | if (rdev->pm.active_crtc_count > 1) { |
| 214 | rdev->pm.requested_power_state_index = -1; |
| 215 | /* start at 1 as we don't want the default mode */ |
| 216 | for (i = 1; i < rdev->pm.num_power_states; i++) { |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 217 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 218 | continue; |
| 219 | else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || |
| 220 | (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { |
| 221 | rdev->pm.requested_power_state_index = i; |
| 222 | break; |
| 223 | } |
| 224 | } |
| 225 | /* if nothing selected, grab the default state. */ |
| 226 | if (rdev->pm.requested_power_state_index == -1) |
| 227 | rdev->pm.requested_power_state_index = 0; |
| 228 | } else |
| 229 | rdev->pm.requested_power_state_index = 1; |
| 230 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 231 | switch (rdev->pm.dynpm_planned_action) { |
| 232 | case DYNPM_ACTION_MINIMUM: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 233 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 234 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 235 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 236 | case DYNPM_ACTION_DOWNCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 237 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
| 238 | if (rdev->pm.current_clock_mode_index == 0) { |
| 239 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 240 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 241 | } else |
| 242 | rdev->pm.requested_clock_mode_index = |
| 243 | rdev->pm.current_clock_mode_index - 1; |
| 244 | } else { |
| 245 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 246 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 247 | } |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 248 | /* don't use the power state if crtcs are active and no display flag is set */ |
| 249 | if ((rdev->pm.active_crtc_count > 0) && |
| 250 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 251 | clock_info[rdev->pm.requested_clock_mode_index].flags & |
| 252 | RADEON_PM_MODE_NO_DISPLAY)) { |
| 253 | rdev->pm.requested_clock_mode_index++; |
| 254 | } |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 255 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 256 | case DYNPM_ACTION_UPCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 257 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
| 258 | if (rdev->pm.current_clock_mode_index == |
| 259 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { |
| 260 | rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 261 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 262 | } else |
| 263 | rdev->pm.requested_clock_mode_index = |
| 264 | rdev->pm.current_clock_mode_index + 1; |
| 265 | } else { |
| 266 | rdev->pm.requested_clock_mode_index = |
| 267 | rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 268 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 269 | } |
| 270 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 271 | case DYNPM_ACTION_DEFAULT: |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 272 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
| 273 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 274 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 275 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 276 | case DYNPM_ACTION_NONE: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 277 | default: |
| 278 | DRM_ERROR("Requested mode for not defined action\n"); |
| 279 | return; |
| 280 | } |
| 281 | } |
| 282 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 283 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
Alex Deucher | ce8a3eb | 2010-05-07 16:58:27 -0400 | [diff] [blame] | 284 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 285 | clock_info[rdev->pm.requested_clock_mode_index].sclk, |
| 286 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 287 | clock_info[rdev->pm.requested_clock_mode_index].mclk, |
| 288 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 289 | pcie_lanes); |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 290 | } |
| 291 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 292 | void rs780_pm_init_profile(struct radeon_device *rdev) |
| 293 | { |
| 294 | if (rdev->pm.num_power_states == 2) { |
| 295 | /* default */ |
| 296 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 297 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 298 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 299 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
| 300 | /* low sh */ |
| 301 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; |
| 302 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; |
| 303 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
| 304 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 305 | /* mid sh */ |
| 306 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; |
| 307 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; |
| 308 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 309 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 310 | /* high sh */ |
| 311 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; |
| 312 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; |
| 313 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 314 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
| 315 | /* low mh */ |
| 316 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; |
| 317 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; |
| 318 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
| 319 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 320 | /* mid mh */ |
| 321 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; |
| 322 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; |
| 323 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 324 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 325 | /* high mh */ |
| 326 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; |
| 327 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; |
| 328 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 329 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
| 330 | } else if (rdev->pm.num_power_states == 3) { |
| 331 | /* default */ |
| 332 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 333 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 334 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 335 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
| 336 | /* low sh */ |
| 337 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; |
| 338 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; |
| 339 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
| 340 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 341 | /* mid sh */ |
| 342 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; |
| 343 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; |
| 344 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 345 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 346 | /* high sh */ |
| 347 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; |
| 348 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; |
| 349 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 350 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
| 351 | /* low mh */ |
| 352 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; |
| 353 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; |
| 354 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
| 355 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 356 | /* mid mh */ |
| 357 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; |
| 358 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; |
| 359 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 360 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 361 | /* high mh */ |
| 362 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; |
| 363 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; |
| 364 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 365 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
| 366 | } else { |
| 367 | /* default */ |
| 368 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 369 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 370 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 371 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
| 372 | /* low sh */ |
| 373 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; |
| 374 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; |
| 375 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
| 376 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 377 | /* mid sh */ |
| 378 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; |
| 379 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; |
| 380 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 381 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 382 | /* high sh */ |
| 383 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; |
| 384 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; |
| 385 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 386 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
| 387 | /* low mh */ |
| 388 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; |
| 389 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; |
| 390 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
| 391 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 392 | /* mid mh */ |
| 393 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; |
| 394 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; |
| 395 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 396 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 397 | /* high mh */ |
| 398 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; |
| 399 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; |
| 400 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 401 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | void r600_pm_init_profile(struct radeon_device *rdev) |
| 406 | { |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 407 | int idx; |
| 408 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 409 | if (rdev->family == CHIP_R600) { |
| 410 | /* XXX */ |
| 411 | /* default */ |
| 412 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 413 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 414 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 415 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 416 | /* low sh */ |
| 417 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 418 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 419 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 420 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 421 | /* mid sh */ |
| 422 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 423 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 424 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 425 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 426 | /* high sh */ |
| 427 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 428 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 429 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 430 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 431 | /* low mh */ |
| 432 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 433 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 434 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 435 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 436 | /* mid mh */ |
| 437 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 438 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 439 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 440 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 441 | /* high mh */ |
| 442 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 443 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 444 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 445 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 446 | } else { |
| 447 | if (rdev->pm.num_power_states < 4) { |
| 448 | /* default */ |
| 449 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 450 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 451 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 452 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; |
| 453 | /* low sh */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 454 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; |
| 455 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; |
| 456 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 457 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
| 458 | /* mid sh */ |
| 459 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; |
| 460 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; |
| 461 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 462 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 463 | /* high sh */ |
| 464 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; |
| 465 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; |
| 466 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 467 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; |
| 468 | /* low mh */ |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 469 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; |
| 470 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 471 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 472 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
| 473 | /* low mh */ |
| 474 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; |
| 475 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; |
| 476 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 477 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 478 | /* high mh */ |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 479 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; |
| 480 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; |
| 481 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 482 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; |
| 483 | } else { |
| 484 | /* default */ |
| 485 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 486 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 487 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 488 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; |
| 489 | /* low sh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 490 | if (rdev->flags & RADEON_IS_MOBILITY) |
| 491 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); |
| 492 | else |
| 493 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); |
| 494 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; |
| 495 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; |
| 496 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
| 497 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 498 | /* mid sh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 499 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; |
| 500 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; |
| 501 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 502 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 503 | /* high sh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 504 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); |
| 505 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; |
| 506 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 507 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 508 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; |
| 509 | /* low mh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 510 | if (rdev->flags & RADEON_IS_MOBILITY) |
| 511 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); |
| 512 | else |
| 513 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); |
| 514 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; |
| 515 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; |
| 516 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
| 517 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 518 | /* mid mh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 519 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; |
| 520 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; |
| 521 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 522 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 523 | /* high mh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 524 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); |
| 525 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; |
| 526 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 527 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 528 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; |
| 529 | } |
| 530 | } |
Alex Deucher | bae6b562 | 2010-04-22 13:38:05 -0400 | [diff] [blame] | 531 | } |
| 532 | |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 533 | void r600_pm_misc(struct radeon_device *rdev) |
| 534 | { |
Rafał Miłecki | a081a9d | 2010-06-07 18:20:25 -0400 | [diff] [blame] | 535 | int req_ps_idx = rdev->pm.requested_power_state_index; |
| 536 | int req_cm_idx = rdev->pm.requested_clock_mode_index; |
| 537 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; |
| 538 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 539 | |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 540 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
Alex Deucher | a377e18 | 2011-06-20 13:00:31 -0400 | [diff] [blame] | 541 | /* 0xff01 is a flag rather then an actual voltage */ |
| 542 | if (voltage->voltage == 0xff01) |
| 543 | return; |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 544 | if (voltage->voltage != rdev->pm.current_vddc) { |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 545 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 546 | rdev->pm.current_vddc = voltage->voltage; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 547 | DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 548 | } |
| 549 | } |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 550 | } |
| 551 | |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 552 | bool r600_gui_idle(struct radeon_device *rdev) |
| 553 | { |
| 554 | if (RREG32(GRBM_STATUS) & GUI_ACTIVE) |
| 555 | return false; |
| 556 | else |
| 557 | return true; |
| 558 | } |
| 559 | |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 560 | /* hpd for digital panel detect/disconnect */ |
| 561 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
| 562 | { |
| 563 | bool connected = false; |
| 564 | |
| 565 | if (ASIC_IS_DCE3(rdev)) { |
| 566 | switch (hpd) { |
| 567 | case RADEON_HPD_1: |
| 568 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) |
| 569 | connected = true; |
| 570 | break; |
| 571 | case RADEON_HPD_2: |
| 572 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) |
| 573 | connected = true; |
| 574 | break; |
| 575 | case RADEON_HPD_3: |
| 576 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) |
| 577 | connected = true; |
| 578 | break; |
| 579 | case RADEON_HPD_4: |
| 580 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) |
| 581 | connected = true; |
| 582 | break; |
| 583 | /* DCE 3.2 */ |
| 584 | case RADEON_HPD_5: |
| 585 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) |
| 586 | connected = true; |
| 587 | break; |
| 588 | case RADEON_HPD_6: |
| 589 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) |
| 590 | connected = true; |
| 591 | break; |
| 592 | default: |
| 593 | break; |
| 594 | } |
| 595 | } else { |
| 596 | switch (hpd) { |
| 597 | case RADEON_HPD_1: |
| 598 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) |
| 599 | connected = true; |
| 600 | break; |
| 601 | case RADEON_HPD_2: |
| 602 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) |
| 603 | connected = true; |
| 604 | break; |
| 605 | case RADEON_HPD_3: |
| 606 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) |
| 607 | connected = true; |
| 608 | break; |
| 609 | default: |
| 610 | break; |
| 611 | } |
| 612 | } |
| 613 | return connected; |
| 614 | } |
| 615 | |
| 616 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 617 | enum radeon_hpd_id hpd) |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 618 | { |
| 619 | u32 tmp; |
| 620 | bool connected = r600_hpd_sense(rdev, hpd); |
| 621 | |
| 622 | if (ASIC_IS_DCE3(rdev)) { |
| 623 | switch (hpd) { |
| 624 | case RADEON_HPD_1: |
| 625 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
| 626 | if (connected) |
| 627 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 628 | else |
| 629 | tmp |= DC_HPDx_INT_POLARITY; |
| 630 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
| 631 | break; |
| 632 | case RADEON_HPD_2: |
| 633 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
| 634 | if (connected) |
| 635 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 636 | else |
| 637 | tmp |= DC_HPDx_INT_POLARITY; |
| 638 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
| 639 | break; |
| 640 | case RADEON_HPD_3: |
| 641 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
| 642 | if (connected) |
| 643 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 644 | else |
| 645 | tmp |= DC_HPDx_INT_POLARITY; |
| 646 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
| 647 | break; |
| 648 | case RADEON_HPD_4: |
| 649 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
| 650 | if (connected) |
| 651 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 652 | else |
| 653 | tmp |= DC_HPDx_INT_POLARITY; |
| 654 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
| 655 | break; |
| 656 | case RADEON_HPD_5: |
| 657 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
| 658 | if (connected) |
| 659 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 660 | else |
| 661 | tmp |= DC_HPDx_INT_POLARITY; |
| 662 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
| 663 | break; |
| 664 | /* DCE 3.2 */ |
| 665 | case RADEON_HPD_6: |
| 666 | tmp = RREG32(DC_HPD6_INT_CONTROL); |
| 667 | if (connected) |
| 668 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 669 | else |
| 670 | tmp |= DC_HPDx_INT_POLARITY; |
| 671 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
| 672 | break; |
| 673 | default: |
| 674 | break; |
| 675 | } |
| 676 | } else { |
| 677 | switch (hpd) { |
| 678 | case RADEON_HPD_1: |
| 679 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); |
| 680 | if (connected) |
| 681 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 682 | else |
| 683 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 684 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
| 685 | break; |
| 686 | case RADEON_HPD_2: |
| 687 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); |
| 688 | if (connected) |
| 689 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 690 | else |
| 691 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 692 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
| 693 | break; |
| 694 | case RADEON_HPD_3: |
| 695 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); |
| 696 | if (connected) |
| 697 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 698 | else |
| 699 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 700 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
| 701 | break; |
| 702 | default: |
| 703 | break; |
| 704 | } |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | void r600_hpd_init(struct radeon_device *rdev) |
| 709 | { |
| 710 | struct drm_device *dev = rdev->ddev; |
| 711 | struct drm_connector *connector; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 712 | unsigned enable = 0; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 713 | |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 714 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 715 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 716 | |
Jerome Glisse | 455c89b | 2012-05-04 11:06:22 -0400 | [diff] [blame] | 717 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || |
| 718 | connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { |
| 719 | /* don't try to enable hpd on eDP or LVDS avoid breaking the |
| 720 | * aux dp channel on imac and help (but not completely fix) |
| 721 | * https://bugzilla.redhat.com/show_bug.cgi?id=726143 |
| 722 | */ |
| 723 | continue; |
| 724 | } |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 725 | if (ASIC_IS_DCE3(rdev)) { |
| 726 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); |
| 727 | if (ASIC_IS_DCE32(rdev)) |
| 728 | tmp |= DC_HPDx_EN; |
| 729 | |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 730 | switch (radeon_connector->hpd.hpd) { |
| 731 | case RADEON_HPD_1: |
| 732 | WREG32(DC_HPD1_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 733 | break; |
| 734 | case RADEON_HPD_2: |
| 735 | WREG32(DC_HPD2_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 736 | break; |
| 737 | case RADEON_HPD_3: |
| 738 | WREG32(DC_HPD3_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 739 | break; |
| 740 | case RADEON_HPD_4: |
| 741 | WREG32(DC_HPD4_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 742 | break; |
| 743 | /* DCE 3.2 */ |
| 744 | case RADEON_HPD_5: |
| 745 | WREG32(DC_HPD5_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 746 | break; |
| 747 | case RADEON_HPD_6: |
| 748 | WREG32(DC_HPD6_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 749 | break; |
| 750 | default: |
| 751 | break; |
| 752 | } |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 753 | } else { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 754 | switch (radeon_connector->hpd.hpd) { |
| 755 | case RADEON_HPD_1: |
| 756 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 757 | break; |
| 758 | case RADEON_HPD_2: |
| 759 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 760 | break; |
| 761 | case RADEON_HPD_3: |
| 762 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 763 | break; |
| 764 | default: |
| 765 | break; |
| 766 | } |
| 767 | } |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 768 | enable |= 1 << radeon_connector->hpd.hpd; |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 769 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 770 | } |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 771 | radeon_irq_kms_enable_hpd(rdev, enable); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | void r600_hpd_fini(struct radeon_device *rdev) |
| 775 | { |
| 776 | struct drm_device *dev = rdev->ddev; |
| 777 | struct drm_connector *connector; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 778 | unsigned disable = 0; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 779 | |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 780 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 781 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 782 | if (ASIC_IS_DCE3(rdev)) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 783 | switch (radeon_connector->hpd.hpd) { |
| 784 | case RADEON_HPD_1: |
| 785 | WREG32(DC_HPD1_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 786 | break; |
| 787 | case RADEON_HPD_2: |
| 788 | WREG32(DC_HPD2_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 789 | break; |
| 790 | case RADEON_HPD_3: |
| 791 | WREG32(DC_HPD3_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 792 | break; |
| 793 | case RADEON_HPD_4: |
| 794 | WREG32(DC_HPD4_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 795 | break; |
| 796 | /* DCE 3.2 */ |
| 797 | case RADEON_HPD_5: |
| 798 | WREG32(DC_HPD5_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 799 | break; |
| 800 | case RADEON_HPD_6: |
| 801 | WREG32(DC_HPD6_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 802 | break; |
| 803 | default: |
| 804 | break; |
| 805 | } |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 806 | } else { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 807 | switch (radeon_connector->hpd.hpd) { |
| 808 | case RADEON_HPD_1: |
| 809 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 810 | break; |
| 811 | case RADEON_HPD_2: |
| 812 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 813 | break; |
| 814 | case RADEON_HPD_3: |
| 815 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 816 | break; |
| 817 | default: |
| 818 | break; |
| 819 | } |
| 820 | } |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 821 | disable |= 1 << radeon_connector->hpd.hpd; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 822 | } |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 823 | radeon_irq_kms_disable_hpd(rdev, disable); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 824 | } |
| 825 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 826 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 827 | * R600 PCIE GART |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 828 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 829 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 830 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 831 | unsigned i; |
| 832 | u32 tmp; |
| 833 | |
Dave Airlie | 2e98f10 | 2010-02-15 15:54:45 +1000 | [diff] [blame] | 834 | /* flush hdp cache so updates hit vram */ |
Alex Deucher | f3886f8 | 2010-12-08 10:05:34 -0500 | [diff] [blame] | 835 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
| 836 | !(rdev->flags & RADEON_IS_AGP)) { |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 837 | void __iomem *ptr = (void *)rdev->gart.ptr; |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 838 | u32 tmp; |
| 839 | |
| 840 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read |
| 841 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL |
Alex Deucher | f3886f8 | 2010-12-08 10:05:34 -0500 | [diff] [blame] | 842 | * This seems to cause problems on some AGP cards. Just use the old |
| 843 | * method for them. |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 844 | */ |
| 845 | WREG32(HDP_DEBUG1, 0); |
| 846 | tmp = readl((void __iomem *)ptr); |
| 847 | } else |
| 848 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
Dave Airlie | 2e98f10 | 2010-02-15 15:54:45 +1000 | [diff] [blame] | 849 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 850 | WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); |
| 851 | WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); |
| 852 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); |
| 853 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 854 | /* read MC_STATUS */ |
| 855 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); |
| 856 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; |
| 857 | if (tmp == 2) { |
| 858 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); |
| 859 | return; |
| 860 | } |
| 861 | if (tmp) { |
| 862 | return; |
| 863 | } |
| 864 | udelay(1); |
| 865 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 866 | } |
| 867 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 868 | int r600_pcie_gart_init(struct radeon_device *rdev) |
| 869 | { |
| 870 | int r; |
| 871 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 872 | if (rdev->gart.robj) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 873 | WARN(1, "R600 PCIE GART already initialized\n"); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 874 | return 0; |
| 875 | } |
| 876 | /* Initialize common gart structure */ |
| 877 | r = radeon_gart_init(rdev); |
| 878 | if (r) |
| 879 | return r; |
| 880 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
| 881 | return radeon_gart_table_vram_alloc(rdev); |
| 882 | } |
| 883 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 884 | static int r600_pcie_gart_enable(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 885 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 886 | u32 tmp; |
| 887 | int r, i; |
| 888 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 889 | if (rdev->gart.robj == NULL) { |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 890 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| 891 | return -EINVAL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 892 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 893 | r = radeon_gart_table_vram_pin(rdev); |
| 894 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 895 | return r; |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 896 | radeon_gart_restore(rdev); |
Dave Airlie | bc1a631 | 2009-09-15 11:07:52 +1000 | [diff] [blame] | 897 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 898 | /* Setup L2 cache */ |
| 899 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| 900 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 901 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 902 | WREG32(VM_L2_CNTL2, 0); |
| 903 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); |
| 904 | /* Setup TLB control */ |
| 905 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| 906 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 907 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | |
| 908 | ENABLE_WAIT_L2_QUERY; |
| 909 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
| 910 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
| 911 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); |
| 912 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
| 913 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); |
| 914 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); |
| 915 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); |
| 916 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
| 917 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
| 918 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
| 919 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
| 920 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
| 921 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| 922 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| 923 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 924 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 925 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
| 926 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
| 927 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
| 928 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
| 929 | (u32)(rdev->dummy_page.addr >> 12)); |
| 930 | for (i = 1; i < 7; i++) |
| 931 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 932 | |
| 933 | r600_pcie_gart_tlb_flush(rdev); |
Tormod Volden | fcf4de5 | 2011-08-31 21:54:07 +0000 | [diff] [blame] | 934 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 935 | (unsigned)(rdev->mc.gtt_size >> 20), |
| 936 | (unsigned long long)rdev->gart.table_addr); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 937 | rdev->gart.ready = true; |
| 938 | return 0; |
| 939 | } |
| 940 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 941 | static void r600_pcie_gart_disable(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 942 | { |
| 943 | u32 tmp; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 944 | int i; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 945 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 946 | /* Disable all tables */ |
| 947 | for (i = 0; i < 7; i++) |
| 948 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 949 | |
| 950 | /* Disable L2 cache */ |
| 951 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
| 952 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 953 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); |
| 954 | /* Setup L1 TLB control */ |
| 955 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | |
| 956 | ENABLE_WAIT_L2_QUERY; |
| 957 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); |
| 958 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); |
| 959 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); |
| 960 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
| 961 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
| 962 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
| 963 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
| 964 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
| 965 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); |
| 966 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); |
| 967 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
| 968 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
| 969 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); |
| 970 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 971 | radeon_gart_table_vram_unpin(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 972 | } |
| 973 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 974 | static void r600_pcie_gart_fini(struct radeon_device *rdev) |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 975 | { |
Jerome Glisse | f927456 | 2010-03-17 14:44:29 +0000 | [diff] [blame] | 976 | radeon_gart_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 977 | r600_pcie_gart_disable(rdev); |
| 978 | radeon_gart_table_vram_free(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 979 | } |
| 980 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 981 | static void r600_agp_enable(struct radeon_device *rdev) |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 982 | { |
| 983 | u32 tmp; |
| 984 | int i; |
| 985 | |
| 986 | /* Setup L2 cache */ |
| 987 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| 988 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 989 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 990 | WREG32(VM_L2_CNTL2, 0); |
| 991 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); |
| 992 | /* Setup TLB control */ |
| 993 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| 994 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 995 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | |
| 996 | ENABLE_WAIT_L2_QUERY; |
| 997 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
| 998 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
| 999 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); |
| 1000 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
| 1001 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); |
| 1002 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); |
| 1003 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); |
| 1004 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
| 1005 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
| 1006 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
| 1007 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
| 1008 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
| 1009 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| 1010 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| 1011 | for (i = 0; i < 7; i++) |
| 1012 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 1013 | } |
| 1014 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1015 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
| 1016 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1017 | unsigned i; |
| 1018 | u32 tmp; |
| 1019 | |
| 1020 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 1021 | /* read MC_STATUS */ |
| 1022 | tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; |
| 1023 | if (!tmp) |
| 1024 | return 0; |
| 1025 | udelay(1); |
| 1026 | } |
| 1027 | return -1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1028 | } |
| 1029 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1030 | static void r600_mc_program(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1031 | { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1032 | struct rv515_mc_save save; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1033 | u32 tmp; |
| 1034 | int i, j; |
| 1035 | |
| 1036 | /* Initialize HDP */ |
| 1037 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| 1038 | WREG32((0x2c14 + j), 0x00000000); |
| 1039 | WREG32((0x2c18 + j), 0x00000000); |
| 1040 | WREG32((0x2c1c + j), 0x00000000); |
| 1041 | WREG32((0x2c20 + j), 0x00000000); |
| 1042 | WREG32((0x2c24 + j), 0x00000000); |
| 1043 | } |
| 1044 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); |
| 1045 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1046 | rv515_mc_stop(rdev, &save); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1047 | if (r600_mc_wait_for_idle(rdev)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1048 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1049 | } |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1050 | /* Lockout access through VGA aperture (doesn't exist before R600) */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1051 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1052 | /* Update configuration */ |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1053 | if (rdev->flags & RADEON_IS_AGP) { |
| 1054 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
| 1055 | /* VRAM before AGP */ |
| 1056 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 1057 | rdev->mc.vram_start >> 12); |
| 1058 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 1059 | rdev->mc.gtt_end >> 12); |
| 1060 | } else { |
| 1061 | /* VRAM after AGP */ |
| 1062 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 1063 | rdev->mc.gtt_start >> 12); |
| 1064 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 1065 | rdev->mc.vram_end >> 12); |
| 1066 | } |
| 1067 | } else { |
| 1068 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); |
| 1069 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); |
| 1070 | } |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1071 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1072 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1073 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
| 1074 | WREG32(MC_VM_FB_LOCATION, tmp); |
| 1075 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
| 1076 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
Jerome Glisse | 46fcd2b | 2010-06-03 19:34:48 +0200 | [diff] [blame] | 1077 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1078 | if (rdev->flags & RADEON_IS_AGP) { |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1079 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
| 1080 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1081 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
| 1082 | } else { |
| 1083 | WREG32(MC_VM_AGP_BASE, 0); |
| 1084 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
| 1085 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
| 1086 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1087 | if (r600_mc_wait_for_idle(rdev)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1088 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1089 | } |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1090 | rv515_mc_resume(rdev, &save); |
Dave Airlie | 698443d | 2009-09-18 14:16:38 +1000 | [diff] [blame] | 1091 | /* we need to own VRAM, so turn off the VGA renderer here |
| 1092 | * to stop it overwriting our objects */ |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1093 | rv515_vga_render_disable(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1094 | } |
| 1095 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1096 | /** |
| 1097 | * r600_vram_gtt_location - try to find VRAM & GTT location |
| 1098 | * @rdev: radeon device structure holding all necessary informations |
| 1099 | * @mc: memory controller structure holding memory informations |
| 1100 | * |
| 1101 | * Function will place try to place VRAM at same place as in CPU (PCI) |
| 1102 | * address space as some GPU seems to have issue when we reprogram at |
| 1103 | * different address space. |
| 1104 | * |
| 1105 | * If there is not enough space to fit the unvisible VRAM after the |
| 1106 | * aperture then we limit the VRAM size to the aperture. |
| 1107 | * |
| 1108 | * If we are using AGP then place VRAM adjacent to AGP aperture are we need |
| 1109 | * them to be in one from GPU point of view so that we can program GPU to |
| 1110 | * catch access outside them (weird GPU policy see ??). |
| 1111 | * |
| 1112 | * This function will never fails, worst case are limiting VRAM or GTT. |
| 1113 | * |
| 1114 | * Note: GTT start, end, size should be initialized before calling this |
| 1115 | * function on AGP platform. |
| 1116 | */ |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1117 | static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1118 | { |
| 1119 | u64 size_bf, size_af; |
| 1120 | |
| 1121 | if (mc->mc_vram_size > 0xE0000000) { |
| 1122 | /* leave room for at least 512M GTT */ |
| 1123 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1124 | mc->real_vram_size = 0xE0000000; |
| 1125 | mc->mc_vram_size = 0xE0000000; |
| 1126 | } |
| 1127 | if (rdev->flags & RADEON_IS_AGP) { |
| 1128 | size_bf = mc->gtt_start; |
Jerome Glisse | dfc6ae5 | 2012-04-17 16:51:38 -0400 | [diff] [blame] | 1129 | size_af = 0xFFFFFFFF - mc->gtt_end; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1130 | if (size_bf > size_af) { |
| 1131 | if (mc->mc_vram_size > size_bf) { |
| 1132 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1133 | mc->real_vram_size = size_bf; |
| 1134 | mc->mc_vram_size = size_bf; |
| 1135 | } |
| 1136 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; |
| 1137 | } else { |
| 1138 | if (mc->mc_vram_size > size_af) { |
| 1139 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1140 | mc->real_vram_size = size_af; |
| 1141 | mc->mc_vram_size = size_af; |
| 1142 | } |
Jerome Glisse | dfc6ae5 | 2012-04-17 16:51:38 -0400 | [diff] [blame] | 1143 | mc->vram_start = mc->gtt_end + 1; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1144 | } |
| 1145 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
| 1146 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
| 1147 | mc->mc_vram_size >> 20, mc->vram_start, |
| 1148 | mc->vram_end, mc->real_vram_size >> 20); |
| 1149 | } else { |
| 1150 | u64 base = 0; |
Alex Deucher | 8961d52 | 2010-12-03 14:37:22 -0500 | [diff] [blame] | 1151 | if (rdev->flags & RADEON_IS_IGP) { |
| 1152 | base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; |
| 1153 | base <<= 24; |
| 1154 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1155 | radeon_vram_location(rdev, &rdev->mc, base); |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 1156 | rdev->mc.gtt_base_align = 0; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1157 | radeon_gtt_location(rdev, mc); |
| 1158 | } |
| 1159 | } |
| 1160 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 1161 | static int r600_mc_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1162 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1163 | u32 tmp; |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1164 | int chansize, numchan; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1165 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1166 | /* Get VRAM informations */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1167 | rdev->mc.vram_is_ddr = true; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1168 | tmp = RREG32(RAMCFG); |
| 1169 | if (tmp & CHANSIZE_OVERRIDE) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1170 | chansize = 16; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1171 | } else if (tmp & CHANSIZE_MASK) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1172 | chansize = 64; |
| 1173 | } else { |
| 1174 | chansize = 32; |
| 1175 | } |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1176 | tmp = RREG32(CHMAP); |
| 1177 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
| 1178 | case 0: |
| 1179 | default: |
| 1180 | numchan = 1; |
| 1181 | break; |
| 1182 | case 1: |
| 1183 | numchan = 2; |
| 1184 | break; |
| 1185 | case 2: |
| 1186 | numchan = 4; |
| 1187 | break; |
| 1188 | case 3: |
| 1189 | numchan = 8; |
| 1190 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1191 | } |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1192 | rdev->mc.vram_width = numchan * chansize; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1193 | /* Could aper size report 0 ? */ |
Jordan Crouse | 01d73a6 | 2010-05-27 13:40:24 -0600 | [diff] [blame] | 1194 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
| 1195 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1196 | /* Setup GPU memory space */ |
| 1197 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
| 1198 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
Jerome Glisse | 51e5fcd | 2010-02-19 14:33:54 +0000 | [diff] [blame] | 1199 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1200 | r600_vram_gtt_location(rdev, &rdev->mc); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1201 | |
Alex Deucher | f892034 | 2010-06-30 12:02:03 -0400 | [diff] [blame] | 1202 | if (rdev->flags & RADEON_IS_IGP) { |
| 1203 | rs690_pm_info(rdev); |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 1204 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
Alex Deucher | f892034 | 2010-06-30 12:02:03 -0400 | [diff] [blame] | 1205 | } |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1206 | radeon_update_bandwidth_info(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1207 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1208 | } |
| 1209 | |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1210 | int r600_vram_scratch_init(struct radeon_device *rdev) |
| 1211 | { |
| 1212 | int r; |
| 1213 | |
| 1214 | if (rdev->vram_scratch.robj == NULL) { |
| 1215 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, |
| 1216 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 1217 | NULL, &rdev->vram_scratch.robj); |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1218 | if (r) { |
| 1219 | return r; |
| 1220 | } |
| 1221 | } |
| 1222 | |
| 1223 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); |
| 1224 | if (unlikely(r != 0)) |
| 1225 | return r; |
| 1226 | r = radeon_bo_pin(rdev->vram_scratch.robj, |
| 1227 | RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); |
| 1228 | if (r) { |
| 1229 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
| 1230 | return r; |
| 1231 | } |
| 1232 | r = radeon_bo_kmap(rdev->vram_scratch.robj, |
| 1233 | (void **)&rdev->vram_scratch.ptr); |
| 1234 | if (r) |
| 1235 | radeon_bo_unpin(rdev->vram_scratch.robj); |
| 1236 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
| 1237 | |
| 1238 | return r; |
| 1239 | } |
| 1240 | |
| 1241 | void r600_vram_scratch_fini(struct radeon_device *rdev) |
| 1242 | { |
| 1243 | int r; |
| 1244 | |
| 1245 | if (rdev->vram_scratch.robj == NULL) { |
| 1246 | return; |
| 1247 | } |
| 1248 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); |
| 1249 | if (likely(r == 0)) { |
| 1250 | radeon_bo_kunmap(rdev->vram_scratch.robj); |
| 1251 | radeon_bo_unpin(rdev->vram_scratch.robj); |
| 1252 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
| 1253 | } |
| 1254 | radeon_bo_unref(&rdev->vram_scratch.robj); |
| 1255 | } |
| 1256 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1257 | /* We doesn't check that the GPU really needs a reset we simply do the |
| 1258 | * reset, it's up to the caller to determine if the GPU needs one. We |
| 1259 | * might add an helper function to check that. |
| 1260 | */ |
Alex Deucher | 71e3d15 | 2013-01-03 12:20:35 -0500 | [diff] [blame] | 1261 | static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1262 | { |
| 1263 | u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
| 1264 | S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | |
| 1265 | S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | |
| 1266 | S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | |
| 1267 | S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | |
| 1268 | S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | |
| 1269 | S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | |
| 1270 | S_008010_GUI_ACTIVE(1); |
| 1271 | u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | |
| 1272 | S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | |
| 1273 | S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | |
| 1274 | S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | |
| 1275 | S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | |
| 1276 | S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | |
| 1277 | S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | |
| 1278 | S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1279 | u32 tmp; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1280 | |
Alex Deucher | 8d96fe9 | 2011-01-21 15:38:22 +0000 | [diff] [blame] | 1281 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
Alex Deucher | 71e3d15 | 2013-01-03 12:20:35 -0500 | [diff] [blame] | 1282 | return; |
Alex Deucher | 8d96fe9 | 2011-01-21 15:38:22 +0000 | [diff] [blame] | 1283 | |
Jerome Glisse | 64c56e8 | 2013-01-02 17:30:35 -0500 | [diff] [blame] | 1284 | dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1285 | RREG32(R_008010_GRBM_STATUS)); |
Jerome Glisse | 64c56e8 | 2013-01-02 17:30:35 -0500 | [diff] [blame] | 1286 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1287 | RREG32(R_008014_GRBM_STATUS2)); |
Jerome Glisse | 64c56e8 | 2013-01-02 17:30:35 -0500 | [diff] [blame] | 1288 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1289 | RREG32(R_000E50_SRBM_STATUS)); |
Jerome Glisse | 440a7cd | 2012-06-27 12:25:01 -0400 | [diff] [blame] | 1290 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
| 1291 | RREG32(CP_STALLED_STAT1)); |
| 1292 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
| 1293 | RREG32(CP_STALLED_STAT2)); |
| 1294 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
| 1295 | RREG32(CP_BUSY_STAT)); |
| 1296 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
| 1297 | RREG32(CP_STAT)); |
Jerome Glisse | 64c56e8 | 2013-01-02 17:30:35 -0500 | [diff] [blame] | 1298 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1299 | /* Disable CP parsing/prefetching */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1300 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
Jerome Glisse | 64c56e8 | 2013-01-02 17:30:35 -0500 | [diff] [blame] | 1301 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1302 | /* Check if any of the rendering block is busy and reset it */ |
| 1303 | if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || |
| 1304 | (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1305 | tmp = S_008020_SOFT_RESET_CR(1) | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1306 | S_008020_SOFT_RESET_DB(1) | |
| 1307 | S_008020_SOFT_RESET_CB(1) | |
| 1308 | S_008020_SOFT_RESET_PA(1) | |
| 1309 | S_008020_SOFT_RESET_SC(1) | |
| 1310 | S_008020_SOFT_RESET_SMX(1) | |
| 1311 | S_008020_SOFT_RESET_SPI(1) | |
| 1312 | S_008020_SOFT_RESET_SX(1) | |
| 1313 | S_008020_SOFT_RESET_SH(1) | |
| 1314 | S_008020_SOFT_RESET_TC(1) | |
| 1315 | S_008020_SOFT_RESET_TA(1) | |
| 1316 | S_008020_SOFT_RESET_VC(1) | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1317 | S_008020_SOFT_RESET_VGT(1); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1318 | dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1319 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1320 | RREG32(R_008020_GRBM_SOFT_RESET); |
| 1321 | mdelay(15); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1322 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1323 | } |
| 1324 | /* Reset CP (we always reset CP) */ |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1325 | tmp = S_008020_SOFT_RESET_CP(1); |
| 1326 | dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
| 1327 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1328 | RREG32(R_008020_GRBM_SOFT_RESET); |
| 1329 | mdelay(15); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1330 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
Alex Deucher | 71e3d15 | 2013-01-03 12:20:35 -0500 | [diff] [blame] | 1331 | |
Jerome Glisse | 64c56e8 | 2013-01-02 17:30:35 -0500 | [diff] [blame] | 1332 | dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1333 | RREG32(R_008010_GRBM_STATUS)); |
Jerome Glisse | 64c56e8 | 2013-01-02 17:30:35 -0500 | [diff] [blame] | 1334 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1335 | RREG32(R_008014_GRBM_STATUS2)); |
Jerome Glisse | 64c56e8 | 2013-01-02 17:30:35 -0500 | [diff] [blame] | 1336 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1337 | RREG32(R_000E50_SRBM_STATUS)); |
Jerome Glisse | 440a7cd | 2012-06-27 12:25:01 -0400 | [diff] [blame] | 1338 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
| 1339 | RREG32(CP_STALLED_STAT1)); |
| 1340 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
| 1341 | RREG32(CP_STALLED_STAT2)); |
| 1342 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
| 1343 | RREG32(CP_BUSY_STAT)); |
| 1344 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
| 1345 | RREG32(CP_STAT)); |
Alex Deucher | 71e3d15 | 2013-01-03 12:20:35 -0500 | [diff] [blame] | 1346 | |
| 1347 | } |
| 1348 | |
| 1349 | static void r600_gpu_soft_reset_dma(struct radeon_device *rdev) |
| 1350 | { |
| 1351 | u32 tmp; |
| 1352 | |
| 1353 | if (RREG32(DMA_STATUS_REG) & DMA_IDLE) |
| 1354 | return; |
| 1355 | |
Jerome Glisse | eaaa698 | 2013-01-02 15:12:15 -0500 | [diff] [blame] | 1356 | dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", |
| 1357 | RREG32(DMA_STATUS_REG)); |
Alex Deucher | 71e3d15 | 2013-01-03 12:20:35 -0500 | [diff] [blame] | 1358 | |
| 1359 | /* Disable DMA */ |
| 1360 | tmp = RREG32(DMA_RB_CNTL); |
| 1361 | tmp &= ~DMA_RB_ENABLE; |
| 1362 | WREG32(DMA_RB_CNTL, tmp); |
| 1363 | |
| 1364 | /* Reset dma */ |
| 1365 | if (rdev->family >= CHIP_RV770) |
| 1366 | WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); |
| 1367 | else |
| 1368 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); |
| 1369 | RREG32(SRBM_SOFT_RESET); |
| 1370 | udelay(50); |
| 1371 | WREG32(SRBM_SOFT_RESET, 0); |
| 1372 | |
| 1373 | dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", |
| 1374 | RREG32(DMA_STATUS_REG)); |
| 1375 | } |
| 1376 | |
| 1377 | static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) |
| 1378 | { |
| 1379 | struct rv515_mc_save save; |
| 1380 | |
Alex Deucher | 19fc42e | 2013-01-14 11:04:39 -0500 | [diff] [blame^] | 1381 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
| 1382 | reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE); |
| 1383 | |
| 1384 | if (RREG32(DMA_STATUS_REG) & DMA_IDLE) |
| 1385 | reset_mask &= ~RADEON_RESET_DMA; |
| 1386 | |
Alex Deucher | 71e3d15 | 2013-01-03 12:20:35 -0500 | [diff] [blame] | 1387 | if (reset_mask == 0) |
| 1388 | return 0; |
| 1389 | |
| 1390 | dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); |
| 1391 | |
| 1392 | rv515_mc_stop(rdev, &save); |
| 1393 | if (r600_mc_wait_for_idle(rdev)) { |
| 1394 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
| 1395 | } |
| 1396 | |
| 1397 | if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) |
| 1398 | r600_gpu_soft_reset_gfx(rdev); |
| 1399 | |
| 1400 | if (reset_mask & RADEON_RESET_DMA) |
| 1401 | r600_gpu_soft_reset_dma(rdev); |
| 1402 | |
| 1403 | /* Wait a little for things to settle down */ |
| 1404 | mdelay(1); |
| 1405 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1406 | rv515_mc_resume(rdev, &save); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1407 | return 0; |
| 1408 | } |
| 1409 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1410 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1411 | { |
| 1412 | u32 srbm_status; |
| 1413 | u32 grbm_status; |
| 1414 | u32 grbm_status2; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1415 | |
| 1416 | srbm_status = RREG32(R_000E50_SRBM_STATUS); |
| 1417 | grbm_status = RREG32(R_008010_GRBM_STATUS); |
| 1418 | grbm_status2 = RREG32(R_008014_GRBM_STATUS2); |
| 1419 | if (!G_008010_GUI_ACTIVE(grbm_status)) { |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 1420 | radeon_ring_lockup_update(ring); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1421 | return false; |
| 1422 | } |
| 1423 | /* force CP activities */ |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 1424 | radeon_ring_force_activity(rdev, ring); |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 1425 | return radeon_ring_test_lockup(rdev, ring); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1426 | } |
| 1427 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1428 | /** |
| 1429 | * r600_dma_is_lockup - Check if the DMA engine is locked up |
| 1430 | * |
| 1431 | * @rdev: radeon_device pointer |
| 1432 | * @ring: radeon_ring structure holding ring information |
| 1433 | * |
| 1434 | * Check if the async DMA engine is locked up (r6xx-evergreen). |
| 1435 | * Returns true if the engine appears to be locked up, false if not. |
| 1436 | */ |
| 1437 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
| 1438 | { |
| 1439 | u32 dma_status_reg; |
| 1440 | |
| 1441 | dma_status_reg = RREG32(DMA_STATUS_REG); |
| 1442 | if (dma_status_reg & DMA_IDLE) { |
| 1443 | radeon_ring_lockup_update(ring); |
| 1444 | return false; |
| 1445 | } |
| 1446 | /* force ring activities */ |
| 1447 | radeon_ring_force_activity(rdev, ring); |
| 1448 | return radeon_ring_test_lockup(rdev, ring); |
| 1449 | } |
| 1450 | |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1451 | int r600_asic_reset(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1452 | { |
Alex Deucher | 71e3d15 | 2013-01-03 12:20:35 -0500 | [diff] [blame] | 1453 | return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX | |
| 1454 | RADEON_RESET_COMPUTE | |
| 1455 | RADEON_RESET_DMA)); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1456 | } |
| 1457 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1458 | u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
| 1459 | u32 tiling_pipe_num, |
| 1460 | u32 max_rb_num, |
| 1461 | u32 total_max_rb_num, |
| 1462 | u32 disabled_rb_mask) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1463 | { |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1464 | u32 rendering_pipe_num, rb_num_width, req_rb_num; |
| 1465 | u32 pipe_rb_ratio, pipe_rb_remain; |
| 1466 | u32 data = 0, mask = 1 << (max_rb_num - 1); |
| 1467 | unsigned i, j; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1468 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1469 | /* mask out the RBs that don't exist on that asic */ |
| 1470 | disabled_rb_mask |= (0xff << max_rb_num) & 0xff; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1471 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1472 | rendering_pipe_num = 1 << tiling_pipe_num; |
| 1473 | req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); |
| 1474 | BUG_ON(rendering_pipe_num < req_rb_num); |
| 1475 | |
| 1476 | pipe_rb_ratio = rendering_pipe_num / req_rb_num; |
| 1477 | pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; |
| 1478 | |
| 1479 | if (rdev->family <= CHIP_RV740) { |
| 1480 | /* r6xx/r7xx */ |
| 1481 | rb_num_width = 2; |
| 1482 | } else { |
| 1483 | /* eg+ */ |
| 1484 | rb_num_width = 4; |
| 1485 | } |
| 1486 | |
| 1487 | for (i = 0; i < max_rb_num; i++) { |
| 1488 | if (!(mask & disabled_rb_mask)) { |
| 1489 | for (j = 0; j < pipe_rb_ratio; j++) { |
| 1490 | data <<= rb_num_width; |
| 1491 | data |= max_rb_num - i - 1; |
| 1492 | } |
| 1493 | if (pipe_rb_remain) { |
| 1494 | data <<= rb_num_width; |
| 1495 | data |= max_rb_num - i - 1; |
| 1496 | pipe_rb_remain--; |
| 1497 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1498 | } |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1499 | mask >>= 1; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1500 | } |
| 1501 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1502 | return data; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1503 | } |
| 1504 | |
| 1505 | int r600_count_pipe_bits(uint32_t val) |
| 1506 | { |
Akinobu Mita | ef8cf3a | 2012-11-09 12:10:41 +0000 | [diff] [blame] | 1507 | return hweight32(val); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1508 | } |
| 1509 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 1510 | static void r600_gpu_init(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1511 | { |
| 1512 | u32 tiling_config; |
| 1513 | u32 ramcfg; |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1514 | u32 cc_rb_backend_disable; |
| 1515 | u32 cc_gc_shader_pipe_config; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1516 | u32 tmp; |
| 1517 | int i, j; |
| 1518 | u32 sq_config; |
| 1519 | u32 sq_gpr_resource_mgmt_1 = 0; |
| 1520 | u32 sq_gpr_resource_mgmt_2 = 0; |
| 1521 | u32 sq_thread_resource_mgmt = 0; |
| 1522 | u32 sq_stack_resource_mgmt_1 = 0; |
| 1523 | u32 sq_stack_resource_mgmt_2 = 0; |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1524 | u32 disabled_rb_mask; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1525 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1526 | rdev->config.r600.tiling_group_size = 256; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1527 | switch (rdev->family) { |
| 1528 | case CHIP_R600: |
| 1529 | rdev->config.r600.max_pipes = 4; |
| 1530 | rdev->config.r600.max_tile_pipes = 8; |
| 1531 | rdev->config.r600.max_simds = 4; |
| 1532 | rdev->config.r600.max_backends = 4; |
| 1533 | rdev->config.r600.max_gprs = 256; |
| 1534 | rdev->config.r600.max_threads = 192; |
| 1535 | rdev->config.r600.max_stack_entries = 256; |
| 1536 | rdev->config.r600.max_hw_contexts = 8; |
| 1537 | rdev->config.r600.max_gs_threads = 16; |
| 1538 | rdev->config.r600.sx_max_export_size = 128; |
| 1539 | rdev->config.r600.sx_max_export_pos_size = 16; |
| 1540 | rdev->config.r600.sx_max_export_smx_size = 128; |
| 1541 | rdev->config.r600.sq_num_cf_insts = 2; |
| 1542 | break; |
| 1543 | case CHIP_RV630: |
| 1544 | case CHIP_RV635: |
| 1545 | rdev->config.r600.max_pipes = 2; |
| 1546 | rdev->config.r600.max_tile_pipes = 2; |
| 1547 | rdev->config.r600.max_simds = 3; |
| 1548 | rdev->config.r600.max_backends = 1; |
| 1549 | rdev->config.r600.max_gprs = 128; |
| 1550 | rdev->config.r600.max_threads = 192; |
| 1551 | rdev->config.r600.max_stack_entries = 128; |
| 1552 | rdev->config.r600.max_hw_contexts = 8; |
| 1553 | rdev->config.r600.max_gs_threads = 4; |
| 1554 | rdev->config.r600.sx_max_export_size = 128; |
| 1555 | rdev->config.r600.sx_max_export_pos_size = 16; |
| 1556 | rdev->config.r600.sx_max_export_smx_size = 128; |
| 1557 | rdev->config.r600.sq_num_cf_insts = 2; |
| 1558 | break; |
| 1559 | case CHIP_RV610: |
| 1560 | case CHIP_RV620: |
| 1561 | case CHIP_RS780: |
| 1562 | case CHIP_RS880: |
| 1563 | rdev->config.r600.max_pipes = 1; |
| 1564 | rdev->config.r600.max_tile_pipes = 1; |
| 1565 | rdev->config.r600.max_simds = 2; |
| 1566 | rdev->config.r600.max_backends = 1; |
| 1567 | rdev->config.r600.max_gprs = 128; |
| 1568 | rdev->config.r600.max_threads = 192; |
| 1569 | rdev->config.r600.max_stack_entries = 128; |
| 1570 | rdev->config.r600.max_hw_contexts = 4; |
| 1571 | rdev->config.r600.max_gs_threads = 4; |
| 1572 | rdev->config.r600.sx_max_export_size = 128; |
| 1573 | rdev->config.r600.sx_max_export_pos_size = 16; |
| 1574 | rdev->config.r600.sx_max_export_smx_size = 128; |
| 1575 | rdev->config.r600.sq_num_cf_insts = 1; |
| 1576 | break; |
| 1577 | case CHIP_RV670: |
| 1578 | rdev->config.r600.max_pipes = 4; |
| 1579 | rdev->config.r600.max_tile_pipes = 4; |
| 1580 | rdev->config.r600.max_simds = 4; |
| 1581 | rdev->config.r600.max_backends = 4; |
| 1582 | rdev->config.r600.max_gprs = 192; |
| 1583 | rdev->config.r600.max_threads = 192; |
| 1584 | rdev->config.r600.max_stack_entries = 256; |
| 1585 | rdev->config.r600.max_hw_contexts = 8; |
| 1586 | rdev->config.r600.max_gs_threads = 16; |
| 1587 | rdev->config.r600.sx_max_export_size = 128; |
| 1588 | rdev->config.r600.sx_max_export_pos_size = 16; |
| 1589 | rdev->config.r600.sx_max_export_smx_size = 128; |
| 1590 | rdev->config.r600.sq_num_cf_insts = 2; |
| 1591 | break; |
| 1592 | default: |
| 1593 | break; |
| 1594 | } |
| 1595 | |
| 1596 | /* Initialize HDP */ |
| 1597 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| 1598 | WREG32((0x2c14 + j), 0x00000000); |
| 1599 | WREG32((0x2c18 + j), 0x00000000); |
| 1600 | WREG32((0x2c1c + j), 0x00000000); |
| 1601 | WREG32((0x2c20 + j), 0x00000000); |
| 1602 | WREG32((0x2c24 + j), 0x00000000); |
| 1603 | } |
| 1604 | |
| 1605 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
| 1606 | |
| 1607 | /* Setup tiling */ |
| 1608 | tiling_config = 0; |
| 1609 | ramcfg = RREG32(RAMCFG); |
| 1610 | switch (rdev->config.r600.max_tile_pipes) { |
| 1611 | case 1: |
| 1612 | tiling_config |= PIPE_TILING(0); |
| 1613 | break; |
| 1614 | case 2: |
| 1615 | tiling_config |= PIPE_TILING(1); |
| 1616 | break; |
| 1617 | case 4: |
| 1618 | tiling_config |= PIPE_TILING(2); |
| 1619 | break; |
| 1620 | case 8: |
| 1621 | tiling_config |= PIPE_TILING(3); |
| 1622 | break; |
| 1623 | default: |
| 1624 | break; |
| 1625 | } |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1626 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
Jerome Glisse | 961fb59 | 2010-02-10 22:30:05 +0000 | [diff] [blame] | 1627 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1628 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
Alex Deucher | 881fe6c | 2010-10-18 23:54:56 -0400 | [diff] [blame] | 1629 | tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1630 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1631 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
| 1632 | if (tmp > 3) { |
| 1633 | tiling_config |= ROW_TILING(3); |
| 1634 | tiling_config |= SAMPLE_SPLIT(3); |
| 1635 | } else { |
| 1636 | tiling_config |= ROW_TILING(tmp); |
| 1637 | tiling_config |= SAMPLE_SPLIT(tmp); |
| 1638 | } |
| 1639 | tiling_config |= BANK_SWAPS(1); |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1640 | |
| 1641 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1642 | tmp = R6XX_MAX_BACKENDS - |
| 1643 | r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); |
| 1644 | if (tmp < rdev->config.r600.max_backends) { |
| 1645 | rdev->config.r600.max_backends = tmp; |
| 1646 | } |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1647 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1648 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; |
| 1649 | tmp = R6XX_MAX_PIPES - |
| 1650 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); |
| 1651 | if (tmp < rdev->config.r600.max_pipes) { |
| 1652 | rdev->config.r600.max_pipes = tmp; |
| 1653 | } |
| 1654 | tmp = R6XX_MAX_SIMDS - |
| 1655 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); |
| 1656 | if (tmp < rdev->config.r600.max_simds) { |
| 1657 | rdev->config.r600.max_simds = tmp; |
| 1658 | } |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1659 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1660 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; |
| 1661 | tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
| 1662 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, |
| 1663 | R6XX_MAX_BACKENDS, disabled_rb_mask); |
| 1664 | tiling_config |= tmp << 16; |
| 1665 | rdev->config.r600.backend_map = tmp; |
| 1666 | |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1667 | rdev->config.r600.tile_config = tiling_config; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1668 | WREG32(GB_TILING_CONFIG, tiling_config); |
| 1669 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); |
| 1670 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1671 | WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1672 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1673 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1674 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
| 1675 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
| 1676 | |
| 1677 | /* Setup some CP states */ |
| 1678 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); |
| 1679 | WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); |
| 1680 | |
| 1681 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | |
| 1682 | SYNC_WALKER | SYNC_ALIGNER)); |
| 1683 | /* Setup various GPU states */ |
| 1684 | if (rdev->family == CHIP_RV670) |
| 1685 | WREG32(ARB_GDEC_RD_CNTL, 0x00000021); |
| 1686 | |
| 1687 | tmp = RREG32(SX_DEBUG_1); |
| 1688 | tmp |= SMX_EVENT_RELEASE; |
| 1689 | if ((rdev->family > CHIP_R600)) |
| 1690 | tmp |= ENABLE_NEW_SMX_ADDRESS; |
| 1691 | WREG32(SX_DEBUG_1, tmp); |
| 1692 | |
| 1693 | if (((rdev->family) == CHIP_R600) || |
| 1694 | ((rdev->family) == CHIP_RV630) || |
| 1695 | ((rdev->family) == CHIP_RV610) || |
| 1696 | ((rdev->family) == CHIP_RV620) || |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1697 | ((rdev->family) == CHIP_RS780) || |
| 1698 | ((rdev->family) == CHIP_RS880)) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1699 | WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
| 1700 | } else { |
| 1701 | WREG32(DB_DEBUG, 0); |
| 1702 | } |
| 1703 | WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | |
| 1704 | DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); |
| 1705 | |
| 1706 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| 1707 | WREG32(VGT_NUM_INSTANCES, 0); |
| 1708 | |
| 1709 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); |
| 1710 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); |
| 1711 | |
| 1712 | tmp = RREG32(SQ_MS_FIFO_SIZES); |
| 1713 | if (((rdev->family) == CHIP_RV610) || |
| 1714 | ((rdev->family) == CHIP_RV620) || |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1715 | ((rdev->family) == CHIP_RS780) || |
| 1716 | ((rdev->family) == CHIP_RS880)) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1717 | tmp = (CACHE_FIFO_SIZE(0xa) | |
| 1718 | FETCH_FIFO_HIWATER(0xa) | |
| 1719 | DONE_FIFO_HIWATER(0xe0) | |
| 1720 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
| 1721 | } else if (((rdev->family) == CHIP_R600) || |
| 1722 | ((rdev->family) == CHIP_RV630)) { |
| 1723 | tmp &= ~DONE_FIFO_HIWATER(0xff); |
| 1724 | tmp |= DONE_FIFO_HIWATER(0x4); |
| 1725 | } |
| 1726 | WREG32(SQ_MS_FIFO_SIZES, tmp); |
| 1727 | |
| 1728 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
| 1729 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
| 1730 | */ |
| 1731 | sq_config = RREG32(SQ_CONFIG); |
| 1732 | sq_config &= ~(PS_PRIO(3) | |
| 1733 | VS_PRIO(3) | |
| 1734 | GS_PRIO(3) | |
| 1735 | ES_PRIO(3)); |
| 1736 | sq_config |= (DX9_CONSTS | |
| 1737 | VC_ENABLE | |
| 1738 | PS_PRIO(0) | |
| 1739 | VS_PRIO(1) | |
| 1740 | GS_PRIO(2) | |
| 1741 | ES_PRIO(3)); |
| 1742 | |
| 1743 | if ((rdev->family) == CHIP_R600) { |
| 1744 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | |
| 1745 | NUM_VS_GPRS(124) | |
| 1746 | NUM_CLAUSE_TEMP_GPRS(4)); |
| 1747 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | |
| 1748 | NUM_ES_GPRS(0)); |
| 1749 | sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | |
| 1750 | NUM_VS_THREADS(48) | |
| 1751 | NUM_GS_THREADS(4) | |
| 1752 | NUM_ES_THREADS(4)); |
| 1753 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | |
| 1754 | NUM_VS_STACK_ENTRIES(128)); |
| 1755 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | |
| 1756 | NUM_ES_STACK_ENTRIES(0)); |
| 1757 | } else if (((rdev->family) == CHIP_RV610) || |
| 1758 | ((rdev->family) == CHIP_RV620) || |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1759 | ((rdev->family) == CHIP_RS780) || |
| 1760 | ((rdev->family) == CHIP_RS880)) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1761 | /* no vertex cache */ |
| 1762 | sq_config &= ~VC_ENABLE; |
| 1763 | |
| 1764 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | |
| 1765 | NUM_VS_GPRS(44) | |
| 1766 | NUM_CLAUSE_TEMP_GPRS(2)); |
| 1767 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | |
| 1768 | NUM_ES_GPRS(17)); |
| 1769 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | |
| 1770 | NUM_VS_THREADS(78) | |
| 1771 | NUM_GS_THREADS(4) | |
| 1772 | NUM_ES_THREADS(31)); |
| 1773 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | |
| 1774 | NUM_VS_STACK_ENTRIES(40)); |
| 1775 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | |
| 1776 | NUM_ES_STACK_ENTRIES(16)); |
| 1777 | } else if (((rdev->family) == CHIP_RV630) || |
| 1778 | ((rdev->family) == CHIP_RV635)) { |
| 1779 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | |
| 1780 | NUM_VS_GPRS(44) | |
| 1781 | NUM_CLAUSE_TEMP_GPRS(2)); |
| 1782 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | |
| 1783 | NUM_ES_GPRS(18)); |
| 1784 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | |
| 1785 | NUM_VS_THREADS(78) | |
| 1786 | NUM_GS_THREADS(4) | |
| 1787 | NUM_ES_THREADS(31)); |
| 1788 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | |
| 1789 | NUM_VS_STACK_ENTRIES(40)); |
| 1790 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | |
| 1791 | NUM_ES_STACK_ENTRIES(16)); |
| 1792 | } else if ((rdev->family) == CHIP_RV670) { |
| 1793 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | |
| 1794 | NUM_VS_GPRS(44) | |
| 1795 | NUM_CLAUSE_TEMP_GPRS(2)); |
| 1796 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | |
| 1797 | NUM_ES_GPRS(17)); |
| 1798 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | |
| 1799 | NUM_VS_THREADS(78) | |
| 1800 | NUM_GS_THREADS(4) | |
| 1801 | NUM_ES_THREADS(31)); |
| 1802 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | |
| 1803 | NUM_VS_STACK_ENTRIES(64)); |
| 1804 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | |
| 1805 | NUM_ES_STACK_ENTRIES(64)); |
| 1806 | } |
| 1807 | |
| 1808 | WREG32(SQ_CONFIG, sq_config); |
| 1809 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); |
| 1810 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); |
| 1811 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
| 1812 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); |
| 1813 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); |
| 1814 | |
| 1815 | if (((rdev->family) == CHIP_RV610) || |
| 1816 | ((rdev->family) == CHIP_RV620) || |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1817 | ((rdev->family) == CHIP_RS780) || |
| 1818 | ((rdev->family) == CHIP_RS880)) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1819 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
| 1820 | } else { |
| 1821 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); |
| 1822 | } |
| 1823 | |
| 1824 | /* More default values. 2D/3D driver should adjust as needed */ |
| 1825 | WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | |
| 1826 | S1_X(0x4) | S1_Y(0xc))); |
| 1827 | WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | |
| 1828 | S1_X(0x2) | S1_Y(0x2) | |
| 1829 | S2_X(0xa) | S2_Y(0x6) | |
| 1830 | S3_X(0x6) | S3_Y(0xa))); |
| 1831 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | |
| 1832 | S1_X(0x4) | S1_Y(0xc) | |
| 1833 | S2_X(0x1) | S2_Y(0x6) | |
| 1834 | S3_X(0xa) | S3_Y(0xe))); |
| 1835 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | |
| 1836 | S5_X(0x0) | S5_Y(0x0) | |
| 1837 | S6_X(0xb) | S6_Y(0x4) | |
| 1838 | S7_X(0x7) | S7_Y(0x8))); |
| 1839 | |
| 1840 | WREG32(VGT_STRMOUT_EN, 0); |
| 1841 | tmp = rdev->config.r600.max_pipes * 16; |
| 1842 | switch (rdev->family) { |
| 1843 | case CHIP_RV610: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1844 | case CHIP_RV620: |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1845 | case CHIP_RS780: |
| 1846 | case CHIP_RS880: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1847 | tmp += 32; |
| 1848 | break; |
| 1849 | case CHIP_RV670: |
| 1850 | tmp += 128; |
| 1851 | break; |
| 1852 | default: |
| 1853 | break; |
| 1854 | } |
| 1855 | if (tmp > 256) { |
| 1856 | tmp = 256; |
| 1857 | } |
| 1858 | WREG32(VGT_ES_PER_GS, 128); |
| 1859 | WREG32(VGT_GS_PER_ES, tmp); |
| 1860 | WREG32(VGT_GS_PER_VS, 2); |
| 1861 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
| 1862 | |
| 1863 | /* more default values. 2D/3D driver should adjust as needed */ |
| 1864 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
| 1865 | WREG32(VGT_STRMOUT_EN, 0); |
| 1866 | WREG32(SX_MISC, 0); |
| 1867 | WREG32(PA_SC_MODE_CNTL, 0); |
| 1868 | WREG32(PA_SC_AA_CONFIG, 0); |
| 1869 | WREG32(PA_SC_LINE_STIPPLE, 0); |
| 1870 | WREG32(SPI_INPUT_Z, 0); |
| 1871 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
| 1872 | WREG32(CB_COLOR7_FRAG, 0); |
| 1873 | |
| 1874 | /* Clear render buffer base addresses */ |
| 1875 | WREG32(CB_COLOR0_BASE, 0); |
| 1876 | WREG32(CB_COLOR1_BASE, 0); |
| 1877 | WREG32(CB_COLOR2_BASE, 0); |
| 1878 | WREG32(CB_COLOR3_BASE, 0); |
| 1879 | WREG32(CB_COLOR4_BASE, 0); |
| 1880 | WREG32(CB_COLOR5_BASE, 0); |
| 1881 | WREG32(CB_COLOR6_BASE, 0); |
| 1882 | WREG32(CB_COLOR7_BASE, 0); |
| 1883 | WREG32(CB_COLOR7_FRAG, 0); |
| 1884 | |
| 1885 | switch (rdev->family) { |
| 1886 | case CHIP_RV610: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1887 | case CHIP_RV620: |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1888 | case CHIP_RS780: |
| 1889 | case CHIP_RS880: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1890 | tmp = TC_L2_SIZE(8); |
| 1891 | break; |
| 1892 | case CHIP_RV630: |
| 1893 | case CHIP_RV635: |
| 1894 | tmp = TC_L2_SIZE(4); |
| 1895 | break; |
| 1896 | case CHIP_R600: |
| 1897 | tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; |
| 1898 | break; |
| 1899 | default: |
| 1900 | tmp = TC_L2_SIZE(0); |
| 1901 | break; |
| 1902 | } |
| 1903 | WREG32(TC_CNTL, tmp); |
| 1904 | |
| 1905 | tmp = RREG32(HDP_HOST_PATH_CNTL); |
| 1906 | WREG32(HDP_HOST_PATH_CNTL, tmp); |
| 1907 | |
| 1908 | tmp = RREG32(ARB_POP); |
| 1909 | tmp |= ENABLE_TC128; |
| 1910 | WREG32(ARB_POP, tmp); |
| 1911 | |
| 1912 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| 1913 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
| 1914 | NUM_CLIP_SEQ(3))); |
| 1915 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); |
Alex Deucher | b866d13 | 2012-06-14 22:06:36 +0200 | [diff] [blame] | 1916 | WREG32(VC_ENHANCE, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1917 | } |
| 1918 | |
| 1919 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1920 | /* |
| 1921 | * Indirect registers accessor |
| 1922 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1923 | u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1924 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1925 | u32 r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1926 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1927 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
| 1928 | (void)RREG32(PCIE_PORT_INDEX); |
| 1929 | r = RREG32(PCIE_PORT_DATA); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1930 | return r; |
| 1931 | } |
| 1932 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1933 | void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1934 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1935 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
| 1936 | (void)RREG32(PCIE_PORT_INDEX); |
| 1937 | WREG32(PCIE_PORT_DATA, (v)); |
| 1938 | (void)RREG32(PCIE_PORT_DATA); |
| 1939 | } |
| 1940 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1941 | /* |
| 1942 | * CP & Ring |
| 1943 | */ |
| 1944 | void r600_cp_stop(struct radeon_device *rdev) |
| 1945 | { |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 1946 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1947 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1948 | WREG32(SCRATCH_UMSK, 0); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1949 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1950 | } |
| 1951 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1952 | int r600_init_microcode(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1953 | { |
| 1954 | struct platform_device *pdev; |
| 1955 | const char *chip_name; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1956 | const char *rlc_chip_name; |
| 1957 | size_t pfp_req_size, me_req_size, rlc_req_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1958 | char fw_name[30]; |
| 1959 | int err; |
| 1960 | |
| 1961 | DRM_DEBUG("\n"); |
| 1962 | |
| 1963 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
| 1964 | err = IS_ERR(pdev); |
| 1965 | if (err) { |
| 1966 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
| 1967 | return -EINVAL; |
| 1968 | } |
| 1969 | |
| 1970 | switch (rdev->family) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1971 | case CHIP_R600: |
| 1972 | chip_name = "R600"; |
| 1973 | rlc_chip_name = "R600"; |
| 1974 | break; |
| 1975 | case CHIP_RV610: |
| 1976 | chip_name = "RV610"; |
| 1977 | rlc_chip_name = "R600"; |
| 1978 | break; |
| 1979 | case CHIP_RV630: |
| 1980 | chip_name = "RV630"; |
| 1981 | rlc_chip_name = "R600"; |
| 1982 | break; |
| 1983 | case CHIP_RV620: |
| 1984 | chip_name = "RV620"; |
| 1985 | rlc_chip_name = "R600"; |
| 1986 | break; |
| 1987 | case CHIP_RV635: |
| 1988 | chip_name = "RV635"; |
| 1989 | rlc_chip_name = "R600"; |
| 1990 | break; |
| 1991 | case CHIP_RV670: |
| 1992 | chip_name = "RV670"; |
| 1993 | rlc_chip_name = "R600"; |
| 1994 | break; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1995 | case CHIP_RS780: |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1996 | case CHIP_RS880: |
| 1997 | chip_name = "RS780"; |
| 1998 | rlc_chip_name = "R600"; |
| 1999 | break; |
| 2000 | case CHIP_RV770: |
| 2001 | chip_name = "RV770"; |
| 2002 | rlc_chip_name = "R700"; |
| 2003 | break; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2004 | case CHIP_RV730: |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2005 | case CHIP_RV740: |
| 2006 | chip_name = "RV730"; |
| 2007 | rlc_chip_name = "R700"; |
| 2008 | break; |
| 2009 | case CHIP_RV710: |
| 2010 | chip_name = "RV710"; |
| 2011 | rlc_chip_name = "R700"; |
| 2012 | break; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2013 | case CHIP_CEDAR: |
| 2014 | chip_name = "CEDAR"; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2015 | rlc_chip_name = "CEDAR"; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2016 | break; |
| 2017 | case CHIP_REDWOOD: |
| 2018 | chip_name = "REDWOOD"; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2019 | rlc_chip_name = "REDWOOD"; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2020 | break; |
| 2021 | case CHIP_JUNIPER: |
| 2022 | chip_name = "JUNIPER"; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2023 | rlc_chip_name = "JUNIPER"; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2024 | break; |
| 2025 | case CHIP_CYPRESS: |
| 2026 | case CHIP_HEMLOCK: |
| 2027 | chip_name = "CYPRESS"; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2028 | rlc_chip_name = "CYPRESS"; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2029 | break; |
Alex Deucher | 439bd6c | 2010-11-22 17:56:31 -0500 | [diff] [blame] | 2030 | case CHIP_PALM: |
| 2031 | chip_name = "PALM"; |
| 2032 | rlc_chip_name = "SUMO"; |
| 2033 | break; |
Alex Deucher | d5c5a72 | 2011-05-31 15:42:48 -0400 | [diff] [blame] | 2034 | case CHIP_SUMO: |
| 2035 | chip_name = "SUMO"; |
| 2036 | rlc_chip_name = "SUMO"; |
| 2037 | break; |
| 2038 | case CHIP_SUMO2: |
| 2039 | chip_name = "SUMO2"; |
| 2040 | rlc_chip_name = "SUMO"; |
| 2041 | break; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2042 | default: BUG(); |
| 2043 | } |
| 2044 | |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2045 | if (rdev->family >= CHIP_CEDAR) { |
| 2046 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
| 2047 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2048 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2049 | } else if (rdev->family >= CHIP_RV770) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2050 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; |
| 2051 | me_req_size = R700_PM4_UCODE_SIZE * 4; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2052 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2053 | } else { |
| 2054 | pfp_req_size = PFP_UCODE_SIZE * 4; |
| 2055 | me_req_size = PM4_UCODE_SIZE * 12; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2056 | rlc_req_size = RLC_UCODE_SIZE * 4; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2057 | } |
| 2058 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2059 | DRM_INFO("Loading %s Microcode\n", chip_name); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2060 | |
| 2061 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
| 2062 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); |
| 2063 | if (err) |
| 2064 | goto out; |
| 2065 | if (rdev->pfp_fw->size != pfp_req_size) { |
| 2066 | printk(KERN_ERR |
| 2067 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", |
| 2068 | rdev->pfp_fw->size, fw_name); |
| 2069 | err = -EINVAL; |
| 2070 | goto out; |
| 2071 | } |
| 2072 | |
| 2073 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
| 2074 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
| 2075 | if (err) |
| 2076 | goto out; |
| 2077 | if (rdev->me_fw->size != me_req_size) { |
| 2078 | printk(KERN_ERR |
| 2079 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", |
| 2080 | rdev->me_fw->size, fw_name); |
| 2081 | err = -EINVAL; |
| 2082 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2083 | |
| 2084 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); |
| 2085 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); |
| 2086 | if (err) |
| 2087 | goto out; |
| 2088 | if (rdev->rlc_fw->size != rlc_req_size) { |
| 2089 | printk(KERN_ERR |
| 2090 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", |
| 2091 | rdev->rlc_fw->size, fw_name); |
| 2092 | err = -EINVAL; |
| 2093 | } |
| 2094 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2095 | out: |
| 2096 | platform_device_unregister(pdev); |
| 2097 | |
| 2098 | if (err) { |
| 2099 | if (err != -EINVAL) |
| 2100 | printk(KERN_ERR |
| 2101 | "r600_cp: Failed to load firmware \"%s\"\n", |
| 2102 | fw_name); |
| 2103 | release_firmware(rdev->pfp_fw); |
| 2104 | rdev->pfp_fw = NULL; |
| 2105 | release_firmware(rdev->me_fw); |
| 2106 | rdev->me_fw = NULL; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2107 | release_firmware(rdev->rlc_fw); |
| 2108 | rdev->rlc_fw = NULL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2109 | } |
| 2110 | return err; |
| 2111 | } |
| 2112 | |
| 2113 | static int r600_cp_load_microcode(struct radeon_device *rdev) |
| 2114 | { |
| 2115 | const __be32 *fw_data; |
| 2116 | int i; |
| 2117 | |
| 2118 | if (!rdev->me_fw || !rdev->pfp_fw) |
| 2119 | return -EINVAL; |
| 2120 | |
| 2121 | r600_cp_stop(rdev); |
| 2122 | |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 2123 | WREG32(CP_RB_CNTL, |
| 2124 | #ifdef __BIG_ENDIAN |
| 2125 | BUF_SWAP_32BIT | |
| 2126 | #endif |
| 2127 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2128 | |
| 2129 | /* Reset cp */ |
| 2130 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
| 2131 | RREG32(GRBM_SOFT_RESET); |
| 2132 | mdelay(15); |
| 2133 | WREG32(GRBM_SOFT_RESET, 0); |
| 2134 | |
| 2135 | WREG32(CP_ME_RAM_WADDR, 0); |
| 2136 | |
| 2137 | fw_data = (const __be32 *)rdev->me_fw->data; |
| 2138 | WREG32(CP_ME_RAM_WADDR, 0); |
| 2139 | for (i = 0; i < PM4_UCODE_SIZE * 3; i++) |
| 2140 | WREG32(CP_ME_RAM_DATA, |
| 2141 | be32_to_cpup(fw_data++)); |
| 2142 | |
| 2143 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
| 2144 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 2145 | for (i = 0; i < PFP_UCODE_SIZE; i++) |
| 2146 | WREG32(CP_PFP_UCODE_DATA, |
| 2147 | be32_to_cpup(fw_data++)); |
| 2148 | |
| 2149 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 2150 | WREG32(CP_ME_RAM_WADDR, 0); |
| 2151 | WREG32(CP_ME_RAM_RADDR, 0); |
| 2152 | return 0; |
| 2153 | } |
| 2154 | |
| 2155 | int r600_cp_start(struct radeon_device *rdev) |
| 2156 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2157 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2158 | int r; |
| 2159 | uint32_t cp_me; |
| 2160 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2161 | r = radeon_ring_lock(rdev, ring, 7); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2162 | if (r) { |
| 2163 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
| 2164 | return r; |
| 2165 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2166 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
| 2167 | radeon_ring_write(ring, 0x1); |
Alex Deucher | 7e7b41d | 2010-09-02 21:32:32 -0400 | [diff] [blame] | 2168 | if (rdev->family >= CHIP_RV770) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2169 | radeon_ring_write(ring, 0x0); |
| 2170 | radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2171 | } else { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2172 | radeon_ring_write(ring, 0x3); |
| 2173 | radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2174 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2175 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
| 2176 | radeon_ring_write(ring, 0); |
| 2177 | radeon_ring_write(ring, 0); |
| 2178 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2179 | |
| 2180 | cp_me = 0xff; |
| 2181 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
| 2182 | return 0; |
| 2183 | } |
| 2184 | |
| 2185 | int r600_cp_resume(struct radeon_device *rdev) |
| 2186 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2187 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2188 | u32 tmp; |
| 2189 | u32 rb_bufsz; |
| 2190 | int r; |
| 2191 | |
| 2192 | /* Reset cp */ |
| 2193 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
| 2194 | RREG32(GRBM_SOFT_RESET); |
| 2195 | mdelay(15); |
| 2196 | WREG32(GRBM_SOFT_RESET, 0); |
| 2197 | |
| 2198 | /* Set ring buffer size */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2199 | rb_bufsz = drm_order(ring->ring_size / 8); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2200 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2201 | #ifdef __BIG_ENDIAN |
Alex Deucher | d6f2893 | 2009-11-02 16:01:27 -0500 | [diff] [blame] | 2202 | tmp |= BUF_SWAP_32BIT; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2203 | #endif |
Alex Deucher | d6f2893 | 2009-11-02 16:01:27 -0500 | [diff] [blame] | 2204 | WREG32(CP_RB_CNTL, tmp); |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2205 | WREG32(CP_SEM_WAIT_TIMER, 0x0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2206 | |
| 2207 | /* Set the write pointer delay */ |
| 2208 | WREG32(CP_RB_WPTR_DELAY, 0); |
| 2209 | |
| 2210 | /* Initialize the ring buffer's read and write pointers */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2211 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
| 2212 | WREG32(CP_RB_RPTR_WR, 0); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2213 | ring->wptr = 0; |
| 2214 | WREG32(CP_RB_WPTR, ring->wptr); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2215 | |
| 2216 | /* set the wb address whether it's enabled or not */ |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 2217 | WREG32(CP_RB_RPTR_ADDR, |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 2218 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2219 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
| 2220 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
| 2221 | |
| 2222 | if (rdev->wb.enabled) |
| 2223 | WREG32(SCRATCH_UMSK, 0xff); |
| 2224 | else { |
| 2225 | tmp |= RB_NO_UPDATE; |
| 2226 | WREG32(SCRATCH_UMSK, 0); |
| 2227 | } |
| 2228 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2229 | mdelay(1); |
| 2230 | WREG32(CP_RB_CNTL, tmp); |
| 2231 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2232 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2233 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
| 2234 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2235 | ring->rptr = RREG32(CP_RB_RPTR); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2236 | |
| 2237 | r600_cp_start(rdev); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2238 | ring->ready = true; |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 2239 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2240 | if (r) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2241 | ring->ready = false; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2242 | return r; |
| 2243 | } |
| 2244 | return 0; |
| 2245 | } |
| 2246 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2247 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2248 | { |
| 2249 | u32 rb_bufsz; |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 2250 | int r; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2251 | |
| 2252 | /* Align ring size */ |
| 2253 | rb_bufsz = drm_order(ring_size / 8); |
| 2254 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2255 | ring->ring_size = ring_size; |
| 2256 | ring->align_mask = 16 - 1; |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 2257 | |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 2258 | if (radeon_ring_supports_scratch_reg(rdev, ring)) { |
| 2259 | r = radeon_scratch_get(rdev, &ring->rptr_save_reg); |
| 2260 | if (r) { |
| 2261 | DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); |
| 2262 | ring->rptr_save_reg = 0; |
| 2263 | } |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 2264 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2265 | } |
| 2266 | |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2267 | void r600_cp_fini(struct radeon_device *rdev) |
| 2268 | { |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 2269 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2270 | r600_cp_stop(rdev); |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 2271 | radeon_ring_fini(rdev, ring); |
| 2272 | radeon_scratch_free(rdev, ring->rptr_save_reg); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2273 | } |
| 2274 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2275 | /* |
| 2276 | * DMA |
| 2277 | * Starting with R600, the GPU has an asynchronous |
| 2278 | * DMA engine. The programming model is very similar |
| 2279 | * to the 3D engine (ring buffer, IBs, etc.), but the |
| 2280 | * DMA controller has it's own packet format that is |
| 2281 | * different form the PM4 format used by the 3D engine. |
| 2282 | * It supports copying data, writing embedded data, |
| 2283 | * solid fills, and a number of other things. It also |
| 2284 | * has support for tiling/detiling of buffers. |
| 2285 | */ |
| 2286 | /** |
| 2287 | * r600_dma_stop - stop the async dma engine |
| 2288 | * |
| 2289 | * @rdev: radeon_device pointer |
| 2290 | * |
| 2291 | * Stop the async dma engine (r6xx-evergreen). |
| 2292 | */ |
| 2293 | void r600_dma_stop(struct radeon_device *rdev) |
| 2294 | { |
| 2295 | u32 rb_cntl = RREG32(DMA_RB_CNTL); |
| 2296 | |
| 2297 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
| 2298 | |
| 2299 | rb_cntl &= ~DMA_RB_ENABLE; |
| 2300 | WREG32(DMA_RB_CNTL, rb_cntl); |
| 2301 | |
| 2302 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; |
| 2303 | } |
| 2304 | |
| 2305 | /** |
| 2306 | * r600_dma_resume - setup and start the async dma engine |
| 2307 | * |
| 2308 | * @rdev: radeon_device pointer |
| 2309 | * |
| 2310 | * Set up the DMA ring buffer and enable it. (r6xx-evergreen). |
| 2311 | * Returns 0 for success, error for failure. |
| 2312 | */ |
| 2313 | int r600_dma_resume(struct radeon_device *rdev) |
| 2314 | { |
| 2315 | struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
| 2316 | u32 rb_cntl, dma_cntl; |
| 2317 | u32 rb_bufsz; |
| 2318 | int r; |
| 2319 | |
| 2320 | /* Reset dma */ |
| 2321 | if (rdev->family >= CHIP_RV770) |
| 2322 | WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); |
| 2323 | else |
| 2324 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); |
| 2325 | RREG32(SRBM_SOFT_RESET); |
| 2326 | udelay(50); |
| 2327 | WREG32(SRBM_SOFT_RESET, 0); |
| 2328 | |
| 2329 | WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); |
| 2330 | WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); |
| 2331 | |
| 2332 | /* Set ring buffer size in dwords */ |
| 2333 | rb_bufsz = drm_order(ring->ring_size / 4); |
| 2334 | rb_cntl = rb_bufsz << 1; |
| 2335 | #ifdef __BIG_ENDIAN |
| 2336 | rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; |
| 2337 | #endif |
| 2338 | WREG32(DMA_RB_CNTL, rb_cntl); |
| 2339 | |
| 2340 | /* Initialize the ring buffer's read and write pointers */ |
| 2341 | WREG32(DMA_RB_RPTR, 0); |
| 2342 | WREG32(DMA_RB_WPTR, 0); |
| 2343 | |
| 2344 | /* set the wb address whether it's enabled or not */ |
| 2345 | WREG32(DMA_RB_RPTR_ADDR_HI, |
| 2346 | upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); |
| 2347 | WREG32(DMA_RB_RPTR_ADDR_LO, |
| 2348 | ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); |
| 2349 | |
| 2350 | if (rdev->wb.enabled) |
| 2351 | rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; |
| 2352 | |
| 2353 | WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); |
| 2354 | |
| 2355 | /* enable DMA IBs */ |
| 2356 | WREG32(DMA_IB_CNTL, DMA_IB_ENABLE); |
| 2357 | |
| 2358 | dma_cntl = RREG32(DMA_CNTL); |
| 2359 | dma_cntl &= ~CTXEMPTY_INT_ENABLE; |
| 2360 | WREG32(DMA_CNTL, dma_cntl); |
| 2361 | |
| 2362 | if (rdev->family >= CHIP_RV770) |
| 2363 | WREG32(DMA_MODE, 1); |
| 2364 | |
| 2365 | ring->wptr = 0; |
| 2366 | WREG32(DMA_RB_WPTR, ring->wptr << 2); |
| 2367 | |
| 2368 | ring->rptr = RREG32(DMA_RB_RPTR) >> 2; |
| 2369 | |
| 2370 | WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); |
| 2371 | |
| 2372 | ring->ready = true; |
| 2373 | |
| 2374 | r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); |
| 2375 | if (r) { |
| 2376 | ring->ready = false; |
| 2377 | return r; |
| 2378 | } |
| 2379 | |
| 2380 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
| 2381 | |
| 2382 | return 0; |
| 2383 | } |
| 2384 | |
| 2385 | /** |
| 2386 | * r600_dma_fini - tear down the async dma engine |
| 2387 | * |
| 2388 | * @rdev: radeon_device pointer |
| 2389 | * |
| 2390 | * Stop the async dma engine and free the ring (r6xx-evergreen). |
| 2391 | */ |
| 2392 | void r600_dma_fini(struct radeon_device *rdev) |
| 2393 | { |
| 2394 | r600_dma_stop(rdev); |
| 2395 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); |
| 2396 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2397 | |
| 2398 | /* |
| 2399 | * GPU scratch registers helpers function. |
| 2400 | */ |
| 2401 | void r600_scratch_init(struct radeon_device *rdev) |
| 2402 | { |
| 2403 | int i; |
| 2404 | |
| 2405 | rdev->scratch.num_reg = 7; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2406 | rdev->scratch.reg_base = SCRATCH_REG0; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2407 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 2408 | rdev->scratch.free[i] = true; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2409 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2410 | } |
| 2411 | } |
| 2412 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2413 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2414 | { |
| 2415 | uint32_t scratch; |
| 2416 | uint32_t tmp = 0; |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 2417 | unsigned i; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2418 | int r; |
| 2419 | |
| 2420 | r = radeon_scratch_get(rdev, &scratch); |
| 2421 | if (r) { |
| 2422 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
| 2423 | return r; |
| 2424 | } |
| 2425 | WREG32(scratch, 0xCAFEDEAD); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2426 | r = radeon_ring_lock(rdev, ring, 3); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2427 | if (r) { |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 2428 | DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2429 | radeon_scratch_free(rdev, scratch); |
| 2430 | return r; |
| 2431 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2432 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 2433 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
| 2434 | radeon_ring_write(ring, 0xDEADBEEF); |
| 2435 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2436 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2437 | tmp = RREG32(scratch); |
| 2438 | if (tmp == 0xDEADBEEF) |
| 2439 | break; |
| 2440 | DRM_UDELAY(1); |
| 2441 | } |
| 2442 | if (i < rdev->usec_timeout) { |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 2443 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2444 | } else { |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 2445 | DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 2446 | ring->idx, scratch, tmp); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2447 | r = -EINVAL; |
| 2448 | } |
| 2449 | radeon_scratch_free(rdev, scratch); |
| 2450 | return r; |
| 2451 | } |
| 2452 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2453 | /** |
| 2454 | * r600_dma_ring_test - simple async dma engine test |
| 2455 | * |
| 2456 | * @rdev: radeon_device pointer |
| 2457 | * @ring: radeon_ring structure holding ring information |
| 2458 | * |
| 2459 | * Test the DMA engine by writing using it to write an |
| 2460 | * value to memory. (r6xx-SI). |
| 2461 | * Returns 0 for success, error for failure. |
| 2462 | */ |
| 2463 | int r600_dma_ring_test(struct radeon_device *rdev, |
| 2464 | struct radeon_ring *ring) |
| 2465 | { |
| 2466 | unsigned i; |
| 2467 | int r; |
| 2468 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
| 2469 | u32 tmp; |
| 2470 | |
| 2471 | if (!ptr) { |
| 2472 | DRM_ERROR("invalid vram scratch pointer\n"); |
| 2473 | return -EINVAL; |
| 2474 | } |
| 2475 | |
| 2476 | tmp = 0xCAFEDEAD; |
| 2477 | writel(tmp, ptr); |
| 2478 | |
| 2479 | r = radeon_ring_lock(rdev, ring, 4); |
| 2480 | if (r) { |
| 2481 | DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); |
| 2482 | return r; |
| 2483 | } |
| 2484 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); |
| 2485 | radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); |
| 2486 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); |
| 2487 | radeon_ring_write(ring, 0xDEADBEEF); |
| 2488 | radeon_ring_unlock_commit(rdev, ring); |
| 2489 | |
| 2490 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2491 | tmp = readl(ptr); |
| 2492 | if (tmp == 0xDEADBEEF) |
| 2493 | break; |
| 2494 | DRM_UDELAY(1); |
| 2495 | } |
| 2496 | |
| 2497 | if (i < rdev->usec_timeout) { |
| 2498 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
| 2499 | } else { |
| 2500 | DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", |
| 2501 | ring->idx, tmp); |
| 2502 | r = -EINVAL; |
| 2503 | } |
| 2504 | return r; |
| 2505 | } |
| 2506 | |
| 2507 | /* |
| 2508 | * CP fences/semaphores |
| 2509 | */ |
| 2510 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2511 | void r600_fence_ring_emit(struct radeon_device *rdev, |
| 2512 | struct radeon_fence *fence) |
| 2513 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2514 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 2515 | |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2516 | if (rdev->wb.use_event) { |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 2517 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
Jerome Glisse | 77b1bad | 2011-10-26 11:41:22 -0400 | [diff] [blame] | 2518 | /* flush read cache over gart */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2519 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 2520 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | |
| 2521 | PACKET3_VC_ACTION_ENA | |
| 2522 | PACKET3_SH_ACTION_ENA); |
| 2523 | radeon_ring_write(ring, 0xFFFFFFFF); |
| 2524 | radeon_ring_write(ring, 0); |
| 2525 | radeon_ring_write(ring, 10); /* poll interval */ |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2526 | /* EVENT_WRITE_EOP - flush caches, send int */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2527 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
| 2528 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); |
| 2529 | radeon_ring_write(ring, addr & 0xffffffff); |
| 2530 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); |
| 2531 | radeon_ring_write(ring, fence->seq); |
| 2532 | radeon_ring_write(ring, 0); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2533 | } else { |
Jerome Glisse | 77b1bad | 2011-10-26 11:41:22 -0400 | [diff] [blame] | 2534 | /* flush read cache over gart */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2535 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 2536 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | |
| 2537 | PACKET3_VC_ACTION_ENA | |
| 2538 | PACKET3_SH_ACTION_ENA); |
| 2539 | radeon_ring_write(ring, 0xFFFFFFFF); |
| 2540 | radeon_ring_write(ring, 0); |
| 2541 | radeon_ring_write(ring, 10); /* poll interval */ |
| 2542 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); |
| 2543 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2544 | /* wait for 3D idle clean */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2545 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 2546 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 2547 | radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2548 | /* Emit fence sequence & fire IRQ */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2549 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 2550 | radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
| 2551 | radeon_ring_write(ring, fence->seq); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2552 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2553 | radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); |
| 2554 | radeon_ring_write(ring, RB_INT_STAT); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2555 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2556 | } |
| 2557 | |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2558 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2559 | struct radeon_ring *ring, |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2560 | struct radeon_semaphore *semaphore, |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 2561 | bool emit_wait) |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2562 | { |
| 2563 | uint64_t addr = semaphore->gpu_addr; |
| 2564 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; |
| 2565 | |
Christian König | 0be7043 | 2012-03-07 11:28:57 +0100 | [diff] [blame] | 2566 | if (rdev->family < CHIP_CAYMAN) |
| 2567 | sel |= PACKET3_SEM_WAIT_ON_SIGNAL; |
| 2568 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2569 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); |
| 2570 | radeon_ring_write(ring, addr & 0xffffffff); |
| 2571 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2572 | } |
| 2573 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2574 | /* |
| 2575 | * DMA fences/semaphores |
| 2576 | */ |
| 2577 | |
| 2578 | /** |
| 2579 | * r600_dma_fence_ring_emit - emit a fence on the DMA ring |
| 2580 | * |
| 2581 | * @rdev: radeon_device pointer |
| 2582 | * @fence: radeon fence object |
| 2583 | * |
| 2584 | * Add a DMA fence packet to the ring to write |
| 2585 | * the fence seq number and DMA trap packet to generate |
| 2586 | * an interrupt if needed (r6xx-r7xx). |
| 2587 | */ |
| 2588 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
| 2589 | struct radeon_fence *fence) |
| 2590 | { |
| 2591 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
| 2592 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
Jerome Glisse | 86a1881 | 2012-12-12 16:43:15 -0500 | [diff] [blame] | 2593 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2594 | /* write the fence */ |
| 2595 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); |
| 2596 | radeon_ring_write(ring, addr & 0xfffffffc); |
| 2597 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); |
Jerome Glisse | 86a1881 | 2012-12-12 16:43:15 -0500 | [diff] [blame] | 2598 | radeon_ring_write(ring, lower_32_bits(fence->seq)); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2599 | /* generate an interrupt */ |
| 2600 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); |
| 2601 | } |
| 2602 | |
| 2603 | /** |
| 2604 | * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring |
| 2605 | * |
| 2606 | * @rdev: radeon_device pointer |
| 2607 | * @ring: radeon_ring structure holding ring information |
| 2608 | * @semaphore: radeon semaphore object |
| 2609 | * @emit_wait: wait or signal semaphore |
| 2610 | * |
| 2611 | * Add a DMA semaphore packet to the ring wait on or signal |
| 2612 | * other rings (r6xx-SI). |
| 2613 | */ |
| 2614 | void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, |
| 2615 | struct radeon_ring *ring, |
| 2616 | struct radeon_semaphore *semaphore, |
| 2617 | bool emit_wait) |
| 2618 | { |
| 2619 | u64 addr = semaphore->gpu_addr; |
| 2620 | u32 s = emit_wait ? 0 : 1; |
| 2621 | |
| 2622 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); |
| 2623 | radeon_ring_write(ring, addr & 0xfffffffc); |
| 2624 | radeon_ring_write(ring, upper_32_bits(addr) & 0xff); |
| 2625 | } |
| 2626 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2627 | int r600_copy_blit(struct radeon_device *rdev, |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 2628 | uint64_t src_offset, |
| 2629 | uint64_t dst_offset, |
| 2630 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 2631 | struct radeon_fence **fence) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2632 | { |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 2633 | struct radeon_semaphore *sem = NULL; |
Christian König | f237750 | 2012-05-09 15:35:01 +0200 | [diff] [blame] | 2634 | struct radeon_sa_bo *vb = NULL; |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 2635 | int r; |
| 2636 | |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 2637 | r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 2638 | if (r) { |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 2639 | return r; |
| 2640 | } |
Christian König | f237750 | 2012-05-09 15:35:01 +0200 | [diff] [blame] | 2641 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 2642 | r600_blit_done_copy(rdev, fence, vb, sem); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2643 | return 0; |
| 2644 | } |
| 2645 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2646 | /** |
| 2647 | * r600_copy_dma - copy pages using the DMA engine |
| 2648 | * |
| 2649 | * @rdev: radeon_device pointer |
| 2650 | * @src_offset: src GPU address |
| 2651 | * @dst_offset: dst GPU address |
| 2652 | * @num_gpu_pages: number of GPU pages to xfer |
| 2653 | * @fence: radeon fence object |
| 2654 | * |
Alex Deucher | 43fb778 | 2013-01-04 09:24:18 -0500 | [diff] [blame] | 2655 | * Copy GPU paging using the DMA engine (r6xx). |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2656 | * Used by the radeon ttm implementation to move pages if |
| 2657 | * registered as the asic copy callback. |
| 2658 | */ |
| 2659 | int r600_copy_dma(struct radeon_device *rdev, |
| 2660 | uint64_t src_offset, uint64_t dst_offset, |
| 2661 | unsigned num_gpu_pages, |
| 2662 | struct radeon_fence **fence) |
| 2663 | { |
| 2664 | struct radeon_semaphore *sem = NULL; |
| 2665 | int ring_index = rdev->asic->copy.dma_ring_index; |
| 2666 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
| 2667 | u32 size_in_dw, cur_size_in_dw; |
| 2668 | int i, num_loops; |
| 2669 | int r = 0; |
| 2670 | |
| 2671 | r = radeon_semaphore_create(rdev, &sem); |
| 2672 | if (r) { |
| 2673 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
| 2674 | return r; |
| 2675 | } |
| 2676 | |
| 2677 | size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; |
Alex Deucher | 43fb778 | 2013-01-04 09:24:18 -0500 | [diff] [blame] | 2678 | num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE); |
| 2679 | r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2680 | if (r) { |
| 2681 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
| 2682 | radeon_semaphore_free(rdev, &sem, NULL); |
| 2683 | return r; |
| 2684 | } |
| 2685 | |
| 2686 | if (radeon_fence_need_sync(*fence, ring->idx)) { |
| 2687 | radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, |
| 2688 | ring->idx); |
| 2689 | radeon_fence_note_sync(*fence, ring->idx); |
| 2690 | } else { |
| 2691 | radeon_semaphore_free(rdev, &sem, NULL); |
| 2692 | } |
| 2693 | |
| 2694 | for (i = 0; i < num_loops; i++) { |
| 2695 | cur_size_in_dw = size_in_dw; |
Alex Deucher | 909d9eb | 2013-01-02 18:30:21 -0500 | [diff] [blame] | 2696 | if (cur_size_in_dw > 0xFFFE) |
| 2697 | cur_size_in_dw = 0xFFFE; |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2698 | size_in_dw -= cur_size_in_dw; |
| 2699 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); |
| 2700 | radeon_ring_write(ring, dst_offset & 0xfffffffc); |
| 2701 | radeon_ring_write(ring, src_offset & 0xfffffffc); |
Alex Deucher | 43fb778 | 2013-01-04 09:24:18 -0500 | [diff] [blame] | 2702 | radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | |
| 2703 | (upper_32_bits(src_offset) & 0xff))); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2704 | src_offset += cur_size_in_dw * 4; |
| 2705 | dst_offset += cur_size_in_dw * 4; |
| 2706 | } |
| 2707 | |
| 2708 | r = radeon_fence_emit(rdev, fence, ring->idx); |
| 2709 | if (r) { |
| 2710 | radeon_ring_unlock_undo(rdev, ring); |
| 2711 | return r; |
| 2712 | } |
| 2713 | |
| 2714 | radeon_ring_unlock_commit(rdev, ring); |
| 2715 | radeon_semaphore_free(rdev, &sem, *fence); |
| 2716 | |
| 2717 | return r; |
| 2718 | } |
| 2719 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2720 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 2721 | uint32_t tiling_flags, uint32_t pitch, |
| 2722 | uint32_t offset, uint32_t obj_size) |
| 2723 | { |
| 2724 | /* FIXME: implement */ |
| 2725 | return 0; |
| 2726 | } |
| 2727 | |
| 2728 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) |
| 2729 | { |
| 2730 | /* FIXME: implement */ |
| 2731 | } |
| 2732 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 2733 | static int r600_startup(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2734 | { |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2735 | struct radeon_ring *ring; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2736 | int r; |
| 2737 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 2738 | /* enable pcie gen2 link */ |
| 2739 | r600_pcie_gen2_enable(rdev); |
| 2740 | |
Alex Deucher | 779720a | 2009-12-09 19:31:44 -0500 | [diff] [blame] | 2741 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
| 2742 | r = r600_init_microcode(rdev); |
| 2743 | if (r) { |
| 2744 | DRM_ERROR("Failed to load firmware!\n"); |
| 2745 | return r; |
| 2746 | } |
| 2747 | } |
| 2748 | |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2749 | r = r600_vram_scratch_init(rdev); |
| 2750 | if (r) |
| 2751 | return r; |
| 2752 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 2753 | r600_mc_program(rdev); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 2754 | if (rdev->flags & RADEON_IS_AGP) { |
| 2755 | r600_agp_enable(rdev); |
| 2756 | } else { |
| 2757 | r = r600_pcie_gart_enable(rdev); |
| 2758 | if (r) |
| 2759 | return r; |
| 2760 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2761 | r600_gpu_init(rdev); |
Jerome Glisse | c38c7b6 | 2010-02-04 17:27:27 +0100 | [diff] [blame] | 2762 | r = r600_blit_init(rdev); |
| 2763 | if (r) { |
| 2764 | r600_blit_fini(rdev); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 2765 | rdev->asic->copy.copy = NULL; |
Jerome Glisse | c38c7b6 | 2010-02-04 17:27:27 +0100 | [diff] [blame] | 2766 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
| 2767 | } |
Alex Deucher | b70d6bb | 2010-08-06 21:36:58 -0400 | [diff] [blame] | 2768 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2769 | /* allocate wb buffer */ |
| 2770 | r = radeon_wb_init(rdev); |
| 2771 | if (r) |
| 2772 | return r; |
| 2773 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 2774 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 2775 | if (r) { |
| 2776 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
| 2777 | return r; |
| 2778 | } |
| 2779 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2780 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); |
| 2781 | if (r) { |
| 2782 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
| 2783 | return r; |
| 2784 | } |
| 2785 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2786 | /* Enable IRQ */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2787 | r = r600_irq_init(rdev); |
| 2788 | if (r) { |
| 2789 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| 2790 | radeon_irq_kms_fini(rdev); |
| 2791 | return r; |
| 2792 | } |
| 2793 | r600_irq_set(rdev); |
| 2794 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2795 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2796 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 2797 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
| 2798 | 0, 0xfffff, RADEON_CP_PACKET2); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2799 | if (r) |
| 2800 | return r; |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2801 | |
| 2802 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
| 2803 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
| 2804 | DMA_RB_RPTR, DMA_RB_WPTR, |
| 2805 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
| 2806 | if (r) |
| 2807 | return r; |
| 2808 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2809 | r = r600_cp_load_microcode(rdev); |
| 2810 | if (r) |
| 2811 | return r; |
| 2812 | r = r600_cp_resume(rdev); |
| 2813 | if (r) |
| 2814 | return r; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2815 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2816 | r = r600_dma_resume(rdev); |
| 2817 | if (r) |
| 2818 | return r; |
| 2819 | |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 2820 | r = radeon_ib_pool_init(rdev); |
| 2821 | if (r) { |
| 2822 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2823 | return r; |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 2824 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2825 | |
Alex Deucher | d4e30ef | 2012-06-04 17:18:51 -0400 | [diff] [blame] | 2826 | r = r600_audio_init(rdev); |
| 2827 | if (r) { |
| 2828 | DRM_ERROR("radeon: audio init failed\n"); |
| 2829 | return r; |
| 2830 | } |
| 2831 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2832 | return 0; |
| 2833 | } |
| 2834 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2835 | void r600_vga_set_state(struct radeon_device *rdev, bool state) |
| 2836 | { |
| 2837 | uint32_t temp; |
| 2838 | |
| 2839 | temp = RREG32(CONFIG_CNTL); |
| 2840 | if (state == false) { |
| 2841 | temp &= ~(1<<0); |
| 2842 | temp |= (1<<1); |
| 2843 | } else { |
| 2844 | temp &= ~(1<<1); |
| 2845 | } |
| 2846 | WREG32(CONFIG_CNTL, temp); |
| 2847 | } |
| 2848 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2849 | int r600_resume(struct radeon_device *rdev) |
| 2850 | { |
| 2851 | int r; |
| 2852 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 2853 | /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, |
| 2854 | * posting will perform necessary task to bring back GPU into good |
| 2855 | * shape. |
| 2856 | */ |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2857 | /* post card */ |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 2858 | atom_asic_init(rdev->mode_info.atom_context); |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2859 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2860 | rdev->accel_working = true; |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2861 | r = r600_startup(rdev); |
| 2862 | if (r) { |
| 2863 | DRM_ERROR("r600 startup failed on resume\n"); |
Jerome Glisse | 6b7746e | 2012-02-20 17:57:20 -0500 | [diff] [blame] | 2864 | rdev->accel_working = false; |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2865 | return r; |
| 2866 | } |
| 2867 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2868 | return r; |
| 2869 | } |
| 2870 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2871 | int r600_suspend(struct radeon_device *rdev) |
| 2872 | { |
Rafał Miłecki | 38fd2c6 | 2010-01-28 18:16:30 +0100 | [diff] [blame] | 2873 | r600_audio_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2874 | r600_cp_stop(rdev); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2875 | r600_dma_stop(rdev); |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 2876 | r600_irq_suspend(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2877 | radeon_wb_disable(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 2878 | r600_pcie_gart_disable(rdev); |
Alex Deucher | 6ddddfe | 2011-10-14 10:51:22 -0400 | [diff] [blame] | 2879 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2880 | return 0; |
| 2881 | } |
| 2882 | |
| 2883 | /* Plan is to move initialization in that function and use |
| 2884 | * helper function so that radeon_device_init pretty much |
| 2885 | * do nothing more than calling asic specific function. This |
| 2886 | * should also allow to remove a bunch of callback function |
| 2887 | * like vram_info. |
| 2888 | */ |
| 2889 | int r600_init(struct radeon_device *rdev) |
| 2890 | { |
| 2891 | int r; |
| 2892 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2893 | if (r600_debugfs_mc_info_init(rdev)) { |
| 2894 | DRM_ERROR("Failed to register debugfs file for mc !\n"); |
| 2895 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2896 | /* Read BIOS */ |
| 2897 | if (!radeon_get_bios(rdev)) { |
| 2898 | if (ASIC_IS_AVIVO(rdev)) |
| 2899 | return -EINVAL; |
| 2900 | } |
| 2901 | /* Must be an ATOMBIOS */ |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 2902 | if (!rdev->is_atom_bios) { |
| 2903 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2904 | return -EINVAL; |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 2905 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2906 | r = radeon_atombios_init(rdev); |
| 2907 | if (r) |
| 2908 | return r; |
| 2909 | /* Post card if necessary */ |
Alex Deucher | fd909c3 | 2011-01-11 18:08:59 -0500 | [diff] [blame] | 2910 | if (!radeon_card_posted(rdev)) { |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 2911 | if (!rdev->bios) { |
| 2912 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
| 2913 | return -EINVAL; |
| 2914 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2915 | DRM_INFO("GPU not posted. posting now...\n"); |
| 2916 | atom_asic_init(rdev->mode_info.atom_context); |
| 2917 | } |
| 2918 | /* Initialize scratch registers */ |
| 2919 | r600_scratch_init(rdev); |
| 2920 | /* Initialize surface registers */ |
| 2921 | radeon_surface_init(rdev); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 2922 | /* Initialize clocks */ |
Michel Dänzer | 5e6dde7 | 2009-09-17 09:42:28 +0200 | [diff] [blame] | 2923 | radeon_get_clock_info(rdev->ddev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2924 | /* Fence driver */ |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 2925 | r = radeon_fence_driver_init(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2926 | if (r) |
| 2927 | return r; |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 2928 | if (rdev->flags & RADEON_IS_AGP) { |
| 2929 | r = radeon_agp_init(rdev); |
| 2930 | if (r) |
| 2931 | radeon_agp_disable(rdev); |
| 2932 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2933 | r = r600_mc_init(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 2934 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2935 | return r; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2936 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2937 | r = radeon_bo_init(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2938 | if (r) |
| 2939 | return r; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2940 | |
| 2941 | r = radeon_irq_kms_init(rdev); |
| 2942 | if (r) |
| 2943 | return r; |
| 2944 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2945 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
| 2946 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2947 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2948 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
| 2949 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
| 2950 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2951 | rdev->ih.ring_obj = NULL; |
| 2952 | r600_ih_ring_init(rdev, 64 * 1024); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2953 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 2954 | r = r600_pcie_gart_init(rdev); |
| 2955 | if (r) |
| 2956 | return r; |
| 2957 | |
Alex Deucher | 779720a | 2009-12-09 19:31:44 -0500 | [diff] [blame] | 2958 | rdev->accel_working = true; |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2959 | r = r600_startup(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2960 | if (r) { |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2961 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
| 2962 | r600_cp_fini(rdev); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2963 | r600_dma_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2964 | r600_irq_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2965 | radeon_wb_fini(rdev); |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 2966 | radeon_ib_pool_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2967 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | 75c8129 | 2009-10-01 18:02:14 +0200 | [diff] [blame] | 2968 | r600_pcie_gart_fini(rdev); |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 2969 | rdev->accel_working = false; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2970 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 2971 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2972 | return 0; |
| 2973 | } |
| 2974 | |
| 2975 | void r600_fini(struct radeon_device *rdev) |
| 2976 | { |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 2977 | r600_audio_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2978 | r600_blit_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2979 | r600_cp_fini(rdev); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 2980 | r600_dma_fini(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2981 | r600_irq_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2982 | radeon_wb_fini(rdev); |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 2983 | radeon_ib_pool_fini(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2984 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 2985 | r600_pcie_gart_fini(rdev); |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2986 | r600_vram_scratch_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2987 | radeon_agp_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2988 | radeon_gem_fini(rdev); |
| 2989 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2990 | radeon_bo_fini(rdev); |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 2991 | radeon_atombios_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2992 | kfree(rdev->bios); |
| 2993 | rdev->bios = NULL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2994 | } |
| 2995 | |
| 2996 | |
| 2997 | /* |
| 2998 | * CS stuff |
| 2999 | */ |
| 3000 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
| 3001 | { |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 3002 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 3003 | u32 next_rptr; |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 3004 | |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 3005 | if (ring->rptr_save_reg) { |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 3006 | next_rptr = ring->wptr + 3 + 4; |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 3007 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 3008 | radeon_ring_write(ring, ((ring->rptr_save_reg - |
| 3009 | PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
| 3010 | radeon_ring_write(ring, next_rptr); |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 3011 | } else if (rdev->wb.enabled) { |
| 3012 | next_rptr = ring->wptr + 5 + 4; |
| 3013 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); |
| 3014 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
| 3015 | radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); |
| 3016 | radeon_ring_write(ring, next_rptr); |
| 3017 | radeon_ring_write(ring, 0); |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 3018 | } |
| 3019 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 3020 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
| 3021 | radeon_ring_write(ring, |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 3022 | #ifdef __BIG_ENDIAN |
| 3023 | (2 << 0) | |
| 3024 | #endif |
| 3025 | (ib->gpu_addr & 0xFFFFFFFC)); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 3026 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
| 3027 | radeon_ring_write(ring, ib->length_dw); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3028 | } |
| 3029 | |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 3030 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3031 | { |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 3032 | struct radeon_ib ib; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3033 | uint32_t scratch; |
| 3034 | uint32_t tmp = 0; |
| 3035 | unsigned i; |
| 3036 | int r; |
| 3037 | |
| 3038 | r = radeon_scratch_get(rdev, &scratch); |
| 3039 | if (r) { |
| 3040 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
| 3041 | return r; |
| 3042 | } |
| 3043 | WREG32(scratch, 0xCAFEDEAD); |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 3044 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3045 | if (r) { |
| 3046 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
Michel Dänzer | af026c5 | 2012-09-20 10:31:10 +0200 | [diff] [blame] | 3047 | goto free_scratch; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3048 | } |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 3049 | ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); |
| 3050 | ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 3051 | ib.ptr[2] = 0xDEADBEEF; |
| 3052 | ib.length_dw = 3; |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 3053 | r = radeon_ib_schedule(rdev, &ib, NULL); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3054 | if (r) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3055 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
Michel Dänzer | af026c5 | 2012-09-20 10:31:10 +0200 | [diff] [blame] | 3056 | goto free_ib; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3057 | } |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 3058 | r = radeon_fence_wait(ib.fence, false); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3059 | if (r) { |
| 3060 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
Michel Dänzer | af026c5 | 2012-09-20 10:31:10 +0200 | [diff] [blame] | 3061 | goto free_ib; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3062 | } |
| 3063 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 3064 | tmp = RREG32(scratch); |
| 3065 | if (tmp == 0xDEADBEEF) |
| 3066 | break; |
| 3067 | DRM_UDELAY(1); |
| 3068 | } |
| 3069 | if (i < rdev->usec_timeout) { |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 3070 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3071 | } else { |
Daniel J Blueman | 4417d7f | 2010-09-22 17:57:19 +0100 | [diff] [blame] | 3072 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3073 | scratch, tmp); |
| 3074 | r = -EINVAL; |
| 3075 | } |
Michel Dänzer | af026c5 | 2012-09-20 10:31:10 +0200 | [diff] [blame] | 3076 | free_ib: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3077 | radeon_ib_free(rdev, &ib); |
Michel Dänzer | af026c5 | 2012-09-20 10:31:10 +0200 | [diff] [blame] | 3078 | free_scratch: |
| 3079 | radeon_scratch_free(rdev, scratch); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3080 | return r; |
| 3081 | } |
| 3082 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 3083 | /** |
| 3084 | * r600_dma_ib_test - test an IB on the DMA engine |
| 3085 | * |
| 3086 | * @rdev: radeon_device pointer |
| 3087 | * @ring: radeon_ring structure holding ring information |
| 3088 | * |
| 3089 | * Test a simple IB in the DMA ring (r6xx-SI). |
| 3090 | * Returns 0 on success, error on failure. |
| 3091 | */ |
| 3092 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
| 3093 | { |
| 3094 | struct radeon_ib ib; |
| 3095 | unsigned i; |
| 3096 | int r; |
| 3097 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
| 3098 | u32 tmp = 0; |
| 3099 | |
| 3100 | if (!ptr) { |
| 3101 | DRM_ERROR("invalid vram scratch pointer\n"); |
| 3102 | return -EINVAL; |
| 3103 | } |
| 3104 | |
| 3105 | tmp = 0xCAFEDEAD; |
| 3106 | writel(tmp, ptr); |
| 3107 | |
| 3108 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); |
| 3109 | if (r) { |
| 3110 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
| 3111 | return r; |
| 3112 | } |
| 3113 | |
| 3114 | ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); |
| 3115 | ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; |
| 3116 | ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; |
| 3117 | ib.ptr[3] = 0xDEADBEEF; |
| 3118 | ib.length_dw = 4; |
| 3119 | |
| 3120 | r = radeon_ib_schedule(rdev, &ib, NULL); |
| 3121 | if (r) { |
| 3122 | radeon_ib_free(rdev, &ib); |
| 3123 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
| 3124 | return r; |
| 3125 | } |
| 3126 | r = radeon_fence_wait(ib.fence, false); |
| 3127 | if (r) { |
| 3128 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
| 3129 | return r; |
| 3130 | } |
| 3131 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 3132 | tmp = readl(ptr); |
| 3133 | if (tmp == 0xDEADBEEF) |
| 3134 | break; |
| 3135 | DRM_UDELAY(1); |
| 3136 | } |
| 3137 | if (i < rdev->usec_timeout) { |
| 3138 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); |
| 3139 | } else { |
| 3140 | DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); |
| 3141 | r = -EINVAL; |
| 3142 | } |
| 3143 | radeon_ib_free(rdev, &ib); |
| 3144 | return r; |
| 3145 | } |
| 3146 | |
| 3147 | /** |
| 3148 | * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine |
| 3149 | * |
| 3150 | * @rdev: radeon_device pointer |
| 3151 | * @ib: IB object to schedule |
| 3152 | * |
| 3153 | * Schedule an IB in the DMA ring (r6xx-r7xx). |
| 3154 | */ |
| 3155 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
| 3156 | { |
| 3157 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
| 3158 | |
| 3159 | if (rdev->wb.enabled) { |
| 3160 | u32 next_rptr = ring->wptr + 4; |
| 3161 | while ((next_rptr & 7) != 5) |
| 3162 | next_rptr++; |
| 3163 | next_rptr += 3; |
| 3164 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); |
| 3165 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
| 3166 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); |
| 3167 | radeon_ring_write(ring, next_rptr); |
| 3168 | } |
| 3169 | |
| 3170 | /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. |
| 3171 | * Pad as necessary with NOPs. |
| 3172 | */ |
| 3173 | while ((ring->wptr & 7) != 5) |
| 3174 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
| 3175 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); |
| 3176 | radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); |
| 3177 | radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); |
| 3178 | |
| 3179 | } |
| 3180 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3181 | /* |
| 3182 | * Interrupts |
| 3183 | * |
| 3184 | * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty |
| 3185 | * the same as the CP ring buffer, but in reverse. Rather than the CPU |
| 3186 | * writing to the ring and the GPU consuming, the GPU writes to the ring |
| 3187 | * and host consumes. As the host irq handler processes interrupts, it |
| 3188 | * increments the rptr. When the rptr catches up with the wptr, all the |
| 3189 | * current interrupts have been processed. |
| 3190 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3191 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3192 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) |
| 3193 | { |
| 3194 | u32 rb_bufsz; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3195 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3196 | /* Align ring size */ |
| 3197 | rb_bufsz = drm_order(ring_size / 4); |
| 3198 | ring_size = (1 << rb_bufsz) * 4; |
| 3199 | rdev->ih.ring_size = ring_size; |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 3200 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
| 3201 | rdev->ih.rptr = 0; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3202 | } |
| 3203 | |
Alex Deucher | 25a857f | 2012-03-20 17:18:22 -0400 | [diff] [blame] | 3204 | int r600_ih_ring_alloc(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3205 | { |
| 3206 | int r; |
| 3207 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3208 | /* Allocate ring buffer */ |
| 3209 | if (rdev->ih.ring_obj == NULL) { |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 3210 | r = radeon_bo_create(rdev, rdev->ih.ring_size, |
Alex Deucher | 268b251 | 2010-11-17 19:00:26 -0500 | [diff] [blame] | 3211 | PAGE_SIZE, true, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3212 | RADEON_GEM_DOMAIN_GTT, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 3213 | NULL, &rdev->ih.ring_obj); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3214 | if (r) { |
| 3215 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); |
| 3216 | return r; |
| 3217 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3218 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
| 3219 | if (unlikely(r != 0)) |
| 3220 | return r; |
| 3221 | r = radeon_bo_pin(rdev->ih.ring_obj, |
| 3222 | RADEON_GEM_DOMAIN_GTT, |
| 3223 | &rdev->ih.gpu_addr); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3224 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3225 | radeon_bo_unreserve(rdev->ih.ring_obj); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3226 | DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); |
| 3227 | return r; |
| 3228 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3229 | r = radeon_bo_kmap(rdev->ih.ring_obj, |
| 3230 | (void **)&rdev->ih.ring); |
| 3231 | radeon_bo_unreserve(rdev->ih.ring_obj); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3232 | if (r) { |
| 3233 | DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); |
| 3234 | return r; |
| 3235 | } |
| 3236 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3237 | return 0; |
| 3238 | } |
| 3239 | |
Alex Deucher | 25a857f | 2012-03-20 17:18:22 -0400 | [diff] [blame] | 3240 | void r600_ih_ring_fini(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3241 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3242 | int r; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3243 | if (rdev->ih.ring_obj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3244 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
| 3245 | if (likely(r == 0)) { |
| 3246 | radeon_bo_kunmap(rdev->ih.ring_obj); |
| 3247 | radeon_bo_unpin(rdev->ih.ring_obj); |
| 3248 | radeon_bo_unreserve(rdev->ih.ring_obj); |
| 3249 | } |
| 3250 | radeon_bo_unref(&rdev->ih.ring_obj); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3251 | rdev->ih.ring = NULL; |
| 3252 | rdev->ih.ring_obj = NULL; |
| 3253 | } |
| 3254 | } |
| 3255 | |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 3256 | void r600_rlc_stop(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3257 | { |
| 3258 | |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 3259 | if ((rdev->family >= CHIP_RV770) && |
| 3260 | (rdev->family <= CHIP_RV740)) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3261 | /* r7xx asics need to soft reset RLC before halting */ |
| 3262 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); |
| 3263 | RREG32(SRBM_SOFT_RESET); |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 3264 | mdelay(15); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3265 | WREG32(SRBM_SOFT_RESET, 0); |
| 3266 | RREG32(SRBM_SOFT_RESET); |
| 3267 | } |
| 3268 | |
| 3269 | WREG32(RLC_CNTL, 0); |
| 3270 | } |
| 3271 | |
| 3272 | static void r600_rlc_start(struct radeon_device *rdev) |
| 3273 | { |
| 3274 | WREG32(RLC_CNTL, RLC_ENABLE); |
| 3275 | } |
| 3276 | |
| 3277 | static int r600_rlc_init(struct radeon_device *rdev) |
| 3278 | { |
| 3279 | u32 i; |
| 3280 | const __be32 *fw_data; |
| 3281 | |
| 3282 | if (!rdev->rlc_fw) |
| 3283 | return -EINVAL; |
| 3284 | |
| 3285 | r600_rlc_stop(rdev); |
| 3286 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3287 | WREG32(RLC_HB_CNTL, 0); |
Alex Deucher | c420c74 | 2012-03-20 17:18:39 -0400 | [diff] [blame] | 3288 | |
| 3289 | if (rdev->family == CHIP_ARUBA) { |
| 3290 | WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); |
| 3291 | WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); |
| 3292 | } |
| 3293 | if (rdev->family <= CHIP_CAYMAN) { |
| 3294 | WREG32(RLC_HB_BASE, 0); |
| 3295 | WREG32(RLC_HB_RPTR, 0); |
| 3296 | WREG32(RLC_HB_WPTR, 0); |
| 3297 | } |
Alex Deucher | 1272780 | 2011-03-02 20:07:32 -0500 | [diff] [blame] | 3298 | if (rdev->family <= CHIP_CAICOS) { |
| 3299 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); |
| 3300 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); |
| 3301 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3302 | WREG32(RLC_MC_CNTL, 0); |
| 3303 | WREG32(RLC_UCODE_CNTL, 0); |
| 3304 | |
| 3305 | fw_data = (const __be32 *)rdev->rlc_fw->data; |
Alex Deucher | c420c74 | 2012-03-20 17:18:39 -0400 | [diff] [blame] | 3306 | if (rdev->family >= CHIP_ARUBA) { |
| 3307 | for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) { |
| 3308 | WREG32(RLC_UCODE_ADDR, i); |
| 3309 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 3310 | } |
| 3311 | } else if (rdev->family >= CHIP_CAYMAN) { |
Alex Deucher | 1272780 | 2011-03-02 20:07:32 -0500 | [diff] [blame] | 3312 | for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { |
| 3313 | WREG32(RLC_UCODE_ADDR, i); |
| 3314 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 3315 | } |
| 3316 | } else if (rdev->family >= CHIP_CEDAR) { |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 3317 | for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { |
| 3318 | WREG32(RLC_UCODE_ADDR, i); |
| 3319 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 3320 | } |
| 3321 | } else if (rdev->family >= CHIP_RV770) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3322 | for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { |
| 3323 | WREG32(RLC_UCODE_ADDR, i); |
| 3324 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 3325 | } |
| 3326 | } else { |
| 3327 | for (i = 0; i < RLC_UCODE_SIZE; i++) { |
| 3328 | WREG32(RLC_UCODE_ADDR, i); |
| 3329 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 3330 | } |
| 3331 | } |
| 3332 | WREG32(RLC_UCODE_ADDR, 0); |
| 3333 | |
| 3334 | r600_rlc_start(rdev); |
| 3335 | |
| 3336 | return 0; |
| 3337 | } |
| 3338 | |
| 3339 | static void r600_enable_interrupts(struct radeon_device *rdev) |
| 3340 | { |
| 3341 | u32 ih_cntl = RREG32(IH_CNTL); |
| 3342 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); |
| 3343 | |
| 3344 | ih_cntl |= ENABLE_INTR; |
| 3345 | ih_rb_cntl |= IH_RB_ENABLE; |
| 3346 | WREG32(IH_CNTL, ih_cntl); |
| 3347 | WREG32(IH_RB_CNTL, ih_rb_cntl); |
| 3348 | rdev->ih.enabled = true; |
| 3349 | } |
| 3350 | |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 3351 | void r600_disable_interrupts(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3352 | { |
| 3353 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); |
| 3354 | u32 ih_cntl = RREG32(IH_CNTL); |
| 3355 | |
| 3356 | ih_rb_cntl &= ~IH_RB_ENABLE; |
| 3357 | ih_cntl &= ~ENABLE_INTR; |
| 3358 | WREG32(IH_RB_CNTL, ih_rb_cntl); |
| 3359 | WREG32(IH_CNTL, ih_cntl); |
| 3360 | /* set rptr, wptr to 0 */ |
| 3361 | WREG32(IH_RB_RPTR, 0); |
| 3362 | WREG32(IH_RB_WPTR, 0); |
| 3363 | rdev->ih.enabled = false; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3364 | rdev->ih.rptr = 0; |
| 3365 | } |
| 3366 | |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3367 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
| 3368 | { |
| 3369 | u32 tmp; |
| 3370 | |
Alex Deucher | 3555e53 | 2010-10-08 12:09:12 -0400 | [diff] [blame] | 3371 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 3372 | tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
| 3373 | WREG32(DMA_CNTL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3374 | WREG32(GRBM_INT_CNTL, 0); |
| 3375 | WREG32(DxMODE_INT_MASK, 0); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3376 | WREG32(D1GRPH_INTERRUPT_CONTROL, 0); |
| 3377 | WREG32(D2GRPH_INTERRUPT_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3378 | if (ASIC_IS_DCE3(rdev)) { |
| 3379 | WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); |
| 3380 | WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); |
| 3381 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
| 3382 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
| 3383 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
| 3384 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
| 3385 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
| 3386 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
| 3387 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
| 3388 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
| 3389 | if (ASIC_IS_DCE32(rdev)) { |
| 3390 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 3391 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3392 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 3393 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 3394 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
| 3395 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); |
| 3396 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
| 3397 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3398 | } else { |
| 3399 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
| 3400 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); |
| 3401 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
| 3402 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3403 | } |
| 3404 | } else { |
| 3405 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); |
| 3406 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); |
| 3407 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 3408 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3409 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 3410 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3411 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 3412 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3413 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
| 3414 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); |
| 3415 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
| 3416 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3417 | } |
| 3418 | } |
| 3419 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3420 | int r600_irq_init(struct radeon_device *rdev) |
| 3421 | { |
| 3422 | int ret = 0; |
| 3423 | int rb_bufsz; |
| 3424 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; |
| 3425 | |
| 3426 | /* allocate ring */ |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 3427 | ret = r600_ih_ring_alloc(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3428 | if (ret) |
| 3429 | return ret; |
| 3430 | |
| 3431 | /* disable irqs */ |
| 3432 | r600_disable_interrupts(rdev); |
| 3433 | |
| 3434 | /* init rlc */ |
| 3435 | ret = r600_rlc_init(rdev); |
| 3436 | if (ret) { |
| 3437 | r600_ih_ring_fini(rdev); |
| 3438 | return ret; |
| 3439 | } |
| 3440 | |
| 3441 | /* setup interrupt control */ |
| 3442 | /* set dummy read address to ring address */ |
| 3443 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); |
| 3444 | interrupt_cntl = RREG32(INTERRUPT_CNTL); |
| 3445 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi |
| 3446 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN |
| 3447 | */ |
| 3448 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; |
| 3449 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ |
| 3450 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; |
| 3451 | WREG32(INTERRUPT_CNTL, interrupt_cntl); |
| 3452 | |
| 3453 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); |
| 3454 | rb_bufsz = drm_order(rdev->ih.ring_size / 4); |
| 3455 | |
| 3456 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | |
| 3457 | IH_WPTR_OVERFLOW_CLEAR | |
| 3458 | (rb_bufsz << 1)); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 3459 | |
| 3460 | if (rdev->wb.enabled) |
| 3461 | ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; |
| 3462 | |
| 3463 | /* set the writeback address whether it's enabled or not */ |
| 3464 | WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); |
| 3465 | WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3466 | |
| 3467 | WREG32(IH_RB_CNTL, ih_rb_cntl); |
| 3468 | |
| 3469 | /* set rptr, wptr to 0 */ |
| 3470 | WREG32(IH_RB_RPTR, 0); |
| 3471 | WREG32(IH_RB_WPTR, 0); |
| 3472 | |
| 3473 | /* Default settings for IH_CNTL (disabled at first) */ |
| 3474 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); |
| 3475 | /* RPTR_REARM only works if msi's are enabled */ |
| 3476 | if (rdev->msi_enabled) |
| 3477 | ih_cntl |= RPTR_REARM; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3478 | WREG32(IH_CNTL, ih_cntl); |
| 3479 | |
| 3480 | /* force the active interrupt state to all disabled */ |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 3481 | if (rdev->family >= CHIP_CEDAR) |
| 3482 | evergreen_disable_interrupt_state(rdev); |
| 3483 | else |
| 3484 | r600_disable_interrupt_state(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3485 | |
Dave Airlie | 2099810 | 2012-04-03 11:53:05 +0100 | [diff] [blame] | 3486 | /* at this point everything should be setup correctly to enable master */ |
| 3487 | pci_set_master(rdev->pdev); |
| 3488 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3489 | /* enable irqs */ |
| 3490 | r600_enable_interrupts(rdev); |
| 3491 | |
| 3492 | return ret; |
| 3493 | } |
| 3494 | |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 3495 | void r600_irq_suspend(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3496 | { |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 3497 | r600_irq_disable(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3498 | r600_rlc_stop(rdev); |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 3499 | } |
| 3500 | |
| 3501 | void r600_irq_fini(struct radeon_device *rdev) |
| 3502 | { |
| 3503 | r600_irq_suspend(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3504 | r600_ih_ring_fini(rdev); |
| 3505 | } |
| 3506 | |
| 3507 | int r600_irq_set(struct radeon_device *rdev) |
| 3508 | { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3509 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
| 3510 | u32 mode_int = 0; |
| 3511 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 3512 | u32 grbm_int_cntl = 0; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3513 | u32 hdmi0, hdmi1; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3514 | u32 d1grph = 0, d2grph = 0; |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 3515 | u32 dma_cntl; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3516 | |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 3517 | if (!rdev->irq.installed) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 3518 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 3519 | return -EINVAL; |
| 3520 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3521 | /* don't enable anything if the ih is disabled */ |
Jerome Glisse | 79c2bbc | 2010-01-15 14:44:38 +0100 | [diff] [blame] | 3522 | if (!rdev->ih.enabled) { |
| 3523 | r600_disable_interrupts(rdev); |
| 3524 | /* force the active interrupt state to all disabled */ |
| 3525 | r600_disable_interrupt_state(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3526 | return 0; |
Jerome Glisse | 79c2bbc | 2010-01-15 14:44:38 +0100 | [diff] [blame] | 3527 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3528 | |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3529 | if (ASIC_IS_DCE3(rdev)) { |
| 3530 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3531 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3532 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3533 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3534 | if (ASIC_IS_DCE32(rdev)) { |
| 3535 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3536 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 3537 | hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
| 3538 | hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3539 | } else { |
| 3540 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
| 3541 | hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3542 | } |
| 3543 | } else { |
| 3544 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3545 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3546 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3547 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
| 3548 | hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3549 | } |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 3550 | dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3551 | |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 3552 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3553 | DRM_DEBUG("r600_irq_set: sw int\n"); |
| 3554 | cp_int_cntl |= RB_INT_ENABLE; |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 3555 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3556 | } |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 3557 | |
| 3558 | if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { |
| 3559 | DRM_DEBUG("r600_irq_set: sw int dma\n"); |
| 3560 | dma_cntl |= TRAP_ENABLE; |
| 3561 | } |
| 3562 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3563 | if (rdev->irq.crtc_vblank_int[0] || |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 3564 | atomic_read(&rdev->irq.pflip[0])) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3565 | DRM_DEBUG("r600_irq_set: vblank 0\n"); |
| 3566 | mode_int |= D1MODE_VBLANK_INT_MASK; |
| 3567 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3568 | if (rdev->irq.crtc_vblank_int[1] || |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 3569 | atomic_read(&rdev->irq.pflip[1])) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3570 | DRM_DEBUG("r600_irq_set: vblank 1\n"); |
| 3571 | mode_int |= D2MODE_VBLANK_INT_MASK; |
| 3572 | } |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3573 | if (rdev->irq.hpd[0]) { |
| 3574 | DRM_DEBUG("r600_irq_set: hpd 1\n"); |
| 3575 | hpd1 |= DC_HPDx_INT_EN; |
| 3576 | } |
| 3577 | if (rdev->irq.hpd[1]) { |
| 3578 | DRM_DEBUG("r600_irq_set: hpd 2\n"); |
| 3579 | hpd2 |= DC_HPDx_INT_EN; |
| 3580 | } |
| 3581 | if (rdev->irq.hpd[2]) { |
| 3582 | DRM_DEBUG("r600_irq_set: hpd 3\n"); |
| 3583 | hpd3 |= DC_HPDx_INT_EN; |
| 3584 | } |
| 3585 | if (rdev->irq.hpd[3]) { |
| 3586 | DRM_DEBUG("r600_irq_set: hpd 4\n"); |
| 3587 | hpd4 |= DC_HPDx_INT_EN; |
| 3588 | } |
| 3589 | if (rdev->irq.hpd[4]) { |
| 3590 | DRM_DEBUG("r600_irq_set: hpd 5\n"); |
| 3591 | hpd5 |= DC_HPDx_INT_EN; |
| 3592 | } |
| 3593 | if (rdev->irq.hpd[5]) { |
| 3594 | DRM_DEBUG("r600_irq_set: hpd 6\n"); |
| 3595 | hpd6 |= DC_HPDx_INT_EN; |
| 3596 | } |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3597 | if (rdev->irq.afmt[0]) { |
| 3598 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); |
| 3599 | hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3600 | } |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3601 | if (rdev->irq.afmt[1]) { |
| 3602 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); |
| 3603 | hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3604 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3605 | |
| 3606 | WREG32(CP_INT_CNTL, cp_int_cntl); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 3607 | WREG32(DMA_CNTL, dma_cntl); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3608 | WREG32(DxMODE_INT_MASK, mode_int); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3609 | WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); |
| 3610 | WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 3611 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3612 | if (ASIC_IS_DCE3(rdev)) { |
| 3613 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
| 3614 | WREG32(DC_HPD2_INT_CONTROL, hpd2); |
| 3615 | WREG32(DC_HPD3_INT_CONTROL, hpd3); |
| 3616 | WREG32(DC_HPD4_INT_CONTROL, hpd4); |
| 3617 | if (ASIC_IS_DCE32(rdev)) { |
| 3618 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
| 3619 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 3620 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); |
| 3621 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3622 | } else { |
| 3623 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
| 3624 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3625 | } |
| 3626 | } else { |
| 3627 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
| 3628 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
| 3629 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3630 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
| 3631 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3632 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3633 | |
| 3634 | return 0; |
| 3635 | } |
| 3636 | |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 3637 | static void r600_irq_ack(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3638 | { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3639 | u32 tmp; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3640 | |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3641 | if (ASIC_IS_DCE3(rdev)) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3642 | rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); |
| 3643 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); |
| 3644 | rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3645 | if (ASIC_IS_DCE32(rdev)) { |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 3646 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); |
| 3647 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3648 | } else { |
| 3649 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); |
| 3650 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); |
| 3651 | } |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3652 | } else { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3653 | rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
| 3654 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); |
| 3655 | rdev->irq.stat_regs.r600.disp_int_cont2 = 0; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3656 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); |
| 3657 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3658 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3659 | rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); |
| 3660 | rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3661 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3662 | if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) |
| 3663 | WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); |
| 3664 | if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) |
| 3665 | WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); |
| 3666 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3667 | WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3668 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3669 | WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3670 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3671 | WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3672 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3673 | WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3674 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3675 | if (ASIC_IS_DCE3(rdev)) { |
| 3676 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
| 3677 | tmp |= DC_HPDx_INT_ACK; |
| 3678 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
| 3679 | } else { |
| 3680 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); |
| 3681 | tmp |= DC_HPDx_INT_ACK; |
| 3682 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
| 3683 | } |
| 3684 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3685 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3686 | if (ASIC_IS_DCE3(rdev)) { |
| 3687 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
| 3688 | tmp |= DC_HPDx_INT_ACK; |
| 3689 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
| 3690 | } else { |
| 3691 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); |
| 3692 | tmp |= DC_HPDx_INT_ACK; |
| 3693 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
| 3694 | } |
| 3695 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3696 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3697 | if (ASIC_IS_DCE3(rdev)) { |
| 3698 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
| 3699 | tmp |= DC_HPDx_INT_ACK; |
| 3700 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
| 3701 | } else { |
| 3702 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); |
| 3703 | tmp |= DC_HPDx_INT_ACK; |
| 3704 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
| 3705 | } |
| 3706 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3707 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3708 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
| 3709 | tmp |= DC_HPDx_INT_ACK; |
| 3710 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
| 3711 | } |
| 3712 | if (ASIC_IS_DCE32(rdev)) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3713 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3714 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
| 3715 | tmp |= DC_HPDx_INT_ACK; |
| 3716 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
| 3717 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3718 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3719 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
| 3720 | tmp |= DC_HPDx_INT_ACK; |
| 3721 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
| 3722 | } |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3723 | if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 3724 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3725 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 3726 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3727 | } |
| 3728 | if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 3729 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3730 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 3731 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3732 | } |
| 3733 | } else { |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3734 | if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { |
| 3735 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); |
| 3736 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; |
| 3737 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); |
| 3738 | } |
| 3739 | if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { |
| 3740 | if (ASIC_IS_DCE3(rdev)) { |
| 3741 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); |
| 3742 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; |
| 3743 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); |
| 3744 | } else { |
| 3745 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); |
| 3746 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; |
| 3747 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); |
| 3748 | } |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3749 | } |
| 3750 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3751 | } |
| 3752 | |
| 3753 | void r600_irq_disable(struct radeon_device *rdev) |
| 3754 | { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3755 | r600_disable_interrupts(rdev); |
| 3756 | /* Wait and acknowledge irq */ |
| 3757 | mdelay(1); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3758 | r600_irq_ack(rdev); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3759 | r600_disable_interrupt_state(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3760 | } |
| 3761 | |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 3762 | static u32 r600_get_ih_wptr(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3763 | { |
| 3764 | u32 wptr, tmp; |
| 3765 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 3766 | if (rdev->wb.enabled) |
Cédric Cano | 204ae24 | 2011-04-19 11:07:13 -0400 | [diff] [blame] | 3767 | wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 3768 | else |
| 3769 | wptr = RREG32(IH_RB_WPTR); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3770 | |
| 3771 | if (wptr & RB_OVERFLOW) { |
Jerome Glisse | 7924e5e | 2010-01-15 14:44:39 +0100 | [diff] [blame] | 3772 | /* When a ring buffer overflow happen start parsing interrupt |
| 3773 | * from the last not overwritten vector (wptr + 16). Hopefully |
| 3774 | * this should allow us to catchup. |
| 3775 | */ |
| 3776 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", |
| 3777 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); |
| 3778 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3779 | tmp = RREG32(IH_RB_CNTL); |
| 3780 | tmp |= IH_WPTR_OVERFLOW_CLEAR; |
| 3781 | WREG32(IH_RB_CNTL, tmp); |
| 3782 | } |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 3783 | return (wptr & rdev->ih.ptr_mask); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3784 | } |
| 3785 | |
| 3786 | /* r600 IV Ring |
| 3787 | * Each IV ring entry is 128 bits: |
| 3788 | * [7:0] - interrupt source id |
| 3789 | * [31:8] - reserved |
| 3790 | * [59:32] - interrupt source data |
| 3791 | * [127:60] - reserved |
| 3792 | * |
| 3793 | * The basic interrupt vector entries |
| 3794 | * are decoded as follows: |
| 3795 | * src_id src_data description |
| 3796 | * 1 0 D1 Vblank |
| 3797 | * 1 1 D1 Vline |
| 3798 | * 5 0 D2 Vblank |
| 3799 | * 5 1 D2 Vline |
| 3800 | * 19 0 FP Hot plug detection A |
| 3801 | * 19 1 FP Hot plug detection B |
| 3802 | * 19 2 DAC A auto-detection |
| 3803 | * 19 3 DAC B auto-detection |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3804 | * 21 4 HDMI block A |
| 3805 | * 21 5 HDMI block B |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3806 | * 176 - CP_INT RB |
| 3807 | * 177 - CP_INT IB1 |
| 3808 | * 178 - CP_INT IB2 |
| 3809 | * 181 - EOP Interrupt |
| 3810 | * 233 - GUI Idle |
| 3811 | * |
| 3812 | * Note, these are based on r600 and may need to be |
| 3813 | * adjusted or added to on newer asics |
| 3814 | */ |
| 3815 | |
| 3816 | int r600_irq_process(struct radeon_device *rdev) |
| 3817 | { |
Dave Airlie | 682f1a5 | 2011-06-18 03:59:51 +0000 | [diff] [blame] | 3818 | u32 wptr; |
| 3819 | u32 rptr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3820 | u32 src_id, src_data; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3821 | u32 ring_index; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3822 | bool queue_hotplug = false; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3823 | bool queue_hdmi = false; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3824 | |
Dave Airlie | 682f1a5 | 2011-06-18 03:59:51 +0000 | [diff] [blame] | 3825 | if (!rdev->ih.enabled || rdev->shutdown) |
Jerome Glisse | 79c2bbc | 2010-01-15 14:44:38 +0100 | [diff] [blame] | 3826 | return IRQ_NONE; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3827 | |
Benjamin Herrenschmidt | f6a5693 | 2011-07-13 06:28:22 +0000 | [diff] [blame] | 3828 | /* No MSIs, need a dummy read to flush PCI DMAs */ |
| 3829 | if (!rdev->msi_enabled) |
| 3830 | RREG32(IH_RB_WPTR); |
| 3831 | |
Dave Airlie | 682f1a5 | 2011-06-18 03:59:51 +0000 | [diff] [blame] | 3832 | wptr = r600_get_ih_wptr(rdev); |
Christian Koenig | c20dc36 | 2012-05-16 21:45:24 +0200 | [diff] [blame] | 3833 | |
| 3834 | restart_ih: |
| 3835 | /* is somebody else already processing irqs? */ |
| 3836 | if (atomic_xchg(&rdev->ih.lock, 1)) |
| 3837 | return IRQ_NONE; |
| 3838 | |
Dave Airlie | 682f1a5 | 2011-06-18 03:59:51 +0000 | [diff] [blame] | 3839 | rptr = rdev->ih.rptr; |
| 3840 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
| 3841 | |
Benjamin Herrenschmidt | 964f664 | 2011-07-13 16:28:19 +1000 | [diff] [blame] | 3842 | /* Order reading of wptr vs. reading of IH ring data */ |
| 3843 | rmb(); |
| 3844 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3845 | /* display interrupts */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3846 | r600_irq_ack(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3847 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3848 | while (rptr != wptr) { |
| 3849 | /* wptr/rptr are in bytes! */ |
| 3850 | ring_index = rptr / 4; |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 3851 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
| 3852 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3853 | |
| 3854 | switch (src_id) { |
| 3855 | case 1: /* D1 vblank/vline */ |
| 3856 | switch (src_data) { |
| 3857 | case 0: /* D1 vblank */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3858 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3859 | if (rdev->irq.crtc_vblank_int[0]) { |
| 3860 | drm_handle_vblank(rdev->ddev, 0); |
| 3861 | rdev->pm.vblank_sync = true; |
| 3862 | wake_up(&rdev->irq.vblank_queue); |
| 3863 | } |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 3864 | if (atomic_read(&rdev->irq.pflip[0])) |
Mario Kleiner | 3e4ea74 | 2010-11-21 10:59:02 -0500 | [diff] [blame] | 3865 | radeon_crtc_handle_flip(rdev, 0); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3866 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3867 | DRM_DEBUG("IH: D1 vblank\n"); |
| 3868 | } |
| 3869 | break; |
| 3870 | case 1: /* D1 vline */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3871 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { |
| 3872 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3873 | DRM_DEBUG("IH: D1 vline\n"); |
| 3874 | } |
| 3875 | break; |
| 3876 | default: |
Alex Deucher | b042589 | 2010-01-11 19:47:38 -0500 | [diff] [blame] | 3877 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3878 | break; |
| 3879 | } |
| 3880 | break; |
| 3881 | case 5: /* D2 vblank/vline */ |
| 3882 | switch (src_data) { |
| 3883 | case 0: /* D2 vblank */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3884 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3885 | if (rdev->irq.crtc_vblank_int[1]) { |
| 3886 | drm_handle_vblank(rdev->ddev, 1); |
| 3887 | rdev->pm.vblank_sync = true; |
| 3888 | wake_up(&rdev->irq.vblank_queue); |
| 3889 | } |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 3890 | if (atomic_read(&rdev->irq.pflip[1])) |
Mario Kleiner | 3e4ea74 | 2010-11-21 10:59:02 -0500 | [diff] [blame] | 3891 | radeon_crtc_handle_flip(rdev, 1); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3892 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3893 | DRM_DEBUG("IH: D2 vblank\n"); |
| 3894 | } |
| 3895 | break; |
| 3896 | case 1: /* D1 vline */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3897 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { |
| 3898 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3899 | DRM_DEBUG("IH: D2 vline\n"); |
| 3900 | } |
| 3901 | break; |
| 3902 | default: |
Alex Deucher | b042589 | 2010-01-11 19:47:38 -0500 | [diff] [blame] | 3903 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3904 | break; |
| 3905 | } |
| 3906 | break; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3907 | case 19: /* HPD/DAC hotplug */ |
| 3908 | switch (src_data) { |
| 3909 | case 0: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3910 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { |
| 3911 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3912 | queue_hotplug = true; |
| 3913 | DRM_DEBUG("IH: HPD1\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3914 | } |
| 3915 | break; |
| 3916 | case 1: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3917 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { |
| 3918 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3919 | queue_hotplug = true; |
| 3920 | DRM_DEBUG("IH: HPD2\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3921 | } |
| 3922 | break; |
| 3923 | case 4: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3924 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { |
| 3925 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3926 | queue_hotplug = true; |
| 3927 | DRM_DEBUG("IH: HPD3\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3928 | } |
| 3929 | break; |
| 3930 | case 5: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3931 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { |
| 3932 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3933 | queue_hotplug = true; |
| 3934 | DRM_DEBUG("IH: HPD4\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3935 | } |
| 3936 | break; |
| 3937 | case 10: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3938 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { |
| 3939 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3940 | queue_hotplug = true; |
| 3941 | DRM_DEBUG("IH: HPD5\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3942 | } |
| 3943 | break; |
| 3944 | case 12: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3945 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
| 3946 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3947 | queue_hotplug = true; |
| 3948 | DRM_DEBUG("IH: HPD6\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3949 | } |
| 3950 | break; |
| 3951 | default: |
Alex Deucher | b042589 | 2010-01-11 19:47:38 -0500 | [diff] [blame] | 3952 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3953 | break; |
| 3954 | } |
| 3955 | break; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 3956 | case 21: /* hdmi */ |
| 3957 | switch (src_data) { |
| 3958 | case 4: |
| 3959 | if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { |
| 3960 | rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; |
| 3961 | queue_hdmi = true; |
| 3962 | DRM_DEBUG("IH: HDMI0\n"); |
| 3963 | } |
| 3964 | break; |
| 3965 | case 5: |
| 3966 | if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { |
| 3967 | rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; |
| 3968 | queue_hdmi = true; |
| 3969 | DRM_DEBUG("IH: HDMI1\n"); |
| 3970 | } |
| 3971 | break; |
| 3972 | default: |
| 3973 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 3974 | break; |
| 3975 | } |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3976 | break; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3977 | case 176: /* CP_INT in ring buffer */ |
| 3978 | case 177: /* CP_INT in IB1 */ |
| 3979 | case 178: /* CP_INT in IB2 */ |
| 3980 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 3981 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3982 | break; |
| 3983 | case 181: /* CP EOP event */ |
| 3984 | DRM_DEBUG("IH: CP EOP\n"); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 3985 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3986 | break; |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 3987 | case 224: /* DMA trap event */ |
| 3988 | DRM_DEBUG("IH: DMA trap\n"); |
| 3989 | radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); |
| 3990 | break; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 3991 | case 233: /* GUI IDLE */ |
Ilija Hadzic | 303c805 | 2011-06-07 14:54:48 -0400 | [diff] [blame] | 3992 | DRM_DEBUG("IH: GUI idle\n"); |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 3993 | break; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3994 | default: |
Alex Deucher | b042589 | 2010-01-11 19:47:38 -0500 | [diff] [blame] | 3995 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3996 | break; |
| 3997 | } |
| 3998 | |
| 3999 | /* wptr/rptr are in bytes! */ |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 4000 | rptr += 16; |
| 4001 | rptr &= rdev->ih.ptr_mask; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 4002 | } |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 4003 | if (queue_hotplug) |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 4004 | schedule_work(&rdev->hotplug_work); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 4005 | if (queue_hdmi) |
| 4006 | schedule_work(&rdev->audio_work); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 4007 | rdev->ih.rptr = rptr; |
| 4008 | WREG32(IH_RB_RPTR, rdev->ih.rptr); |
Christian Koenig | c20dc36 | 2012-05-16 21:45:24 +0200 | [diff] [blame] | 4009 | atomic_set(&rdev->ih.lock, 0); |
| 4010 | |
| 4011 | /* make sure wptr hasn't changed while processing */ |
| 4012 | wptr = r600_get_ih_wptr(rdev); |
| 4013 | if (wptr != rptr) |
| 4014 | goto restart_ih; |
| 4015 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 4016 | return IRQ_HANDLED; |
| 4017 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 4018 | |
| 4019 | /* |
| 4020 | * Debugfs info |
| 4021 | */ |
| 4022 | #if defined(CONFIG_DEBUG_FS) |
| 4023 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 4024 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) |
| 4025 | { |
| 4026 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 4027 | struct drm_device *dev = node->minor->dev; |
| 4028 | struct radeon_device *rdev = dev->dev_private; |
| 4029 | |
| 4030 | DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); |
| 4031 | DREG32_SYS(m, rdev, VM_L2_STATUS); |
| 4032 | return 0; |
| 4033 | } |
| 4034 | |
| 4035 | static struct drm_info_list r600_mc_info_list[] = { |
| 4036 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 4037 | }; |
| 4038 | #endif |
| 4039 | |
| 4040 | int r600_debugfs_mc_info_init(struct radeon_device *rdev) |
| 4041 | { |
| 4042 | #if defined(CONFIG_DEBUG_FS) |
| 4043 | return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); |
| 4044 | #else |
| 4045 | return 0; |
| 4046 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 4047 | } |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 4048 | |
| 4049 | /** |
| 4050 | * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl |
| 4051 | * rdev: radeon device structure |
| 4052 | * bo: buffer object struct which userspace is waiting for idle |
| 4053 | * |
| 4054 | * Some R6XX/R7XX doesn't seems to take into account HDP flush performed |
| 4055 | * through ring buffer, this leads to corruption in rendering, see |
| 4056 | * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we |
| 4057 | * directly perform HDP flush by writing register through MMIO. |
| 4058 | */ |
| 4059 | void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) |
| 4060 | { |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 4061 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read |
Alex Deucher | f3886f8 | 2010-12-08 10:05:34 -0500 | [diff] [blame] | 4062 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. |
| 4063 | * This seems to cause problems on some AGP cards. Just use the old |
| 4064 | * method for them. |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 4065 | */ |
Alex Deucher | e488459 | 2010-09-27 10:57:10 -0400 | [diff] [blame] | 4066 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
Alex Deucher | f3886f8 | 2010-12-08 10:05:34 -0500 | [diff] [blame] | 4067 | rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 4068 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 4069 | u32 tmp; |
| 4070 | |
| 4071 | WREG32(HDP_DEBUG1, 0); |
| 4072 | tmp = readl((void __iomem *)ptr); |
| 4073 | } else |
| 4074 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 4075 | } |
Alex Deucher | 3313e3d | 2011-01-06 18:49:34 -0500 | [diff] [blame] | 4076 | |
| 4077 | void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
| 4078 | { |
| 4079 | u32 link_width_cntl, mask, target_reg; |
| 4080 | |
| 4081 | if (rdev->flags & RADEON_IS_IGP) |
| 4082 | return; |
| 4083 | |
| 4084 | if (!(rdev->flags & RADEON_IS_PCIE)) |
| 4085 | return; |
| 4086 | |
| 4087 | /* x2 cards have a special sequence */ |
| 4088 | if (ASIC_IS_X2(rdev)) |
| 4089 | return; |
| 4090 | |
| 4091 | /* FIXME wait for idle */ |
| 4092 | |
| 4093 | switch (lanes) { |
| 4094 | case 0: |
| 4095 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; |
| 4096 | break; |
| 4097 | case 1: |
| 4098 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; |
| 4099 | break; |
| 4100 | case 2: |
| 4101 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; |
| 4102 | break; |
| 4103 | case 4: |
| 4104 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; |
| 4105 | break; |
| 4106 | case 8: |
| 4107 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; |
| 4108 | break; |
| 4109 | case 12: |
| 4110 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
| 4111 | break; |
| 4112 | case 16: |
| 4113 | default: |
| 4114 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
| 4115 | break; |
| 4116 | } |
| 4117 | |
| 4118 | link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
| 4119 | |
| 4120 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == |
| 4121 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) |
| 4122 | return; |
| 4123 | |
| 4124 | if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) |
| 4125 | return; |
| 4126 | |
| 4127 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | |
| 4128 | RADEON_PCIE_LC_RECONFIG_NOW | |
| 4129 | R600_PCIE_LC_RENEGOTIATE_EN | |
| 4130 | R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); |
| 4131 | link_width_cntl |= mask; |
| 4132 | |
| 4133 | WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 4134 | |
| 4135 | /* some northbridges can renegotiate the link rather than requiring |
| 4136 | * a complete re-config. |
| 4137 | * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) |
| 4138 | */ |
| 4139 | if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) |
| 4140 | link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; |
| 4141 | else |
| 4142 | link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; |
| 4143 | |
| 4144 | WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | |
| 4145 | RADEON_PCIE_LC_RECONFIG_NOW)); |
| 4146 | |
| 4147 | if (rdev->family >= CHIP_RV770) |
| 4148 | target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; |
| 4149 | else |
| 4150 | target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; |
| 4151 | |
| 4152 | /* wait for lane set to complete */ |
| 4153 | link_width_cntl = RREG32(target_reg); |
| 4154 | while (link_width_cntl == 0xffffffff) |
| 4155 | link_width_cntl = RREG32(target_reg); |
| 4156 | |
| 4157 | } |
| 4158 | |
| 4159 | int r600_get_pcie_lanes(struct radeon_device *rdev) |
| 4160 | { |
| 4161 | u32 link_width_cntl; |
| 4162 | |
| 4163 | if (rdev->flags & RADEON_IS_IGP) |
| 4164 | return 0; |
| 4165 | |
| 4166 | if (!(rdev->flags & RADEON_IS_PCIE)) |
| 4167 | return 0; |
| 4168 | |
| 4169 | /* x2 cards have a special sequence */ |
| 4170 | if (ASIC_IS_X2(rdev)) |
| 4171 | return 0; |
| 4172 | |
| 4173 | /* FIXME wait for idle */ |
| 4174 | |
| 4175 | link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
| 4176 | |
| 4177 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { |
| 4178 | case RADEON_PCIE_LC_LINK_WIDTH_X0: |
| 4179 | return 0; |
| 4180 | case RADEON_PCIE_LC_LINK_WIDTH_X1: |
| 4181 | return 1; |
| 4182 | case RADEON_PCIE_LC_LINK_WIDTH_X2: |
| 4183 | return 2; |
| 4184 | case RADEON_PCIE_LC_LINK_WIDTH_X4: |
| 4185 | return 4; |
| 4186 | case RADEON_PCIE_LC_LINK_WIDTH_X8: |
| 4187 | return 8; |
| 4188 | case RADEON_PCIE_LC_LINK_WIDTH_X16: |
| 4189 | default: |
| 4190 | return 16; |
| 4191 | } |
| 4192 | } |
| 4193 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 4194 | static void r600_pcie_gen2_enable(struct radeon_device *rdev) |
| 4195 | { |
| 4196 | u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; |
| 4197 | u16 link_cntl2; |
Dave Airlie | 197bbb3 | 2012-06-27 08:35:54 +0100 | [diff] [blame] | 4198 | u32 mask; |
| 4199 | int ret; |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 4200 | |
Alex Deucher | d42dd57 | 2011-01-12 20:05:11 -0500 | [diff] [blame] | 4201 | if (radeon_pcie_gen2 == 0) |
| 4202 | return; |
| 4203 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 4204 | if (rdev->flags & RADEON_IS_IGP) |
| 4205 | return; |
| 4206 | |
| 4207 | if (!(rdev->flags & RADEON_IS_PCIE)) |
| 4208 | return; |
| 4209 | |
| 4210 | /* x2 cards have a special sequence */ |
| 4211 | if (ASIC_IS_X2(rdev)) |
| 4212 | return; |
| 4213 | |
| 4214 | /* only RV6xx+ chips are supported */ |
| 4215 | if (rdev->family <= CHIP_R600) |
| 4216 | return; |
| 4217 | |
Dave Airlie | 197bbb3 | 2012-06-27 08:35:54 +0100 | [diff] [blame] | 4218 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); |
| 4219 | if (ret != 0) |
| 4220 | return; |
| 4221 | |
| 4222 | if (!(mask & DRM_PCIE_SPEED_50)) |
| 4223 | return; |
| 4224 | |
Alex Deucher | 3691fee | 2012-10-08 17:46:27 -0400 | [diff] [blame] | 4225 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 4226 | if (speed_cntl & LC_CURRENT_DATA_RATE) { |
| 4227 | DRM_INFO("PCIE gen 2 link speeds already enabled\n"); |
| 4228 | return; |
| 4229 | } |
| 4230 | |
Dave Airlie | 197bbb3 | 2012-06-27 08:35:54 +0100 | [diff] [blame] | 4231 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
| 4232 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 4233 | /* 55 nm r6xx asics */ |
| 4234 | if ((rdev->family == CHIP_RV670) || |
| 4235 | (rdev->family == CHIP_RV620) || |
| 4236 | (rdev->family == CHIP_RV635)) { |
| 4237 | /* advertise upconfig capability */ |
| 4238 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
| 4239 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
| 4240 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 4241 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
| 4242 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
| 4243 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; |
| 4244 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | |
| 4245 | LC_RECONFIG_ARC_MISSING_ESCAPE); |
| 4246 | link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; |
| 4247 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 4248 | } else { |
| 4249 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
| 4250 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 4251 | } |
| 4252 | } |
| 4253 | |
| 4254 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 4255 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
| 4256 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
| 4257 | |
| 4258 | /* 55 nm r6xx asics */ |
| 4259 | if ((rdev->family == CHIP_RV670) || |
| 4260 | (rdev->family == CHIP_RV620) || |
| 4261 | (rdev->family == CHIP_RV635)) { |
| 4262 | WREG32(MM_CFGREGS_CNTL, 0x8); |
| 4263 | link_cntl2 = RREG32(0x4088); |
| 4264 | WREG32(MM_CFGREGS_CNTL, 0); |
| 4265 | /* not supported yet */ |
| 4266 | if (link_cntl2 & SELECTABLE_DEEMPHASIS) |
| 4267 | return; |
| 4268 | } |
| 4269 | |
| 4270 | speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; |
| 4271 | speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); |
| 4272 | speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; |
| 4273 | speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; |
| 4274 | speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; |
| 4275 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 4276 | |
| 4277 | tmp = RREG32(0x541c); |
| 4278 | WREG32(0x541c, tmp | 0x8); |
| 4279 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); |
| 4280 | link_cntl2 = RREG16(0x4088); |
| 4281 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; |
| 4282 | link_cntl2 |= 0x2; |
| 4283 | WREG16(0x4088, link_cntl2); |
| 4284 | WREG32(MM_CFGREGS_CNTL, 0); |
| 4285 | |
| 4286 | if ((rdev->family == CHIP_RV670) || |
| 4287 | (rdev->family == CHIP_RV620) || |
| 4288 | (rdev->family == CHIP_RV635)) { |
| 4289 | training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); |
| 4290 | training_cntl &= ~LC_POINT_7_PLUS_EN; |
| 4291 | WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); |
| 4292 | } else { |
| 4293 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 4294 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
| 4295 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 4296 | } |
| 4297 | |
| 4298 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 4299 | speed_cntl |= LC_GEN2_EN_STRAP; |
| 4300 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 4301 | |
| 4302 | } else { |
| 4303 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
| 4304 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
| 4305 | if (1) |
| 4306 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
| 4307 | else |
| 4308 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
| 4309 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 4310 | } |
| 4311 | } |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 4312 | |
| 4313 | /** |
| 4314 | * r600_get_gpu_clock - return GPU clock counter snapshot |
| 4315 | * |
| 4316 | * @rdev: radeon_device pointer |
| 4317 | * |
| 4318 | * Fetches a GPU clock counter snapshot (R6xx-cayman). |
| 4319 | * Returns the 64 bit clock counter snapshot. |
| 4320 | */ |
| 4321 | uint64_t r600_get_gpu_clock(struct radeon_device *rdev) |
| 4322 | { |
| 4323 | uint64_t clock; |
| 4324 | |
| 4325 | mutex_lock(&rdev->gpu_clock_mutex); |
| 4326 | WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); |
| 4327 | clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | |
| 4328 | ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); |
| 4329 | mutex_unlock(&rdev->gpu_clock_mutex); |
| 4330 | return clock; |
| 4331 | } |