blob: b217c22ff72fe9a2284f59f8c1cd62aca58680aa [file] [log] [blame]
Feng Tange24c7452009-12-14 14:20:22 -08001/*
Grant Likelyca632f52011-06-06 01:16:30 -06002 * Designware SPI core controller driver (refer pxa2xx_spi.c)
Feng Tange24c7452009-12-14 14:20:22 -08003 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
Feng Tange24c7452009-12-14 14:20:22 -080014 */
15
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040018#include <linux/module.h>
Feng Tange24c7452009-12-14 14:20:22 -080019#include <linux/highmem.h>
20#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Feng Tange24c7452009-12-14 14:20:22 -080022#include <linux/spi/spi.h>
Baruch Siachd9c73bb2014-01-31 12:07:47 +020023#include <linux/gpio.h>
Feng Tange24c7452009-12-14 14:20:22 -080024
Grant Likelyca632f52011-06-06 01:16:30 -060025#include "spi-dw.h"
Grant Likely568a60e2011-02-28 12:47:12 -070026
Feng Tange24c7452009-12-14 14:20:22 -080027#ifdef CONFIG_DEBUG_FS
28#include <linux/debugfs.h>
29#endif
30
Feng Tange24c7452009-12-14 14:20:22 -080031/* Slave spi_dev related */
32struct chip_data {
Feng Tange24c7452009-12-14 14:20:22 -080033 u8 cs; /* chip select pin */
Feng Tange24c7452009-12-14 14:20:22 -080034 u8 tmode; /* TR/TO/RO/EEPROM */
35 u8 type; /* SPI/SSP/MicroWire */
36
37 u8 poll_mode; /* 1 means use poll mode */
38
Feng Tange24c7452009-12-14 14:20:22 -080039 u8 enable_dma;
Feng Tange24c7452009-12-14 14:20:22 -080040 u16 clk_div; /* baud rate divider */
41 u32 speed_hz; /* baud rate */
Feng Tange24c7452009-12-14 14:20:22 -080042 void (*cs_control)(u32 command);
43};
44
45#ifdef CONFIG_DEBUG_FS
Feng Tange24c7452009-12-14 14:20:22 -080046#define SPI_REGS_BUFSIZE 1024
Andy Shevchenko53288fe2014-09-12 15:11:56 +030047static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
48 size_t count, loff_t *ppos)
Feng Tange24c7452009-12-14 14:20:22 -080049{
Andy Shevchenko53288fe2014-09-12 15:11:56 +030050 struct dw_spi *dws = file->private_data;
Feng Tange24c7452009-12-14 14:20:22 -080051 char *buf;
52 u32 len = 0;
53 ssize_t ret;
54
Feng Tange24c7452009-12-14 14:20:22 -080055 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
56 if (!buf)
57 return 0;
58
59 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
Andy Shevchenko53288fe2014-09-12 15:11:56 +030060 "%s registers:\n", dev_name(&dws->master->dev));
Feng Tange24c7452009-12-14 14:20:22 -080061 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
62 "=================================\n");
63 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070064 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
Feng Tange24c7452009-12-14 14:20:22 -080065 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070066 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
Feng Tange24c7452009-12-14 14:20:22 -080067 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070068 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
Feng Tange24c7452009-12-14 14:20:22 -080069 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070070 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
Feng Tange24c7452009-12-14 14:20:22 -080071 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070072 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
Feng Tange24c7452009-12-14 14:20:22 -080073 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070074 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080075 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070076 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080077 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070078 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080079 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070080 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080081 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070082 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
Feng Tange24c7452009-12-14 14:20:22 -080083 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070084 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
Feng Tange24c7452009-12-14 14:20:22 -080085 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070086 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
Feng Tange24c7452009-12-14 14:20:22 -080087 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070088 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
Feng Tange24c7452009-12-14 14:20:22 -080089 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070090 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
Feng Tange24c7452009-12-14 14:20:22 -080091 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070092 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
Feng Tange24c7452009-12-14 14:20:22 -080093 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "=================================\n");
95
Andy Shevchenko53288fe2014-09-12 15:11:56 +030096 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
Feng Tange24c7452009-12-14 14:20:22 -080097 kfree(buf);
98 return ret;
99}
100
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300101static const struct file_operations dw_spi_regs_ops = {
Feng Tange24c7452009-12-14 14:20:22 -0800102 .owner = THIS_MODULE,
Stephen Boyd234e3402012-04-05 14:25:11 -0700103 .open = simple_open,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300104 .read = dw_spi_show_regs,
Arnd Bergmann6038f372010-08-15 18:52:59 +0200105 .llseek = default_llseek,
Feng Tange24c7452009-12-14 14:20:22 -0800106};
107
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300108static int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800109{
Phil Reide70002c2017-01-06 17:35:13 +0800110 char name[32];
Phil Reid13288bd2016-12-22 17:18:12 +0800111
Phil Reide70002c2017-01-06 17:35:13 +0800112 snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
Phil Reid13288bd2016-12-22 17:18:12 +0800113 dws->debugfs = debugfs_create_dir(name, NULL);
Feng Tange24c7452009-12-14 14:20:22 -0800114 if (!dws->debugfs)
115 return -ENOMEM;
116
117 debugfs_create_file("registers", S_IFREG | S_IRUGO,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300118 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
Feng Tange24c7452009-12-14 14:20:22 -0800119 return 0;
120}
121
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300122static void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800123{
Jingoo Hanfadcace2014-09-02 11:49:24 +0900124 debugfs_remove_recursive(dws->debugfs);
Feng Tange24c7452009-12-14 14:20:22 -0800125}
126
127#else
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300128static inline int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800129{
George Shore20a588f2010-01-21 11:40:49 +0000130 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800131}
132
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300133static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800134{
135}
136#endif /* CONFIG_DEBUG_FS */
137
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200138static void dw_spi_set_cs(struct spi_device *spi, bool enable)
139{
140 struct dw_spi *dws = spi_master_get_devdata(spi->master);
141 struct chip_data *chip = spi_get_ctldata(spi);
142
143 /* Chip select logic is inverted from spi_set_cs() */
Andy Shevchenko207cda92015-03-25 20:26:26 +0200144 if (chip && chip->cs_control)
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200145 chip->cs_control(!enable);
146
147 if (!enable)
148 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
149}
150
Alek Du2ff271b2011-03-30 23:09:54 +0800151/* Return the max entries we can fill into tx fifo */
152static inline u32 tx_max(struct dw_spi *dws)
153{
154 u32 tx_left, tx_room, rxtx_gap;
155
156 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
Thor Thayerdd114442015-03-12 14:19:31 -0500157 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
Alek Du2ff271b2011-03-30 23:09:54 +0800158
159 /*
160 * Another concern is about the tx/rx mismatch, we
161 * though to use (dws->fifo_len - rxflr - txflr) as
162 * one maximum value for tx, but it doesn't cover the
163 * data which is out of tx/rx fifo and inside the
164 * shift registers. So a control from sw point of
165 * view is taken.
166 */
167 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
168 / dws->n_bytes;
169
170 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
171}
172
173/* Return the max entries we should read out of rx fifo */
174static inline u32 rx_max(struct dw_spi *dws)
175{
176 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
177
Thor Thayerdd114442015-03-12 14:19:31 -0500178 return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
Alek Du2ff271b2011-03-30 23:09:54 +0800179}
180
Alek Du3b8a4dd2011-03-30 23:09:55 +0800181static void dw_writer(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800182{
Alek Du2ff271b2011-03-30 23:09:54 +0800183 u32 max = tx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800184 u16 txw = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800185
Alek Du2ff271b2011-03-30 23:09:54 +0800186 while (max--) {
187 /* Set the tx word if the transfer's original "tx" is not null */
188 if (dws->tx_end - dws->len) {
189 if (dws->n_bytes == 1)
190 txw = *(u8 *)(dws->tx);
191 else
192 txw = *(u16 *)(dws->tx);
193 }
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200194 dw_write_io_reg(dws, DW_SPI_DR, txw);
Alek Du2ff271b2011-03-30 23:09:54 +0800195 dws->tx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800196 }
Feng Tange24c7452009-12-14 14:20:22 -0800197}
198
Alek Du3b8a4dd2011-03-30 23:09:55 +0800199static void dw_reader(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800200{
Alek Du2ff271b2011-03-30 23:09:54 +0800201 u32 max = rx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800202 u16 rxw;
Feng Tange24c7452009-12-14 14:20:22 -0800203
Alek Du2ff271b2011-03-30 23:09:54 +0800204 while (max--) {
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200205 rxw = dw_read_io_reg(dws, DW_SPI_DR);
Feng Tangde6efe02011-03-30 23:09:52 +0800206 /* Care rx only if the transfer's original "rx" is not null */
207 if (dws->rx_end - dws->len) {
208 if (dws->n_bytes == 1)
209 *(u8 *)(dws->rx) = rxw;
210 else
211 *(u16 *)(dws->rx) = rxw;
212 }
213 dws->rx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800214 }
Feng Tange24c7452009-12-14 14:20:22 -0800215}
216
Feng Tange24c7452009-12-14 14:20:22 -0800217static void int_error_stop(struct dw_spi *dws, const char *msg)
218{
Andy Shevchenko45746e82015-03-02 14:58:55 +0200219 spi_reset_chip(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800220
221 dev_err(&dws->master->dev, "%s\n", msg);
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200222 dws->master->cur_msg->status = -EIO;
223 spi_finalize_current_transfer(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800224}
225
Feng Tange24c7452009-12-14 14:20:22 -0800226static irqreturn_t interrupt_transfer(struct dw_spi *dws)
227{
Thor Thayerdd114442015-03-12 14:19:31 -0500228 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
Feng Tange24c7452009-12-14 14:20:22 -0800229
Feng Tange24c7452009-12-14 14:20:22 -0800230 /* Error handling */
231 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
Thor Thayerdd114442015-03-12 14:19:31 -0500232 dw_readl(dws, DW_SPI_ICR);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800233 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
Feng Tange24c7452009-12-14 14:20:22 -0800234 return IRQ_HANDLED;
235 }
236
Alek Du3b8a4dd2011-03-30 23:09:55 +0800237 dw_reader(dws);
238 if (dws->rx_end == dws->rx) {
239 spi_mask_intr(dws, SPI_INT_TXEI);
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200240 spi_finalize_current_transfer(dws->master);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800241 return IRQ_HANDLED;
242 }
Feng Tang552e4502010-01-20 13:49:45 -0700243 if (irq_status & SPI_INT_TXEI) {
244 spi_mask_intr(dws, SPI_INT_TXEI);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800245 dw_writer(dws);
246 /* Enable TX irq always, it will be disabled when RX finished */
247 spi_umask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800248 }
Feng Tang552e4502010-01-20 13:49:45 -0700249
Feng Tange24c7452009-12-14 14:20:22 -0800250 return IRQ_HANDLED;
251}
252
253static irqreturn_t dw_spi_irq(int irq, void *dev_id)
254{
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200255 struct spi_master *master = dev_id;
256 struct dw_spi *dws = spi_master_get_devdata(master);
Thor Thayerdd114442015-03-12 14:19:31 -0500257 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
Yong Wangcbcc0622010-09-07 15:27:27 +0800258
Yong Wangcbcc0622010-09-07 15:27:27 +0800259 if (!irq_status)
260 return IRQ_NONE;
Feng Tange24c7452009-12-14 14:20:22 -0800261
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200262 if (!master->cur_msg) {
Feng Tange24c7452009-12-14 14:20:22 -0800263 spi_mask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800264 return IRQ_HANDLED;
265 }
266
267 return dws->transfer_handler(dws);
268}
269
270/* Must be called inside pump_transfers() */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200271static int poll_transfer(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800272{
Alek Du2ff271b2011-03-30 23:09:54 +0800273 do {
274 dw_writer(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800275 dw_reader(dws);
Alek Du2ff271b2011-03-30 23:09:54 +0800276 cpu_relax();
277 } while (dws->rx_end > dws->rx);
Feng Tange24c7452009-12-14 14:20:22 -0800278
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200279 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800280}
281
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200282static int dw_spi_transfer_one(struct spi_master *master,
283 struct spi_device *spi, struct spi_transfer *transfer)
Feng Tange24c7452009-12-14 14:20:22 -0800284{
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200285 struct dw_spi *dws = spi_master_get_devdata(master);
286 struct chip_data *chip = spi_get_ctldata(spi);
Feng Tange24c7452009-12-14 14:20:22 -0800287 u8 imask = 0;
Andy Shevchenkoea113702015-02-24 13:32:11 +0200288 u16 txlevel = 0;
Andy Shevchenko4adb1f82015-10-14 23:12:18 +0300289 u32 cr0;
Andy Shevchenko9f145382015-03-09 16:48:46 +0200290 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800291
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200292 dws->dma_mapped = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800293
Feng Tange24c7452009-12-14 14:20:22 -0800294 dws->tx = (void *)transfer->tx_buf;
295 dws->tx_end = dws->tx + transfer->len;
296 dws->rx = transfer->rx_buf;
297 dws->rx_end = dws->rx + transfer->len;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200298 dws->len = transfer->len;
Feng Tange24c7452009-12-14 14:20:22 -0800299
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200300 spi_enable_chip(dws, 0);
301
Feng Tange24c7452009-12-14 14:20:22 -0800302 /* Handle per transfer options for bpw and speed */
Matthias Seidel13b10302016-09-04 02:04:49 +0200303 if (transfer->speed_hz != dws->current_freq) {
304 if (transfer->speed_hz != chip->speed_hz) {
305 /* clk_div doesn't support odd number */
Matthias Seidel3aef4632016-09-07 17:45:30 +0200306 chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
Matthias Seidel13b10302016-09-04 02:04:49 +0200307 chip->speed_hz = transfer->speed_hz;
308 }
309 dws->current_freq = transfer->speed_hz;
Jarkko Nikula0ed36992015-09-15 16:26:23 +0300310 spi_set_clk(dws, chip->clk_div);
Feng Tange24c7452009-12-14 14:20:22 -0800311 }
Jarkko Nikula0ed36992015-09-15 16:26:23 +0300312 if (transfer->bits_per_word == 8) {
313 dws->n_bytes = 1;
314 dws->dma_width = 1;
315 } else if (transfer->bits_per_word == 16) {
316 dws->n_bytes = 2;
317 dws->dma_width = 2;
Andy Shevchenko863cb2f2015-10-14 23:12:20 +0300318 } else {
319 return -EINVAL;
Feng Tange24c7452009-12-14 14:20:22 -0800320 }
Andy Shevchenko4adb1f82015-10-14 23:12:18 +0300321 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
Jarkko Nikula0ed36992015-09-15 16:26:23 +0300322 cr0 = (transfer->bits_per_word - 1)
323 | (chip->type << SPI_FRF_OFFSET)
324 | (spi->mode << SPI_MODE_OFFSET)
325 | (chip->tmode << SPI_TMOD_OFFSET);
Feng Tange24c7452009-12-14 14:20:22 -0800326
George Shore052dc7c2010-01-21 11:40:52 +0000327 /*
328 * Adjust transfer mode if necessary. Requires platform dependent
329 * chipselect mechanism.
330 */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200331 if (chip->cs_control) {
George Shore052dc7c2010-01-21 11:40:52 +0000332 if (dws->rx && dws->tx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800333 chip->tmode = SPI_TMOD_TR;
George Shore052dc7c2010-01-21 11:40:52 +0000334 else if (dws->rx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800335 chip->tmode = SPI_TMOD_RO;
George Shore052dc7c2010-01-21 11:40:52 +0000336 else
Feng Tange3e55ff2010-09-07 15:52:06 +0800337 chip->tmode = SPI_TMOD_TO;
George Shore052dc7c2010-01-21 11:40:52 +0000338
Feng Tange3e55ff2010-09-07 15:52:06 +0800339 cr0 &= ~SPI_TMOD_MASK;
George Shore052dc7c2010-01-21 11:40:52 +0000340 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
341 }
342
Thor Thayerdd114442015-03-12 14:19:31 -0500343 dw_writel(dws, DW_SPI_CTRL0, cr0);
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200344
Feng Tange24c7452009-12-14 14:20:22 -0800345 /* Check if current transfer is a DMA transaction */
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200346 if (master->can_dma && master->can_dma(master, spi, transfer))
347 dws->dma_mapped = master->cur_msg_mapped;
Feng Tange24c7452009-12-14 14:20:22 -0800348
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200349 /* For poll mode just disable all interrupts */
350 spi_mask_intr(dws, 0xff);
351
Feng Tang552e4502010-01-20 13:49:45 -0700352 /*
353 * Interrupt mode
354 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
355 */
Andy Shevchenko9f145382015-03-09 16:48:46 +0200356 if (dws->dma_mapped) {
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200357 ret = dws->dma_ops->dma_setup(dws, transfer);
Andy Shevchenko9f145382015-03-09 16:48:46 +0200358 if (ret < 0) {
359 spi_enable_chip(dws, 1);
360 return ret;
361 }
362 } else if (!chip->poll_mode) {
Andy Shevchenkoea113702015-02-24 13:32:11 +0200363 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
Thor Thayerdd114442015-03-12 14:19:31 -0500364 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
Feng Tang552e4502010-01-20 13:49:45 -0700365
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200366 /* Set the interrupt mask */
Jingoo Hanfadcace2014-09-02 11:49:24 +0900367 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
368 SPI_INT_RXUI | SPI_INT_RXOI;
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200369 spi_umask_intr(dws, imask);
370
Feng Tange24c7452009-12-14 14:20:22 -0800371 dws->transfer_handler = interrupt_transfer;
372 }
373
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200374 spi_enable_chip(dws, 1);
Feng Tange24c7452009-12-14 14:20:22 -0800375
Andy Shevchenko9f145382015-03-09 16:48:46 +0200376 if (dws->dma_mapped) {
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200377 ret = dws->dma_ops->dma_transfer(dws, transfer);
Andy Shevchenko9f145382015-03-09 16:48:46 +0200378 if (ret < 0)
379 return ret;
380 }
Feng Tange24c7452009-12-14 14:20:22 -0800381
382 if (chip->poll_mode)
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200383 return poll_transfer(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800384
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200385 return 1;
Feng Tange24c7452009-12-14 14:20:22 -0800386}
387
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200388static void dw_spi_handle_err(struct spi_master *master,
Baruch Siachec37e8e2014-01-31 12:07:44 +0200389 struct spi_message *msg)
Feng Tange24c7452009-12-14 14:20:22 -0800390{
Baruch Siachec37e8e2014-01-31 12:07:44 +0200391 struct dw_spi *dws = spi_master_get_devdata(master);
Feng Tange24c7452009-12-14 14:20:22 -0800392
Andy Shevchenko4d5ac1e2015-03-09 16:48:48 +0200393 if (dws->dma_mapped)
394 dws->dma_ops->dma_stop(dws);
395
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200396 spi_reset_chip(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800397}
398
399/* This may be called twice for each spi dev */
400static int dw_spi_setup(struct spi_device *spi)
401{
402 struct dw_spi_chip *chip_info = NULL;
403 struct chip_data *chip;
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200404 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800405
Feng Tange24c7452009-12-14 14:20:22 -0800406 /* Only alloc on first setup */
407 chip = spi_get_ctldata(spi);
408 if (!chip) {
Axel Lina97c8832014-08-31 12:47:06 +0800409 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
Feng Tange24c7452009-12-14 14:20:22 -0800410 if (!chip)
411 return -ENOMEM;
Baruch Siach43f627a2013-12-30 20:30:46 +0200412 spi_set_ctldata(spi, chip);
Feng Tange24c7452009-12-14 14:20:22 -0800413 }
414
415 /*
416 * Protocol drivers may change the chip settings, so...
417 * if chip_info exists, use it
418 */
419 chip_info = spi->controller_data;
420
421 /* chip_info doesn't always exist */
422 if (chip_info) {
423 if (chip_info->cs_control)
424 chip->cs_control = chip_info->cs_control;
425
426 chip->poll_mode = chip_info->poll_mode;
427 chip->type = chip_info->type;
Feng Tange24c7452009-12-14 14:20:22 -0800428 }
429
Jisheng Zhang60968282015-12-23 19:05:39 +0800430 chip->tmode = SPI_TMOD_TR;
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300431
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200432 if (gpio_is_valid(spi->cs_gpio)) {
433 ret = gpio_direction_output(spi->cs_gpio,
434 !(spi->mode & SPI_CS_HIGH));
435 if (ret)
436 return ret;
437 }
438
Feng Tange24c7452009-12-14 14:20:22 -0800439 return 0;
440}
441
Axel Lina97c8832014-08-31 12:47:06 +0800442static void dw_spi_cleanup(struct spi_device *spi)
443{
444 struct chip_data *chip = spi_get_ctldata(spi);
445
446 kfree(chip);
447 spi_set_ctldata(spi, NULL);
448}
449
Feng Tange24c7452009-12-14 14:20:22 -0800450/* Restart the controller, disable all interrupts, clean rx fifo */
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200451static void spi_hw_init(struct device *dev, struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800452{
Andy Shevchenko45746e82015-03-02 14:58:55 +0200453 spi_reset_chip(dws);
Feng Tangc587b6f2010-01-21 10:41:10 +0800454
455 /*
456 * Try to detect the FIFO depth if not set by interface driver,
457 * the depth could be from 2 to 256 from HW spec
458 */
459 if (!dws->fifo_len) {
460 u32 fifo;
Jingoo Hanfadcace2014-09-02 11:49:24 +0900461
Andy Shevchenko9d239d32015-02-25 11:39:36 +0200462 for (fifo = 1; fifo < 256; fifo++) {
Thor Thayerdd114442015-03-12 14:19:31 -0500463 dw_writel(dws, DW_SPI_TXFLTR, fifo);
464 if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
Feng Tangc587b6f2010-01-21 10:41:10 +0800465 break;
466 }
Thor Thayerdd114442015-03-12 14:19:31 -0500467 dw_writel(dws, DW_SPI_TXFLTR, 0);
Feng Tangc587b6f2010-01-21 10:41:10 +0800468
Andy Shevchenko9d239d32015-02-25 11:39:36 +0200469 dws->fifo_len = (fifo == 1) ? 0 : fifo;
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200470 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
Feng Tangc587b6f2010-01-21 10:41:10 +0800471 }
Feng Tange24c7452009-12-14 14:20:22 -0800472}
473
Baruch Siach04f421e2013-12-30 20:30:44 +0200474int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800475{
476 struct spi_master *master;
477 int ret;
478
479 BUG_ON(dws == NULL);
480
Baruch Siach04f421e2013-12-30 20:30:44 +0200481 master = spi_alloc_master(dev, 0);
482 if (!master)
483 return -ENOMEM;
Feng Tange24c7452009-12-14 14:20:22 -0800484
485 dws->master = master;
486 dws->type = SSI_MOTO_SPI;
Feng Tange24c7452009-12-14 14:20:22 -0800487 dws->dma_inited = 0;
Andy Shevchenkod7ef54c2015-10-27 17:48:16 +0200488 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
Feng Tange24c7452009-12-14 14:20:22 -0800489
Phil Reide70002c2017-01-06 17:35:13 +0800490 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
491 master);
Feng Tange24c7452009-12-14 14:20:22 -0800492 if (ret < 0) {
Andy Shevchenko5f0966e2015-10-14 23:12:17 +0300493 dev_err(dev, "can not get IRQ\n");
Feng Tange24c7452009-12-14 14:20:22 -0800494 goto err_free_master;
495 }
496
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300497 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
Stephen Warren24778be2013-05-21 20:36:35 -0600498 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
Feng Tange24c7452009-12-14 14:20:22 -0800499 master->bus_num = dws->bus_num;
500 master->num_chipselect = dws->num_cs;
Feng Tange24c7452009-12-14 14:20:22 -0800501 master->setup = dw_spi_setup;
Axel Lina97c8832014-08-31 12:47:06 +0800502 master->cleanup = dw_spi_cleanup;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200503 master->set_cs = dw_spi_set_cs;
504 master->transfer_one = dw_spi_transfer_one;
505 master->handle_err = dw_spi_handle_err;
Axel Lin765ee702014-02-20 21:37:56 +0800506 master->max_speed_hz = dws->max_freq;
Thor Thayer9c6de472014-10-08 13:51:34 -0500507 master->dev.of_node = dev->of_node;
Thor Thayer80b444e2016-10-10 09:25:25 -0500508 master->flags = SPI_MASTER_GPIO_SS;
Feng Tange24c7452009-12-14 14:20:22 -0800509
Feng Tange24c7452009-12-14 14:20:22 -0800510 /* Basic HW init */
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200511 spi_hw_init(dev, dws);
Feng Tange24c7452009-12-14 14:20:22 -0800512
Feng Tang7063c0d2010-12-24 13:59:11 +0800513 if (dws->dma_ops && dws->dma_ops->dma_init) {
514 ret = dws->dma_ops->dma_init(dws);
515 if (ret) {
Andy Shevchenko3dbb3b92015-01-07 16:56:54 +0200516 dev_warn(dev, "DMA init failed\n");
Feng Tang7063c0d2010-12-24 13:59:11 +0800517 dws->dma_inited = 0;
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200518 } else {
519 master->can_dma = dws->dma_ops->can_dma;
Feng Tang7063c0d2010-12-24 13:59:11 +0800520 }
521 }
522
Feng Tange24c7452009-12-14 14:20:22 -0800523 spi_master_set_devdata(master, dws);
Baruch Siach04f421e2013-12-30 20:30:44 +0200524 ret = devm_spi_register_master(dev, master);
Feng Tange24c7452009-12-14 14:20:22 -0800525 if (ret) {
526 dev_err(&master->dev, "problem registering spi master\n");
Baruch Siachec37e8e2014-01-31 12:07:44 +0200527 goto err_dma_exit;
Feng Tange24c7452009-12-14 14:20:22 -0800528 }
529
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300530 dw_spi_debugfs_init(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800531 return 0;
532
Baruch Siachec37e8e2014-01-31 12:07:44 +0200533err_dma_exit:
Feng Tang7063c0d2010-12-24 13:59:11 +0800534 if (dws->dma_ops && dws->dma_ops->dma_exit)
535 dws->dma_ops->dma_exit(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800536 spi_enable_chip(dws, 0);
Andy Shevchenko02f20382015-10-20 12:11:40 +0300537 free_irq(dws->irq, master);
Feng Tange24c7452009-12-14 14:20:22 -0800538err_free_master:
539 spi_master_put(master);
Feng Tange24c7452009-12-14 14:20:22 -0800540 return ret;
541}
Feng Tang79290a22010-12-24 13:59:10 +0800542EXPORT_SYMBOL_GPL(dw_spi_add_host);
Feng Tange24c7452009-12-14 14:20:22 -0800543
Grant Likelyfd4a3192012-12-07 16:57:14 +0000544void dw_spi_remove_host(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800545{
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300546 dw_spi_debugfs_remove(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800547
Feng Tang7063c0d2010-12-24 13:59:11 +0800548 if (dws->dma_ops && dws->dma_ops->dma_exit)
549 dws->dma_ops->dma_exit(dws);
Andy Shevchenko1cc3f142015-10-14 23:12:23 +0300550
551 spi_shutdown_chip(dws);
Andy Shevchenko02f20382015-10-20 12:11:40 +0300552
553 free_irq(dws->irq, dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800554}
Feng Tang79290a22010-12-24 13:59:10 +0800555EXPORT_SYMBOL_GPL(dw_spi_remove_host);
Feng Tange24c7452009-12-14 14:20:22 -0800556
557int dw_spi_suspend_host(struct dw_spi *dws)
558{
Andy Shevchenko1cc3f142015-10-14 23:12:23 +0300559 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800560
Baruch Siachec37e8e2014-01-31 12:07:44 +0200561 ret = spi_master_suspend(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800562 if (ret)
563 return ret;
Andy Shevchenko1cc3f142015-10-14 23:12:23 +0300564
565 spi_shutdown_chip(dws);
566 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800567}
Feng Tang79290a22010-12-24 13:59:10 +0800568EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
Feng Tange24c7452009-12-14 14:20:22 -0800569
570int dw_spi_resume_host(struct dw_spi *dws)
571{
572 int ret;
573
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200574 spi_hw_init(&dws->master->dev, dws);
Baruch Siachec37e8e2014-01-31 12:07:44 +0200575 ret = spi_master_resume(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800576 if (ret)
577 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
578 return ret;
579}
Feng Tang79290a22010-12-24 13:59:10 +0800580EXPORT_SYMBOL_GPL(dw_spi_resume_host);
Feng Tange24c7452009-12-14 14:20:22 -0800581
582MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
583MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
584MODULE_LICENSE("GPL v2");