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Shawn Guo73d2b4c2011-10-17 08:42:16 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +080013#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +080014#include "imx53-pinfunc.h"
Lucas Stach564695d2013-11-14 11:18:58 +010015#include <dt-bindings/clock/imx5-clock.h>
Denis Carikli4e05a7a2014-01-06 17:16:07 +010016#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
Shawn Guo73d2b4c2011-10-17 08:42:16 +080018
19/ {
20 aliases {
Marek Vasut22970072014-02-28 12:58:41 +010021 ethernet0 = &fec;
Shawn Guo5230f8f2012-08-05 14:01:28 +080022 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Philipp Zabelc60dc1d2013-04-09 19:18:47 +020029 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
Sascha Hauerc63d06d2014-01-16 13:44:18 +010032 mmc0 = &esdhc1;
33 mmc1 = &esdhc2;
34 mmc2 = &esdhc3;
35 mmc3 = &esdhc4;
Sascha Hauercf4e5772013-06-25 15:51:56 +020036 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 serial4 = &uart5;
41 spi0 = &ecspi1;
42 spi1 = &ecspi2;
43 spi2 = &cspi;
Shawn Guo73d2b4c2011-10-17 08:42:16 +080044 };
45
Fabio Estevam070bd7e2013-07-07 10:12:30 -030046 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49 cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a8";
52 reg = <0x0>;
53 };
54 };
55
Philipp Zabele05c8c92014-03-05 10:21:00 +010056 display-subsystem {
57 compatible = "fsl,imx-display-subsystem";
58 ports = <&ipu_di0>, <&ipu_di1>;
59 };
60
Shawn Guo73d2b4c2011-10-17 08:42:16 +080061 tzic: tz-interrupt-controller@0fffc000 {
62 compatible = "fsl,imx53-tzic", "fsl,tzic";
63 interrupt-controller;
64 #interrupt-cells = <1>;
65 reg = <0x0fffc000 0x4000>;
66 };
67
68 clocks {
69 #address-cells = <1>;
70 #size-cells = <0>;
71
72 ckil {
73 compatible = "fsl,imx-ckil", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +080074 #clock-cells = <0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +080075 clock-frequency = <32768>;
76 };
77
78 ckih1 {
79 compatible = "fsl,imx-ckih1", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +080080 #clock-cells = <0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +080081 clock-frequency = <22579200>;
82 };
83
84 ckih2 {
85 compatible = "fsl,imx-ckih2", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +080086 #clock-cells = <0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +080087 clock-frequency = <0>;
88 };
89
90 osc {
91 compatible = "fsl,imx-osc", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +080092 #clock-cells = <0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +080093 clock-frequency = <24000000>;
94 };
95 };
96
97 soc {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 compatible = "simple-bus";
101 interrupt-parent = <&tzic>;
102 ranges;
103
Marek Vasut7affee42013-11-22 12:05:03 +0100104 sata: sata@10000000 {
105 compatible = "fsl,imx53-ahci";
106 reg = <0x10000000 0x1000>;
107 interrupts = <28>;
108 clocks = <&clks IMX5_CLK_SATA_GATE>,
109 <&clks IMX5_CLK_SATA_REF>,
110 <&clks IMX5_CLK_AHB>;
Shawn Guo02578152014-07-08 16:14:47 +0800111 clock-names = "sata", "sata_ref", "ahb";
Marek Vasut7affee42013-11-22 12:05:03 +0100112 status = "disabled";
113 };
114
Sascha Hauerabed9a62012-06-05 13:52:10 +0200115 ipu: ipu@18000000 {
Philipp Zabele05c8c92014-03-05 10:21:00 +0100116 #address-cells = <1>;
117 #size-cells = <0>;
Sascha Hauerabed9a62012-06-05 13:52:10 +0200118 compatible = "fsl,imx53-ipu";
Sascha Hauer6d66da82014-05-06 13:01:34 +0200119 reg = <0x18000000 0x08000000>;
Sascha Hauerabed9a62012-06-05 13:52:10 +0200120 interrupts = <11 10>;
Lucas Stach564695d2013-11-14 11:18:58 +0100121 clocks = <&clks IMX5_CLK_IPU_GATE>,
122 <&clks IMX5_CLK_IPU_DI0_GATE>,
123 <&clks IMX5_CLK_IPU_DI1_GATE>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100124 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100125 resets = <&src 2>;
Philipp Zabele05c8c92014-03-05 10:21:00 +0100126
127 ipu_di0: port@2 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reg = <2>;
131
132 ipu_di0_disp0: endpoint@0 {
133 reg = <0>;
134 };
135
136 ipu_di0_lvds0: endpoint@1 {
137 reg = <1>;
138 remote-endpoint = <&lvds0_in>;
139 };
140 };
141
142 ipu_di1: port@3 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 reg = <3>;
146
147 ipu_di1_disp1: endpoint@0 {
148 reg = <0>;
149 };
150
151 ipu_di1_lvds1: endpoint@1 {
152 reg = <1>;
153 remote-endpoint = <&lvds1_in>;
154 };
155
156 ipu_di1_tve: endpoint@2 {
157 reg = <2>;
158 remote-endpoint = <&tve_in>;
159 };
160 };
Sascha Hauerabed9a62012-06-05 13:52:10 +0200161 };
162
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800163 aips@50000000 { /* AIPS1 */
164 compatible = "fsl,aips-bus", "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 reg = <0x50000000 0x10000000>;
168 ranges;
169
170 spba@50000000 {
171 compatible = "fsl,spba-bus", "simple-bus";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0x50000000 0x40000>;
175 ranges;
176
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100177 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800178 compatible = "fsl,imx53-esdhc";
179 reg = <0x50004000 0x4000>;
180 interrupts = <1>;
Lucas Stach564695d2013-11-14 11:18:58 +0100181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 <&clks IMX5_CLK_DUMMY>,
183 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200184 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200185 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800186 status = "disabled";
187 };
188
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100189 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800190 compatible = "fsl,imx53-esdhc";
191 reg = <0x50008000 0x4000>;
192 interrupts = <2>;
Lucas Stach564695d2013-11-14 11:18:58 +0100193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200196 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200197 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800198 status = "disabled";
199 };
200
Shawn Guo0c456cf2012-04-02 14:39:26 +0800201 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800202 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
203 reg = <0x5000c000 0x4000>;
204 interrupts = <33>;
Lucas Stach564695d2013-11-14 11:18:58 +0100205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 <&clks IMX5_CLK_UART3_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200207 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800208 status = "disabled";
209 };
210
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100211 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
215 reg = <0x50010000 0x4000>;
216 interrupts = <36>;
Lucas Stach564695d2013-11-14 11:18:58 +0100217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
218 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200219 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800220 status = "disabled";
221 };
222
Shawn Guoffc505c2012-05-11 13:12:01 +0800223 ssi2: ssi@50014000 {
Markus Pargmann28f93d02014-01-17 10:07:42 +0100224 compatible = "fsl,imx53-ssi",
225 "fsl,imx51-ssi",
226 "fsl,imx21-ssi";
Shawn Guoffc505c2012-05-11 13:12:01 +0800227 reg = <0x50014000 0x4000>;
228 interrupts = <30>;
Lucas Stach564695d2013-11-14 11:18:58 +0100229 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800230 dmas = <&sdma 24 1 0>,
231 <&sdma 25 1 0>;
232 dma-names = "rx", "tx";
Shawn Guoffc505c2012-05-11 13:12:01 +0800233 fsl,fifo-depth = <15>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800234 status = "disabled";
235 };
236
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100237 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800238 compatible = "fsl,imx53-esdhc";
239 reg = <0x50020000 0x4000>;
240 interrupts = <3>;
Lucas Stach564695d2013-11-14 11:18:58 +0100241 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
242 <&clks IMX5_CLK_DUMMY>,
243 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200244 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200245 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800246 status = "disabled";
247 };
248
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100249 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800250 compatible = "fsl,imx53-esdhc";
251 reg = <0x50024000 0x4000>;
252 interrupts = <4>;
Lucas Stach564695d2013-11-14 11:18:58 +0100253 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
254 <&clks IMX5_CLK_DUMMY>,
255 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200256 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200257 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800258 status = "disabled";
259 };
260 };
261
Steffen Trumtrarac082812014-06-25 13:01:30 +0200262 aipstz1: bridge@53f00000 {
263 compatible = "fsl,imx53-aipstz";
264 reg = <0x53f00000 0x60>;
265 };
266
Michael Grzeschika79025c2013-04-11 12:13:16 +0200267 usbphy0: usbphy@0 {
268 compatible = "usb-nop-xceiv";
Lucas Stach564695d2013-11-14 11:18:58 +0100269 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200270 clock-names = "main_clk";
271 status = "okay";
272 };
273
274 usbphy1: usbphy@1 {
275 compatible = "usb-nop-xceiv";
Lucas Stach564695d2013-11-14 11:18:58 +0100276 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200277 clock-names = "main_clk";
278 status = "okay";
279 };
280
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100281 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200282 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
283 reg = <0x53f80000 0x0200>;
284 interrupts = <18>;
Lucas Stach564695d2013-11-14 11:18:58 +0100285 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200286 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200287 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200288 status = "disabled";
289 };
290
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100291 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200292 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
293 reg = <0x53f80200 0x0200>;
294 interrupts = <14>;
Lucas Stach564695d2013-11-14 11:18:58 +0100295 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200296 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200297 fsl,usbphy = <&usbphy1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200298 status = "disabled";
299 };
300
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100301 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200302 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
303 reg = <0x53f80400 0x0200>;
304 interrupts = <16>;
Lucas Stach564695d2013-11-14 11:18:58 +0100305 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200306 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200307 status = "disabled";
308 };
309
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100310 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200311 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
312 reg = <0x53f80600 0x0200>;
313 interrupts = <17>;
Lucas Stach564695d2013-11-14 11:18:58 +0100314 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200315 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200316 status = "disabled";
317 };
318
Michael Grzeschika5735022013-04-11 12:13:14 +0200319 usbmisc: usbmisc@53f80800 {
320 #index-cells = <1>;
321 compatible = "fsl,imx53-usbmisc";
322 reg = <0x53f80800 0x200>;
Lucas Stach564695d2013-11-14 11:18:58 +0100323 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200324 };
325
Richard Zhao4d191862011-12-14 09:26:44 +0800326 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200327 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800328 reg = <0x53f84000 0x4000>;
329 interrupts = <50 51>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800333 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800334 };
335
Richard Zhao4d191862011-12-14 09:26:44 +0800336 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200337 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800338 reg = <0x53f88000 0x4000>;
339 interrupts = <52 53>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800343 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800344 };
345
Richard Zhao4d191862011-12-14 09:26:44 +0800346 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200347 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800348 reg = <0x53f8c000 0x4000>;
349 interrupts = <54 55>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800353 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800354 };
355
Richard Zhao4d191862011-12-14 09:26:44 +0800356 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200357 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800358 reg = <0x53f90000 0x4000>;
359 interrupts = <56 57>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800363 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800364 };
365
Rostislav Lisovy675e4d02013-10-22 19:07:21 +0200366 kpp: kpp@53f94000 {
367 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
368 reg = <0x53f94000 0x4000>;
369 interrupts = <60>;
Lucas Stach564695d2013-11-14 11:18:58 +0100370 clocks = <&clks IMX5_CLK_DUMMY>;
Rostislav Lisovy675e4d02013-10-22 19:07:21 +0200371 status = "disabled";
372 };
373
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100374 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800375 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
376 reg = <0x53f98000 0x4000>;
377 interrupts = <58>;
Lucas Stach564695d2013-11-14 11:18:58 +0100378 clocks = <&clks IMX5_CLK_DUMMY>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800379 };
380
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100381 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800382 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
383 reg = <0x53f9c000 0x4000>;
384 interrupts = <59>;
Lucas Stach564695d2013-11-14 11:18:58 +0100385 clocks = <&clks IMX5_CLK_DUMMY>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800386 status = "disabled";
387 };
388
Sascha Hauercc8aae92013-03-14 13:09:00 +0100389 gpt: timer@53fa0000 {
390 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
391 reg = <0x53fa0000 0x4000>;
392 interrupts = <39>;
Lucas Stach564695d2013-11-14 11:18:58 +0100393 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
394 <&clks IMX5_CLK_GPT_HF_GATE>;
Sascha Hauercc8aae92013-03-14 13:09:00 +0100395 clock-names = "ipg", "per";
396 };
397
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100398 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800399 compatible = "fsl,imx53-iomuxc";
400 reg = <0x53fa8000 0x4000>;
Shawn Guo5be03a72012-08-12 20:02:10 +0800401 };
402
Philipp Zabel5af9f142013-03-27 18:30:43 +0100403 gpr: iomuxc-gpr@53fa8000 {
404 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
405 reg = <0x53fa8000 0xc>;
406 };
407
Philipp Zabel420714a2013-03-27 18:30:44 +0100408 ldb: ldb@53fa8008 {
409 #address-cells = <1>;
410 #size-cells = <0>;
411 compatible = "fsl,imx53-ldb";
412 reg = <0x53fa8008 0x4>;
413 gpr = <&gpr>;
Lucas Stach564695d2013-11-14 11:18:58 +0100414 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
415 <&clks IMX5_CLK_LDB_DI1_SEL>,
416 <&clks IMX5_CLK_IPU_DI0_SEL>,
417 <&clks IMX5_CLK_IPU_DI1_SEL>,
418 <&clks IMX5_CLK_LDB_DI0_GATE>,
419 <&clks IMX5_CLK_LDB_DI1_GATE>;
Philipp Zabel420714a2013-03-27 18:30:44 +0100420 clock-names = "di0_pll", "di1_pll",
421 "di0_sel", "di1_sel",
422 "di0", "di1";
423 status = "disabled";
424
425 lvds-channel@0 {
Markus Niebel1b134c92014-09-11 15:56:56 +0800426 #address-cells = <1>;
427 #size-cells = <0>;
Philipp Zabel420714a2013-03-27 18:30:44 +0100428 reg = <0>;
Philipp Zabel420714a2013-03-27 18:30:44 +0100429 status = "disabled";
Philipp Zabele05c8c92014-03-05 10:21:00 +0100430
Markus Niebel1b134c92014-09-11 15:56:56 +0800431 port@0 {
432 reg = <0>;
433
Philipp Zabele05c8c92014-03-05 10:21:00 +0100434 lvds0_in: endpoint {
435 remote-endpoint = <&ipu_di0_lvds0>;
436 };
437 };
Philipp Zabel420714a2013-03-27 18:30:44 +0100438 };
439
440 lvds-channel@1 {
Markus Niebel1b134c92014-09-11 15:56:56 +0800441 #address-cells = <1>;
442 #size-cells = <0>;
Philipp Zabel420714a2013-03-27 18:30:44 +0100443 reg = <1>;
Philipp Zabel420714a2013-03-27 18:30:44 +0100444 status = "disabled";
Philipp Zabele05c8c92014-03-05 10:21:00 +0100445
Markus Niebel1b134c92014-09-11 15:56:56 +0800446 port@1 {
447 reg = <1>;
448
Philipp Zabele05c8c92014-03-05 10:21:00 +0100449 lvds1_in: endpoint {
Lothar Waßmannfa1746a2014-04-10 10:03:40 +0200450 remote-endpoint = <&ipu_di1_lvds1>;
Philipp Zabele05c8c92014-03-05 10:21:00 +0100451 };
452 };
Philipp Zabel420714a2013-03-27 18:30:44 +0100453 };
454 };
455
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200456 pwm1: pwm@53fb4000 {
457 #pwm-cells = <2>;
458 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
459 reg = <0x53fb4000 0x4000>;
Lucas Stach564695d2013-11-14 11:18:58 +0100460 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
461 <&clks IMX5_CLK_PWM1_HF_GATE>;
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200462 clock-names = "ipg", "per";
463 interrupts = <61>;
464 };
465
466 pwm2: pwm@53fb8000 {
467 #pwm-cells = <2>;
468 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
469 reg = <0x53fb8000 0x4000>;
Lucas Stach564695d2013-11-14 11:18:58 +0100470 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
471 <&clks IMX5_CLK_PWM2_HF_GATE>;
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200472 clock-names = "ipg", "per";
473 interrupts = <94>;
474 };
475
Shawn Guo0c456cf2012-04-02 14:39:26 +0800476 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800477 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
478 reg = <0x53fbc000 0x4000>;
479 interrupts = <31>;
Lucas Stach564695d2013-11-14 11:18:58 +0100480 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
481 <&clks IMX5_CLK_UART1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200482 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800483 status = "disabled";
484 };
485
Shawn Guo0c456cf2012-04-02 14:39:26 +0800486 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800487 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
488 reg = <0x53fc0000 0x4000>;
489 interrupts = <32>;
Lucas Stach564695d2013-11-14 11:18:58 +0100490 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
491 <&clks IMX5_CLK_UART2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200492 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800493 status = "disabled";
494 };
495
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200496 can1: can@53fc8000 {
497 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
498 reg = <0x53fc8000 0x4000>;
499 interrupts = <82>;
Lucas Stach564695d2013-11-14 11:18:58 +0100500 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
501 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200502 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200503 status = "disabled";
504 };
505
506 can2: can@53fcc000 {
507 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
508 reg = <0x53fcc000 0x4000>;
509 interrupts = <83>;
Lucas Stach564695d2013-11-14 11:18:58 +0100510 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
511 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200512 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200513 status = "disabled";
514 };
515
Philipp Zabel8d84c372013-03-28 17:35:23 +0100516 src: src@53fd0000 {
517 compatible = "fsl,imx53-src", "fsl,imx51-src";
518 reg = <0x53fd0000 0x4000>;
519 #reset-cells = <1>;
520 };
521
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200522 clks: ccm@53fd4000{
523 compatible = "fsl,imx53-ccm";
524 reg = <0x53fd4000 0x4000>;
525 interrupts = <0 71 0x04 0 72 0x04>;
526 #clock-cells = <1>;
527 };
528
Richard Zhao4d191862011-12-14 09:26:44 +0800529 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200530 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800531 reg = <0x53fdc000 0x4000>;
532 interrupts = <103 104>;
533 gpio-controller;
534 #gpio-cells = <2>;
535 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800536 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800537 };
538
Richard Zhao4d191862011-12-14 09:26:44 +0800539 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200540 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800541 reg = <0x53fe0000 0x4000>;
542 interrupts = <105 106>;
543 gpio-controller;
544 #gpio-cells = <2>;
545 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800546 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800547 };
548
Richard Zhao4d191862011-12-14 09:26:44 +0800549 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200550 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800551 reg = <0x53fe4000 0x4000>;
552 interrupts = <107 108>;
553 gpio-controller;
554 #gpio-cells = <2>;
555 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800556 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800557 };
558
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100559 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800560 #address-cells = <1>;
561 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800562 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800563 reg = <0x53fec000 0x4000>;
564 interrupts = <64>;
Lucas Stach564695d2013-11-14 11:18:58 +0100565 clocks = <&clks IMX5_CLK_I2C3_GATE>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800566 status = "disabled";
567 };
568
Shawn Guo0c456cf2012-04-02 14:39:26 +0800569 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800570 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
571 reg = <0x53ff0000 0x4000>;
572 interrupts = <13>;
Lucas Stach564695d2013-11-14 11:18:58 +0100573 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
574 <&clks IMX5_CLK_UART4_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200575 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800576 status = "disabled";
577 };
578 };
579
580 aips@60000000 { /* AIPS2 */
581 compatible = "fsl,aips-bus", "simple-bus";
582 #address-cells = <1>;
583 #size-cells = <1>;
584 reg = <0x60000000 0x10000000>;
585 ranges;
586
Steffen Trumtrarac082812014-06-25 13:01:30 +0200587 aipstz2: bridge@63f00000 {
588 compatible = "fsl,imx53-aipstz";
589 reg = <0x63f00000 0x60>;
590 };
591
Sascha Hauer4f3b2a42013-06-25 15:51:52 +0200592 iim: iim@63f98000 {
593 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
594 reg = <0x63f98000 0x4000>;
595 interrupts = <69>;
Lucas Stach564695d2013-11-14 11:18:58 +0100596 clocks = <&clks IMX5_CLK_IIM_GATE>;
Sascha Hauer4f3b2a42013-06-25 15:51:52 +0200597 };
598
Shawn Guo0c456cf2012-04-02 14:39:26 +0800599 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800600 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
601 reg = <0x63f90000 0x4000>;
602 interrupts = <86>;
Lucas Stach564695d2013-11-14 11:18:58 +0100603 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
604 <&clks IMX5_CLK_UART5_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200605 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800606 status = "disabled";
607 };
608
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100609 owire: owire@63fa4000 {
610 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
611 reg = <0x63fa4000 0x4000>;
Lucas Stach564695d2013-11-14 11:18:58 +0100612 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100613 status = "disabled";
614 };
615
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100616 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800617 #address-cells = <1>;
618 #size-cells = <0>;
619 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
620 reg = <0x63fac000 0x4000>;
621 interrupts = <37>;
Lucas Stach564695d2013-11-14 11:18:58 +0100622 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
623 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200624 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800625 status = "disabled";
626 };
627
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100628 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800629 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
630 reg = <0x63fb0000 0x4000>;
631 interrupts = <6>;
Lucas Stach564695d2013-11-14 11:18:58 +0100632 clocks = <&clks IMX5_CLK_SDMA_GATE>,
633 <&clks IMX5_CLK_SDMA_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200634 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800635 #dma-cells = <3>;
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300636 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800637 };
638
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100639 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800640 #address-cells = <1>;
641 #size-cells = <0>;
642 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
643 reg = <0x63fc0000 0x4000>;
644 interrupts = <38>;
Lucas Stach564695d2013-11-14 11:18:58 +0100645 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
646 <&clks IMX5_CLK_CSPI_IPG_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200647 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800648 status = "disabled";
649 };
650
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100651 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800652 #address-cells = <1>;
653 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800654 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800655 reg = <0x63fc4000 0x4000>;
656 interrupts = <63>;
Lucas Stach564695d2013-11-14 11:18:58 +0100657 clocks = <&clks IMX5_CLK_I2C2_GATE>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800658 status = "disabled";
659 };
660
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100661 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800662 #address-cells = <1>;
663 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800664 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800665 reg = <0x63fc8000 0x4000>;
666 interrupts = <62>;
Lucas Stach564695d2013-11-14 11:18:58 +0100667 clocks = <&clks IMX5_CLK_I2C1_GATE>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800668 status = "disabled";
669 };
670
Shawn Guoffc505c2012-05-11 13:12:01 +0800671 ssi1: ssi@63fcc000 {
Markus Pargmann28f93d02014-01-17 10:07:42 +0100672 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
673 "fsl,imx21-ssi";
Shawn Guoffc505c2012-05-11 13:12:01 +0800674 reg = <0x63fcc000 0x4000>;
675 interrupts = <29>;
Lucas Stach564695d2013-11-14 11:18:58 +0100676 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800677 dmas = <&sdma 28 0 0>,
678 <&sdma 29 0 0>;
679 dma-names = "rx", "tx";
Shawn Guoffc505c2012-05-11 13:12:01 +0800680 fsl,fifo-depth = <15>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800681 status = "disabled";
682 };
683
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100684 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800685 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
686 reg = <0x63fd0000 0x4000>;
687 status = "disabled";
688 };
689
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100690 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200691 compatible = "fsl,imx53-nand";
692 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
693 interrupts = <8>;
Lucas Stach564695d2013-11-14 11:18:58 +0100694 clocks = <&clks IMX5_CLK_NFC_GATE>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200695 status = "disabled";
696 };
697
Shawn Guoffc505c2012-05-11 13:12:01 +0800698 ssi3: ssi@63fe8000 {
Markus Pargmann28f93d02014-01-17 10:07:42 +0100699 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
700 "fsl,imx21-ssi";
Shawn Guoffc505c2012-05-11 13:12:01 +0800701 reg = <0x63fe8000 0x4000>;
702 interrupts = <96>;
Lucas Stach564695d2013-11-14 11:18:58 +0100703 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800704 dmas = <&sdma 46 0 0>,
705 <&sdma 47 0 0>;
706 dma-names = "rx", "tx";
Shawn Guoffc505c2012-05-11 13:12:01 +0800707 fsl,fifo-depth = <15>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800708 status = "disabled";
709 };
710
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100711 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800712 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
713 reg = <0x63fec000 0x4000>;
714 interrupts = <87>;
Lucas Stach564695d2013-11-14 11:18:58 +0100715 clocks = <&clks IMX5_CLK_FEC_GATE>,
716 <&clks IMX5_CLK_FEC_GATE>,
717 <&clks IMX5_CLK_FEC_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200718 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800719 status = "disabled";
720 };
Philipp Zabel19194c22013-06-04 12:12:22 +0200721
722 tve: tve@63ff0000 {
723 compatible = "fsl,imx53-tve";
724 reg = <0x63ff0000 0x1000>;
725 interrupts = <92>;
Lucas Stach564695d2013-11-14 11:18:58 +0100726 clocks = <&clks IMX5_CLK_TVE_GATE>,
727 <&clks IMX5_CLK_IPU_DI1_SEL>;
Philipp Zabel19194c22013-06-04 12:12:22 +0200728 clock-names = "tve", "di_sel";
Philipp Zabel19194c22013-06-04 12:12:22 +0200729 status = "disabled";
Philipp Zabele05c8c92014-03-05 10:21:00 +0100730
731 port {
732 tve_in: endpoint {
733 remote-endpoint = <&ipu_di1_tve>;
734 };
735 };
Philipp Zabel19194c22013-06-04 12:12:22 +0200736 };
Fabio Estevamfbf970f2013-06-28 19:49:18 -0300737
738 vpu: vpu@63ff4000 {
739 compatible = "fsl,imx53-vpu";
740 reg = <0x63ff4000 0x1000>;
741 interrupts = <9>;
Lothar Waßmannfa97d2f2014-08-13 15:47:47 +0200742 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
Lucas Stach564695d2013-11-14 11:18:58 +0100743 <&clks IMX5_CLK_VPU_GATE>;
Fabio Estevamfbf970f2013-06-28 19:49:18 -0300744 clock-names = "per", "ahb";
Philipp Zabelb1e2e542014-03-19 15:49:24 +0100745 resets = <&src 1>;
Fabio Estevamfbf970f2013-06-28 19:49:18 -0300746 iram = <&ocram>;
Fabio Estevamfbf970f2013-06-28 19:49:18 -0300747 };
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800748 };
Philipp Zabel481fbe12013-07-01 11:06:09 +0200749
750 ocram: sram@f8000000 {
751 compatible = "mmio-sram";
752 reg = <0xf8000000 0x20000>;
Lucas Stach564695d2013-11-14 11:18:58 +0100753 clocks = <&clks IMX5_CLK_OCRAM>;
Philipp Zabel481fbe12013-07-01 11:06:09 +0200754 };
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800755 };
756};