blob: 1dd8d927e0353035c8a38ba6b5b88c082a21b1d4 [file] [log] [blame]
Daniel Vetter0a10c852010-03-11 21:19:14 +00001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
Alex Deucherabf1dc62012-07-17 14:02:36 -040043/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
Daniel Vetter0a10c852010-03-11 21:19:14 +000053static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
Alex Deucherabf1dc62012-07-17 14:02:36 -040060/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
Daniel Vetter0a10c852010-03-11 21:19:14 +000070static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
Alex Deucherabf1dc62012-07-17 14:02:36 -040077/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
Daniel Vetter0a10c852010-03-11 21:19:14 +000085static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
Alex Deucherb4df8be2011-04-12 13:40:18 -0400125 if (rdev->family >= CHIP_R600) {
Daniel Vetter0a10c852010-03-11 21:19:14 +0000126 rdev->pciep_rreg = &r600_pciep_rreg;
127 rdev->pciep_wreg = &r600_pciep_wreg;
128 }
129}
130
131
132/* helper to disable agp */
Alex Deucherabf1dc62012-07-17 14:02:36 -0400133/**
134 * radeon_agp_disable - AGP disable helper function
135 *
136 * @rdev: radeon device pointer
137 *
138 * Removes AGP flags and changes the gart callbacks on AGP
139 * cards when using the internal gart rather than AGP (all asics).
140 */
Daniel Vetter0a10c852010-03-11 21:19:14 +0000141void radeon_agp_disable(struct radeon_device *rdev)
142{
143 rdev->flags &= ~RADEON_IS_AGP;
144 if (rdev->family >= CHIP_R600) {
145 DRM_INFO("Forcing AGP to PCIE mode\n");
146 rdev->flags |= RADEON_IS_PCIE;
147 } else if (rdev->family >= CHIP_RV515 ||
148 rdev->family == CHIP_RV380 ||
149 rdev->family == CHIP_RV410 ||
150 rdev->family == CHIP_R423) {
151 DRM_INFO("Forcing AGP to PCIE mode\n");
152 rdev->flags |= RADEON_IS_PCIE;
Alex Deucherc5b3b852012-02-23 17:53:46 -0500153 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
154 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
Daniel Vetter0a10c852010-03-11 21:19:14 +0000155 } else {
156 DRM_INFO("Forcing AGP to PCI mode\n");
157 rdev->flags |= RADEON_IS_PCI;
Alex Deucherc5b3b852012-02-23 17:53:46 -0500158 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
159 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
Daniel Vetter0a10c852010-03-11 21:19:14 +0000160 }
161 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
162}
163
164/*
165 * ASIC
166 */
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000167static struct radeon_asic r100_asic = {
168 .init = &r100_init,
169 .fini = &r100_fini,
170 .suspend = &r100_suspend,
171 .resume = &r100_resume,
172 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000173 .asic_reset = &r100_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500174 .ioctl_wait_idle = NULL,
175 .gui_idle = &r100_gui_idle,
176 .mc_wait_for_idle = &r100_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500177 .gart = {
178 .tlb_flush = &r100_pci_gart_tlb_flush,
179 .set_page = &r100_pci_gart_set_page,
180 },
Christian König4c87bc22011-10-19 19:02:21 +0200181 .ring = {
182 [RADEON_RING_TYPE_GFX_INDEX] = {
183 .ib_execute = &r100_ring_ib_execute,
184 .emit_fence = &r100_fence_ring_emit,
185 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100186 .cs_parse = &r100_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500187 .ring_start = &r100_ring_start,
188 .ring_test = &r100_ring_test,
189 .ib_test = &r100_ib_test,
Christian König312c4a82012-05-02 15:11:09 +0200190 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200191 }
192 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500193 .irq = {
194 .set = &r100_irq_set,
195 .process = &r100_irq_process,
196 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500197 .display = {
198 .bandwidth_update = &r100_bandwidth_update,
199 .get_vblank_counter = &r100_get_vblank_counter,
200 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400201 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400202 .get_backlight_level = &radeon_legacy_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500203 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500204 .copy = {
205 .blit = &r100_copy_blit,
206 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
207 .dma = NULL,
208 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
209 .copy = &r100_copy_blit,
210 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
211 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500212 .surface = {
213 .set_reg = r100_set_surface_reg,
214 .clear_reg = r100_clear_surface_reg,
215 },
Alex Deucher901ea572012-02-23 17:53:39 -0500216 .hpd = {
217 .init = &r100_hpd_init,
218 .fini = &r100_hpd_fini,
219 .sense = &r100_hpd_sense,
220 .set_polarity = &r100_hpd_set_polarity,
221 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500222 .pm = {
223 .misc = &r100_pm_misc,
224 .prepare = &r100_pm_prepare,
225 .finish = &r100_pm_finish,
226 .init_profile = &r100_pm_init_profile,
227 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500228 .get_engine_clock = &radeon_legacy_get_engine_clock,
229 .set_engine_clock = &radeon_legacy_set_engine_clock,
230 .get_memory_clock = &radeon_legacy_get_memory_clock,
231 .set_memory_clock = NULL,
232 .get_pcie_lanes = NULL,
233 .set_pcie_lanes = NULL,
234 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500235 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500236 .pflip = {
237 .pre_page_flip = &r100_pre_page_flip,
238 .page_flip = &r100_page_flip,
239 .post_page_flip = &r100_post_page_flip,
240 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000241};
242
243static struct radeon_asic r200_asic = {
244 .init = &r100_init,
245 .fini = &r100_fini,
246 .suspend = &r100_suspend,
247 .resume = &r100_resume,
248 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000249 .asic_reset = &r100_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500250 .ioctl_wait_idle = NULL,
251 .gui_idle = &r100_gui_idle,
252 .mc_wait_for_idle = &r100_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500253 .gart = {
254 .tlb_flush = &r100_pci_gart_tlb_flush,
255 .set_page = &r100_pci_gart_set_page,
256 },
Christian König4c87bc22011-10-19 19:02:21 +0200257 .ring = {
258 [RADEON_RING_TYPE_GFX_INDEX] = {
259 .ib_execute = &r100_ring_ib_execute,
260 .emit_fence = &r100_fence_ring_emit,
261 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100262 .cs_parse = &r100_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500263 .ring_start = &r100_ring_start,
264 .ring_test = &r100_ring_test,
265 .ib_test = &r100_ib_test,
Christian König312c4a82012-05-02 15:11:09 +0200266 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200267 }
268 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500269 .irq = {
270 .set = &r100_irq_set,
271 .process = &r100_irq_process,
272 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500273 .display = {
274 .bandwidth_update = &r100_bandwidth_update,
275 .get_vblank_counter = &r100_get_vblank_counter,
276 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400277 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400278 .get_backlight_level = &radeon_legacy_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500279 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500280 .copy = {
281 .blit = &r100_copy_blit,
282 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
283 .dma = &r200_copy_dma,
284 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
285 .copy = &r100_copy_blit,
286 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
287 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500288 .surface = {
289 .set_reg = r100_set_surface_reg,
290 .clear_reg = r100_clear_surface_reg,
291 },
Alex Deucher901ea572012-02-23 17:53:39 -0500292 .hpd = {
293 .init = &r100_hpd_init,
294 .fini = &r100_hpd_fini,
295 .sense = &r100_hpd_sense,
296 .set_polarity = &r100_hpd_set_polarity,
297 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500298 .pm = {
299 .misc = &r100_pm_misc,
300 .prepare = &r100_pm_prepare,
301 .finish = &r100_pm_finish,
302 .init_profile = &r100_pm_init_profile,
303 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500304 .get_engine_clock = &radeon_legacy_get_engine_clock,
305 .set_engine_clock = &radeon_legacy_set_engine_clock,
306 .get_memory_clock = &radeon_legacy_get_memory_clock,
307 .set_memory_clock = NULL,
308 .get_pcie_lanes = NULL,
309 .set_pcie_lanes = NULL,
310 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500311 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500312 .pflip = {
313 .pre_page_flip = &r100_pre_page_flip,
314 .page_flip = &r100_page_flip,
315 .post_page_flip = &r100_post_page_flip,
316 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000317};
318
319static struct radeon_asic r300_asic = {
320 .init = &r300_init,
321 .fini = &r300_fini,
322 .suspend = &r300_suspend,
323 .resume = &r300_resume,
324 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000325 .asic_reset = &r300_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500326 .ioctl_wait_idle = NULL,
327 .gui_idle = &r100_gui_idle,
328 .mc_wait_for_idle = &r300_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500329 .gart = {
330 .tlb_flush = &r100_pci_gart_tlb_flush,
331 .set_page = &r100_pci_gart_set_page,
332 },
Christian König4c87bc22011-10-19 19:02:21 +0200333 .ring = {
334 [RADEON_RING_TYPE_GFX_INDEX] = {
335 .ib_execute = &r100_ring_ib_execute,
336 .emit_fence = &r300_fence_ring_emit,
337 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100338 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500339 .ring_start = &r300_ring_start,
340 .ring_test = &r100_ring_test,
341 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200342 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200343 }
344 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500345 .irq = {
346 .set = &r100_irq_set,
347 .process = &r100_irq_process,
348 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500349 .display = {
350 .bandwidth_update = &r100_bandwidth_update,
351 .get_vblank_counter = &r100_get_vblank_counter,
352 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400353 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400354 .get_backlight_level = &radeon_legacy_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500355 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500356 .copy = {
357 .blit = &r100_copy_blit,
358 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
359 .dma = &r200_copy_dma,
360 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
361 .copy = &r100_copy_blit,
362 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
363 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500364 .surface = {
365 .set_reg = r100_set_surface_reg,
366 .clear_reg = r100_clear_surface_reg,
367 },
Alex Deucher901ea572012-02-23 17:53:39 -0500368 .hpd = {
369 .init = &r100_hpd_init,
370 .fini = &r100_hpd_fini,
371 .sense = &r100_hpd_sense,
372 .set_polarity = &r100_hpd_set_polarity,
373 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500374 .pm = {
375 .misc = &r100_pm_misc,
376 .prepare = &r100_pm_prepare,
377 .finish = &r100_pm_finish,
378 .init_profile = &r100_pm_init_profile,
379 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500380 .get_engine_clock = &radeon_legacy_get_engine_clock,
381 .set_engine_clock = &radeon_legacy_set_engine_clock,
382 .get_memory_clock = &radeon_legacy_get_memory_clock,
383 .set_memory_clock = NULL,
384 .get_pcie_lanes = &rv370_get_pcie_lanes,
385 .set_pcie_lanes = &rv370_set_pcie_lanes,
386 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500387 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500388 .pflip = {
389 .pre_page_flip = &r100_pre_page_flip,
390 .page_flip = &r100_page_flip,
391 .post_page_flip = &r100_post_page_flip,
392 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000393};
394
395static struct radeon_asic r300_asic_pcie = {
396 .init = &r300_init,
397 .fini = &r300_fini,
398 .suspend = &r300_suspend,
399 .resume = &r300_resume,
400 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000401 .asic_reset = &r300_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500402 .ioctl_wait_idle = NULL,
403 .gui_idle = &r100_gui_idle,
404 .mc_wait_for_idle = &r300_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500405 .gart = {
406 .tlb_flush = &rv370_pcie_gart_tlb_flush,
407 .set_page = &rv370_pcie_gart_set_page,
408 },
Christian König4c87bc22011-10-19 19:02:21 +0200409 .ring = {
410 [RADEON_RING_TYPE_GFX_INDEX] = {
411 .ib_execute = &r100_ring_ib_execute,
412 .emit_fence = &r300_fence_ring_emit,
413 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100414 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500415 .ring_start = &r300_ring_start,
416 .ring_test = &r100_ring_test,
417 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200418 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200419 }
420 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500421 .irq = {
422 .set = &r100_irq_set,
423 .process = &r100_irq_process,
424 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500425 .display = {
426 .bandwidth_update = &r100_bandwidth_update,
427 .get_vblank_counter = &r100_get_vblank_counter,
428 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400429 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400430 .get_backlight_level = &radeon_legacy_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500431 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500432 .copy = {
433 .blit = &r100_copy_blit,
434 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
435 .dma = &r200_copy_dma,
436 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
437 .copy = &r100_copy_blit,
438 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
439 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500440 .surface = {
441 .set_reg = r100_set_surface_reg,
442 .clear_reg = r100_clear_surface_reg,
443 },
Alex Deucher901ea572012-02-23 17:53:39 -0500444 .hpd = {
445 .init = &r100_hpd_init,
446 .fini = &r100_hpd_fini,
447 .sense = &r100_hpd_sense,
448 .set_polarity = &r100_hpd_set_polarity,
449 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500450 .pm = {
451 .misc = &r100_pm_misc,
452 .prepare = &r100_pm_prepare,
453 .finish = &r100_pm_finish,
454 .init_profile = &r100_pm_init_profile,
455 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500456 .get_engine_clock = &radeon_legacy_get_engine_clock,
457 .set_engine_clock = &radeon_legacy_set_engine_clock,
458 .get_memory_clock = &radeon_legacy_get_memory_clock,
459 .set_memory_clock = NULL,
460 .get_pcie_lanes = &rv370_get_pcie_lanes,
461 .set_pcie_lanes = &rv370_set_pcie_lanes,
462 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500463 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500464 .pflip = {
465 .pre_page_flip = &r100_pre_page_flip,
466 .page_flip = &r100_page_flip,
467 .post_page_flip = &r100_post_page_flip,
468 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000469};
470
471static struct radeon_asic r420_asic = {
472 .init = &r420_init,
473 .fini = &r420_fini,
474 .suspend = &r420_suspend,
475 .resume = &r420_resume,
476 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000477 .asic_reset = &r300_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500478 .ioctl_wait_idle = NULL,
479 .gui_idle = &r100_gui_idle,
480 .mc_wait_for_idle = &r300_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500481 .gart = {
482 .tlb_flush = &rv370_pcie_gart_tlb_flush,
483 .set_page = &rv370_pcie_gart_set_page,
484 },
Christian König4c87bc22011-10-19 19:02:21 +0200485 .ring = {
486 [RADEON_RING_TYPE_GFX_INDEX] = {
487 .ib_execute = &r100_ring_ib_execute,
488 .emit_fence = &r300_fence_ring_emit,
489 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100490 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500491 .ring_start = &r300_ring_start,
492 .ring_test = &r100_ring_test,
493 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200494 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200495 }
496 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500497 .irq = {
498 .set = &r100_irq_set,
499 .process = &r100_irq_process,
500 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500501 .display = {
502 .bandwidth_update = &r100_bandwidth_update,
503 .get_vblank_counter = &r100_get_vblank_counter,
504 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400505 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400506 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500507 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500508 .copy = {
509 .blit = &r100_copy_blit,
510 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
511 .dma = &r200_copy_dma,
512 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
513 .copy = &r100_copy_blit,
514 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
515 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500516 .surface = {
517 .set_reg = r100_set_surface_reg,
518 .clear_reg = r100_clear_surface_reg,
519 },
Alex Deucher901ea572012-02-23 17:53:39 -0500520 .hpd = {
521 .init = &r100_hpd_init,
522 .fini = &r100_hpd_fini,
523 .sense = &r100_hpd_sense,
524 .set_polarity = &r100_hpd_set_polarity,
525 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500526 .pm = {
527 .misc = &r100_pm_misc,
528 .prepare = &r100_pm_prepare,
529 .finish = &r100_pm_finish,
530 .init_profile = &r420_pm_init_profile,
531 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500532 .get_engine_clock = &radeon_atom_get_engine_clock,
533 .set_engine_clock = &radeon_atom_set_engine_clock,
534 .get_memory_clock = &radeon_atom_get_memory_clock,
535 .set_memory_clock = &radeon_atom_set_memory_clock,
536 .get_pcie_lanes = &rv370_get_pcie_lanes,
537 .set_pcie_lanes = &rv370_set_pcie_lanes,
538 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500539 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500540 .pflip = {
541 .pre_page_flip = &r100_pre_page_flip,
542 .page_flip = &r100_page_flip,
543 .post_page_flip = &r100_post_page_flip,
544 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000545};
546
547static struct radeon_asic rs400_asic = {
548 .init = &rs400_init,
549 .fini = &rs400_fini,
550 .suspend = &rs400_suspend,
551 .resume = &rs400_resume,
552 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000553 .asic_reset = &r300_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500554 .ioctl_wait_idle = NULL,
555 .gui_idle = &r100_gui_idle,
556 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500557 .gart = {
558 .tlb_flush = &rs400_gart_tlb_flush,
559 .set_page = &rs400_gart_set_page,
560 },
Christian König4c87bc22011-10-19 19:02:21 +0200561 .ring = {
562 [RADEON_RING_TYPE_GFX_INDEX] = {
563 .ib_execute = &r100_ring_ib_execute,
564 .emit_fence = &r300_fence_ring_emit,
565 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100566 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500567 .ring_start = &r300_ring_start,
568 .ring_test = &r100_ring_test,
569 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200570 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200571 }
572 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500573 .irq = {
574 .set = &r100_irq_set,
575 .process = &r100_irq_process,
576 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500577 .display = {
578 .bandwidth_update = &r100_bandwidth_update,
579 .get_vblank_counter = &r100_get_vblank_counter,
580 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400581 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400582 .get_backlight_level = &radeon_legacy_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500583 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500584 .copy = {
585 .blit = &r100_copy_blit,
586 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
587 .dma = &r200_copy_dma,
588 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
589 .copy = &r100_copy_blit,
590 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
591 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500592 .surface = {
593 .set_reg = r100_set_surface_reg,
594 .clear_reg = r100_clear_surface_reg,
595 },
Alex Deucher901ea572012-02-23 17:53:39 -0500596 .hpd = {
597 .init = &r100_hpd_init,
598 .fini = &r100_hpd_fini,
599 .sense = &r100_hpd_sense,
600 .set_polarity = &r100_hpd_set_polarity,
601 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500602 .pm = {
603 .misc = &r100_pm_misc,
604 .prepare = &r100_pm_prepare,
605 .finish = &r100_pm_finish,
606 .init_profile = &r100_pm_init_profile,
607 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500608 .get_engine_clock = &radeon_legacy_get_engine_clock,
609 .set_engine_clock = &radeon_legacy_set_engine_clock,
610 .get_memory_clock = &radeon_legacy_get_memory_clock,
611 .set_memory_clock = NULL,
612 .get_pcie_lanes = NULL,
613 .set_pcie_lanes = NULL,
614 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500615 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500616 .pflip = {
617 .pre_page_flip = &r100_pre_page_flip,
618 .page_flip = &r100_page_flip,
619 .post_page_flip = &r100_post_page_flip,
620 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000621};
622
623static struct radeon_asic rs600_asic = {
624 .init = &rs600_init,
625 .fini = &rs600_fini,
626 .suspend = &rs600_suspend,
627 .resume = &rs600_resume,
628 .vga_set_state = &r100_vga_set_state,
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000629 .asic_reset = &rs600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500630 .ioctl_wait_idle = NULL,
631 .gui_idle = &r100_gui_idle,
632 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500633 .gart = {
634 .tlb_flush = &rs600_gart_tlb_flush,
635 .set_page = &rs600_gart_set_page,
636 },
Christian König4c87bc22011-10-19 19:02:21 +0200637 .ring = {
638 [RADEON_RING_TYPE_GFX_INDEX] = {
639 .ib_execute = &r100_ring_ib_execute,
640 .emit_fence = &r300_fence_ring_emit,
641 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100642 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500643 .ring_start = &r300_ring_start,
644 .ring_test = &r100_ring_test,
645 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200646 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200647 }
648 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500649 .irq = {
650 .set = &rs600_irq_set,
651 .process = &rs600_irq_process,
652 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500653 .display = {
654 .bandwidth_update = &rs600_bandwidth_update,
655 .get_vblank_counter = &rs600_get_vblank_counter,
656 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400657 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400658 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500659 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500660 .copy = {
661 .blit = &r100_copy_blit,
662 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
663 .dma = &r200_copy_dma,
664 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
665 .copy = &r100_copy_blit,
666 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
667 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500668 .surface = {
669 .set_reg = r100_set_surface_reg,
670 .clear_reg = r100_clear_surface_reg,
671 },
Alex Deucher901ea572012-02-23 17:53:39 -0500672 .hpd = {
673 .init = &rs600_hpd_init,
674 .fini = &rs600_hpd_fini,
675 .sense = &rs600_hpd_sense,
676 .set_polarity = &rs600_hpd_set_polarity,
677 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500678 .pm = {
679 .misc = &rs600_pm_misc,
680 .prepare = &rs600_pm_prepare,
681 .finish = &rs600_pm_finish,
682 .init_profile = &r420_pm_init_profile,
683 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500684 .get_engine_clock = &radeon_atom_get_engine_clock,
685 .set_engine_clock = &radeon_atom_set_engine_clock,
686 .get_memory_clock = &radeon_atom_get_memory_clock,
687 .set_memory_clock = &radeon_atom_set_memory_clock,
688 .get_pcie_lanes = NULL,
689 .set_pcie_lanes = NULL,
690 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500691 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500692 .pflip = {
693 .pre_page_flip = &rs600_pre_page_flip,
694 .page_flip = &rs600_page_flip,
695 .post_page_flip = &rs600_post_page_flip,
696 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000697};
698
699static struct radeon_asic rs690_asic = {
700 .init = &rs690_init,
701 .fini = &rs690_fini,
702 .suspend = &rs690_suspend,
703 .resume = &rs690_resume,
704 .vga_set_state = &r100_vga_set_state,
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000705 .asic_reset = &rs600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500706 .ioctl_wait_idle = NULL,
707 .gui_idle = &r100_gui_idle,
708 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500709 .gart = {
710 .tlb_flush = &rs400_gart_tlb_flush,
711 .set_page = &rs400_gart_set_page,
712 },
Christian König4c87bc22011-10-19 19:02:21 +0200713 .ring = {
714 [RADEON_RING_TYPE_GFX_INDEX] = {
715 .ib_execute = &r100_ring_ib_execute,
716 .emit_fence = &r300_fence_ring_emit,
717 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100718 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500719 .ring_start = &r300_ring_start,
720 .ring_test = &r100_ring_test,
721 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200722 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200723 }
724 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500725 .irq = {
726 .set = &rs600_irq_set,
727 .process = &rs600_irq_process,
728 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500729 .display = {
730 .get_vblank_counter = &rs600_get_vblank_counter,
731 .bandwidth_update = &rs690_bandwidth_update,
732 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400733 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400734 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500735 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500736 .copy = {
737 .blit = &r100_copy_blit,
738 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
739 .dma = &r200_copy_dma,
740 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
741 .copy = &r200_copy_dma,
742 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
743 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500744 .surface = {
745 .set_reg = r100_set_surface_reg,
746 .clear_reg = r100_clear_surface_reg,
747 },
Alex Deucher901ea572012-02-23 17:53:39 -0500748 .hpd = {
749 .init = &rs600_hpd_init,
750 .fini = &rs600_hpd_fini,
751 .sense = &rs600_hpd_sense,
752 .set_polarity = &rs600_hpd_set_polarity,
753 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500754 .pm = {
755 .misc = &rs600_pm_misc,
756 .prepare = &rs600_pm_prepare,
757 .finish = &rs600_pm_finish,
758 .init_profile = &r420_pm_init_profile,
759 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500760 .get_engine_clock = &radeon_atom_get_engine_clock,
761 .set_engine_clock = &radeon_atom_set_engine_clock,
762 .get_memory_clock = &radeon_atom_get_memory_clock,
763 .set_memory_clock = &radeon_atom_set_memory_clock,
764 .get_pcie_lanes = NULL,
765 .set_pcie_lanes = NULL,
766 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500767 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500768 .pflip = {
769 .pre_page_flip = &rs600_pre_page_flip,
770 .page_flip = &rs600_page_flip,
771 .post_page_flip = &rs600_post_page_flip,
772 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000773};
774
775static struct radeon_asic rv515_asic = {
776 .init = &rv515_init,
777 .fini = &rv515_fini,
778 .suspend = &rv515_suspend,
779 .resume = &rv515_resume,
780 .vga_set_state = &r100_vga_set_state,
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000781 .asic_reset = &rs600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500782 .ioctl_wait_idle = NULL,
783 .gui_idle = &r100_gui_idle,
784 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500785 .gart = {
786 .tlb_flush = &rv370_pcie_gart_tlb_flush,
787 .set_page = &rv370_pcie_gart_set_page,
788 },
Christian König4c87bc22011-10-19 19:02:21 +0200789 .ring = {
790 [RADEON_RING_TYPE_GFX_INDEX] = {
791 .ib_execute = &r100_ring_ib_execute,
792 .emit_fence = &r300_fence_ring_emit,
793 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100794 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500795 .ring_start = &rv515_ring_start,
796 .ring_test = &r100_ring_test,
797 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200798 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200799 }
800 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500801 .irq = {
802 .set = &rs600_irq_set,
803 .process = &rs600_irq_process,
804 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500805 .display = {
806 .get_vblank_counter = &rs600_get_vblank_counter,
807 .bandwidth_update = &rv515_bandwidth_update,
808 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400809 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400810 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500811 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500812 .copy = {
813 .blit = &r100_copy_blit,
814 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
815 .dma = &r200_copy_dma,
816 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
817 .copy = &r100_copy_blit,
818 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
819 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500820 .surface = {
821 .set_reg = r100_set_surface_reg,
822 .clear_reg = r100_clear_surface_reg,
823 },
Alex Deucher901ea572012-02-23 17:53:39 -0500824 .hpd = {
825 .init = &rs600_hpd_init,
826 .fini = &rs600_hpd_fini,
827 .sense = &rs600_hpd_sense,
828 .set_polarity = &rs600_hpd_set_polarity,
829 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500830 .pm = {
831 .misc = &rs600_pm_misc,
832 .prepare = &rs600_pm_prepare,
833 .finish = &rs600_pm_finish,
834 .init_profile = &r420_pm_init_profile,
835 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500836 .get_engine_clock = &radeon_atom_get_engine_clock,
837 .set_engine_clock = &radeon_atom_set_engine_clock,
838 .get_memory_clock = &radeon_atom_get_memory_clock,
839 .set_memory_clock = &radeon_atom_set_memory_clock,
840 .get_pcie_lanes = &rv370_get_pcie_lanes,
841 .set_pcie_lanes = &rv370_set_pcie_lanes,
842 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500843 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500844 .pflip = {
845 .pre_page_flip = &rs600_pre_page_flip,
846 .page_flip = &rs600_page_flip,
847 .post_page_flip = &rs600_post_page_flip,
848 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000849};
850
851static struct radeon_asic r520_asic = {
852 .init = &r520_init,
853 .fini = &rv515_fini,
854 .suspend = &rv515_suspend,
855 .resume = &r520_resume,
856 .vga_set_state = &r100_vga_set_state,
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000857 .asic_reset = &rs600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500858 .ioctl_wait_idle = NULL,
859 .gui_idle = &r100_gui_idle,
860 .mc_wait_for_idle = &r520_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500861 .gart = {
862 .tlb_flush = &rv370_pcie_gart_tlb_flush,
863 .set_page = &rv370_pcie_gart_set_page,
864 },
Christian König4c87bc22011-10-19 19:02:21 +0200865 .ring = {
866 [RADEON_RING_TYPE_GFX_INDEX] = {
867 .ib_execute = &r100_ring_ib_execute,
868 .emit_fence = &r300_fence_ring_emit,
869 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100870 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500871 .ring_start = &rv515_ring_start,
872 .ring_test = &r100_ring_test,
873 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200874 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200875 }
876 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500877 .irq = {
878 .set = &rs600_irq_set,
879 .process = &rs600_irq_process,
880 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500881 .display = {
882 .bandwidth_update = &rv515_bandwidth_update,
883 .get_vblank_counter = &rs600_get_vblank_counter,
884 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400885 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400886 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500887 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500888 .copy = {
889 .blit = &r100_copy_blit,
890 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
891 .dma = &r200_copy_dma,
892 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
893 .copy = &r100_copy_blit,
894 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
895 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500896 .surface = {
897 .set_reg = r100_set_surface_reg,
898 .clear_reg = r100_clear_surface_reg,
899 },
Alex Deucher901ea572012-02-23 17:53:39 -0500900 .hpd = {
901 .init = &rs600_hpd_init,
902 .fini = &rs600_hpd_fini,
903 .sense = &rs600_hpd_sense,
904 .set_polarity = &rs600_hpd_set_polarity,
905 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500906 .pm = {
907 .misc = &rs600_pm_misc,
908 .prepare = &rs600_pm_prepare,
909 .finish = &rs600_pm_finish,
910 .init_profile = &r420_pm_init_profile,
911 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500912 .get_engine_clock = &radeon_atom_get_engine_clock,
913 .set_engine_clock = &radeon_atom_set_engine_clock,
914 .get_memory_clock = &radeon_atom_get_memory_clock,
915 .set_memory_clock = &radeon_atom_set_memory_clock,
916 .get_pcie_lanes = &rv370_get_pcie_lanes,
917 .set_pcie_lanes = &rv370_set_pcie_lanes,
918 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500919 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500920 .pflip = {
921 .pre_page_flip = &rs600_pre_page_flip,
922 .page_flip = &rs600_page_flip,
923 .post_page_flip = &rs600_post_page_flip,
924 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000925};
926
927static struct radeon_asic r600_asic = {
928 .init = &r600_init,
929 .fini = &r600_fini,
930 .suspend = &r600_suspend,
931 .resume = &r600_resume,
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000932 .vga_set_state = &r600_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000933 .asic_reset = &r600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500934 .ioctl_wait_idle = r600_ioctl_wait_idle,
935 .gui_idle = &r600_gui_idle,
936 .mc_wait_for_idle = &r600_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500937 .gart = {
938 .tlb_flush = &r600_pcie_gart_tlb_flush,
939 .set_page = &rs600_gart_set_page,
940 },
Christian König4c87bc22011-10-19 19:02:21 +0200941 .ring = {
942 [RADEON_RING_TYPE_GFX_INDEX] = {
943 .ib_execute = &r600_ring_ib_execute,
944 .emit_fence = &r600_fence_ring_emit,
945 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100946 .cs_parse = &r600_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500947 .ring_test = &r600_ring_test,
948 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +0200949 .is_lockup = &r600_gpu_is_lockup,
Alex Deucher4d756582012-09-27 15:08:35 -0400950 },
951 [R600_RING_TYPE_DMA_INDEX] = {
952 .ib_execute = &r600_dma_ring_ib_execute,
953 .emit_fence = &r600_dma_fence_ring_emit,
954 .emit_semaphore = &r600_dma_semaphore_ring_emit,
955 .cs_parse = NULL,
956 .ring_test = &r600_dma_ring_test,
957 .ib_test = &r600_dma_ib_test,
958 .is_lockup = &r600_dma_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200959 }
960 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500961 .irq = {
962 .set = &r600_irq_set,
963 .process = &r600_irq_process,
964 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500965 .display = {
966 .bandwidth_update = &rv515_bandwidth_update,
967 .get_vblank_counter = &rs600_get_vblank_counter,
968 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400969 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -0400970 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500971 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500972 .copy = {
973 .blit = &r600_copy_blit,
974 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
Alex Deucher4d756582012-09-27 15:08:35 -0400975 .dma = &r600_copy_dma,
976 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
Alex Deucher27cd7762012-02-23 17:53:42 -0500977 .copy = &r600_copy_blit,
978 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
979 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500980 .surface = {
981 .set_reg = r600_set_surface_reg,
982 .clear_reg = r600_clear_surface_reg,
983 },
Alex Deucher901ea572012-02-23 17:53:39 -0500984 .hpd = {
985 .init = &r600_hpd_init,
986 .fini = &r600_hpd_fini,
987 .sense = &r600_hpd_sense,
988 .set_polarity = &r600_hpd_set_polarity,
989 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500990 .pm = {
991 .misc = &r600_pm_misc,
992 .prepare = &rs600_pm_prepare,
993 .finish = &rs600_pm_finish,
994 .init_profile = &r600_pm_init_profile,
995 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500996 .get_engine_clock = &radeon_atom_get_engine_clock,
997 .set_engine_clock = &radeon_atom_set_engine_clock,
998 .get_memory_clock = &radeon_atom_get_memory_clock,
999 .set_memory_clock = &radeon_atom_set_memory_clock,
1000 .get_pcie_lanes = &r600_get_pcie_lanes,
1001 .set_pcie_lanes = &r600_set_pcie_lanes,
1002 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001003 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001004 .pflip = {
1005 .pre_page_flip = &rs600_pre_page_flip,
1006 .page_flip = &rs600_page_flip,
1007 .post_page_flip = &rs600_post_page_flip,
1008 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001009};
1010
Alex Deucherf47299c2010-03-16 20:54:38 -04001011static struct radeon_asic rs780_asic = {
1012 .init = &r600_init,
1013 .fini = &r600_fini,
1014 .suspend = &r600_suspend,
1015 .resume = &r600_resume,
Alex Deucherf47299c2010-03-16 20:54:38 -04001016 .vga_set_state = &r600_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +00001017 .asic_reset = &r600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -05001018 .ioctl_wait_idle = r600_ioctl_wait_idle,
1019 .gui_idle = &r600_gui_idle,
1020 .mc_wait_for_idle = &r600_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001021 .gart = {
1022 .tlb_flush = &r600_pcie_gart_tlb_flush,
1023 .set_page = &rs600_gart_set_page,
1024 },
Christian König4c87bc22011-10-19 19:02:21 +02001025 .ring = {
1026 [RADEON_RING_TYPE_GFX_INDEX] = {
1027 .ib_execute = &r600_ring_ib_execute,
1028 .emit_fence = &r600_fence_ring_emit,
1029 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001030 .cs_parse = &r600_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001031 .ring_test = &r600_ring_test,
1032 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001033 .is_lockup = &r600_gpu_is_lockup,
Alex Deucher4d756582012-09-27 15:08:35 -04001034 },
1035 [R600_RING_TYPE_DMA_INDEX] = {
1036 .ib_execute = &r600_dma_ring_ib_execute,
1037 .emit_fence = &r600_dma_fence_ring_emit,
1038 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1039 .cs_parse = NULL,
1040 .ring_test = &r600_dma_ring_test,
1041 .ib_test = &r600_dma_ib_test,
1042 .is_lockup = &r600_dma_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001043 }
1044 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001045 .irq = {
1046 .set = &r600_irq_set,
1047 .process = &r600_irq_process,
1048 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001049 .display = {
1050 .bandwidth_update = &rs690_bandwidth_update,
1051 .get_vblank_counter = &rs600_get_vblank_counter,
1052 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001053 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -04001054 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001055 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001056 .copy = {
1057 .blit = &r600_copy_blit,
1058 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
Alex Deucher4d756582012-09-27 15:08:35 -04001059 .dma = &r600_copy_dma,
1060 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
Alex Deucher27cd7762012-02-23 17:53:42 -05001061 .copy = &r600_copy_blit,
1062 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1063 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001064 .surface = {
1065 .set_reg = r600_set_surface_reg,
1066 .clear_reg = r600_clear_surface_reg,
1067 },
Alex Deucher901ea572012-02-23 17:53:39 -05001068 .hpd = {
1069 .init = &r600_hpd_init,
1070 .fini = &r600_hpd_fini,
1071 .sense = &r600_hpd_sense,
1072 .set_polarity = &r600_hpd_set_polarity,
1073 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001074 .pm = {
1075 .misc = &r600_pm_misc,
1076 .prepare = &rs600_pm_prepare,
1077 .finish = &rs600_pm_finish,
1078 .init_profile = &rs780_pm_init_profile,
1079 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001080 .get_engine_clock = &radeon_atom_get_engine_clock,
1081 .set_engine_clock = &radeon_atom_set_engine_clock,
1082 .get_memory_clock = NULL,
1083 .set_memory_clock = NULL,
1084 .get_pcie_lanes = NULL,
1085 .set_pcie_lanes = NULL,
1086 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001087 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001088 .pflip = {
1089 .pre_page_flip = &rs600_pre_page_flip,
1090 .page_flip = &rs600_page_flip,
1091 .post_page_flip = &rs600_post_page_flip,
1092 },
Alex Deucherf47299c2010-03-16 20:54:38 -04001093};
1094
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001095static struct radeon_asic rv770_asic = {
1096 .init = &rv770_init,
1097 .fini = &rv770_fini,
1098 .suspend = &rv770_suspend,
1099 .resume = &rv770_resume,
Jerome Glissea2d07b72010-03-09 14:45:11 +00001100 .asic_reset = &r600_asic_reset,
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001101 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001102 .ioctl_wait_idle = r600_ioctl_wait_idle,
1103 .gui_idle = &r600_gui_idle,
1104 .mc_wait_for_idle = &r600_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001105 .gart = {
1106 .tlb_flush = &r600_pcie_gart_tlb_flush,
1107 .set_page = &rs600_gart_set_page,
1108 },
Christian König4c87bc22011-10-19 19:02:21 +02001109 .ring = {
1110 [RADEON_RING_TYPE_GFX_INDEX] = {
1111 .ib_execute = &r600_ring_ib_execute,
1112 .emit_fence = &r600_fence_ring_emit,
1113 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001114 .cs_parse = &r600_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001115 .ring_test = &r600_ring_test,
1116 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001117 .is_lockup = &r600_gpu_is_lockup,
Alex Deucher4d756582012-09-27 15:08:35 -04001118 },
1119 [R600_RING_TYPE_DMA_INDEX] = {
1120 .ib_execute = &r600_dma_ring_ib_execute,
1121 .emit_fence = &r600_dma_fence_ring_emit,
1122 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1123 .cs_parse = NULL,
1124 .ring_test = &r600_dma_ring_test,
1125 .ib_test = &r600_dma_ib_test,
1126 .is_lockup = &r600_dma_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001127 }
1128 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001129 .irq = {
1130 .set = &r600_irq_set,
1131 .process = &r600_irq_process,
1132 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001133 .display = {
1134 .bandwidth_update = &rv515_bandwidth_update,
1135 .get_vblank_counter = &rs600_get_vblank_counter,
1136 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001137 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -04001138 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001139 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001140 .copy = {
1141 .blit = &r600_copy_blit,
1142 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
Alex Deucher4d756582012-09-27 15:08:35 -04001143 .dma = &r600_copy_dma,
1144 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
Alex Deucher27cd7762012-02-23 17:53:42 -05001145 .copy = &r600_copy_blit,
1146 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1147 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001148 .surface = {
1149 .set_reg = r600_set_surface_reg,
1150 .clear_reg = r600_clear_surface_reg,
1151 },
Alex Deucher901ea572012-02-23 17:53:39 -05001152 .hpd = {
1153 .init = &r600_hpd_init,
1154 .fini = &r600_hpd_fini,
1155 .sense = &r600_hpd_sense,
1156 .set_polarity = &r600_hpd_set_polarity,
1157 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001158 .pm = {
1159 .misc = &rv770_pm_misc,
1160 .prepare = &rs600_pm_prepare,
1161 .finish = &rs600_pm_finish,
1162 .init_profile = &r600_pm_init_profile,
1163 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001164 .get_engine_clock = &radeon_atom_get_engine_clock,
1165 .set_engine_clock = &radeon_atom_set_engine_clock,
1166 .get_memory_clock = &radeon_atom_get_memory_clock,
1167 .set_memory_clock = &radeon_atom_set_memory_clock,
1168 .get_pcie_lanes = &r600_get_pcie_lanes,
1169 .set_pcie_lanes = &r600_set_pcie_lanes,
1170 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -05001171 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001172 .pflip = {
1173 .pre_page_flip = &rs600_pre_page_flip,
1174 .page_flip = &rv770_page_flip,
1175 .post_page_flip = &rs600_post_page_flip,
1176 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001177};
1178
1179static struct radeon_asic evergreen_asic = {
1180 .init = &evergreen_init,
1181 .fini = &evergreen_fini,
1182 .suspend = &evergreen_suspend,
1183 .resume = &evergreen_resume,
Jerome Glissea2d07b72010-03-09 14:45:11 +00001184 .asic_reset = &evergreen_asic_reset,
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001185 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001186 .ioctl_wait_idle = r600_ioctl_wait_idle,
1187 .gui_idle = &r600_gui_idle,
1188 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001189 .gart = {
1190 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1191 .set_page = &rs600_gart_set_page,
1192 },
Christian König4c87bc22011-10-19 19:02:21 +02001193 .ring = {
1194 [RADEON_RING_TYPE_GFX_INDEX] = {
1195 .ib_execute = &evergreen_ring_ib_execute,
1196 .emit_fence = &r600_fence_ring_emit,
1197 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001198 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001199 .ring_test = &r600_ring_test,
1200 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001201 .is_lockup = &evergreen_gpu_is_lockup,
Alex Deucher233d1ad2012-12-04 15:25:59 -05001202 },
1203 [R600_RING_TYPE_DMA_INDEX] = {
1204 .ib_execute = &evergreen_dma_ring_ib_execute,
1205 .emit_fence = &evergreen_dma_fence_ring_emit,
1206 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1207 .cs_parse = NULL,
1208 .ring_test = &r600_dma_ring_test,
1209 .ib_test = &r600_dma_ib_test,
1210 .is_lockup = &r600_dma_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001211 }
1212 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001213 .irq = {
1214 .set = &evergreen_irq_set,
1215 .process = &evergreen_irq_process,
1216 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001217 .display = {
1218 .bandwidth_update = &evergreen_bandwidth_update,
1219 .get_vblank_counter = &evergreen_get_vblank_counter,
1220 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001221 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -04001222 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001223 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001224 .copy = {
1225 .blit = &r600_copy_blit,
1226 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
Alex Deucher233d1ad2012-12-04 15:25:59 -05001227 .dma = &evergreen_copy_dma,
1228 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
Alex Deucher27cd7762012-02-23 17:53:42 -05001229 .copy = &r600_copy_blit,
1230 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1231 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001232 .surface = {
1233 .set_reg = r600_set_surface_reg,
1234 .clear_reg = r600_clear_surface_reg,
1235 },
Alex Deucher901ea572012-02-23 17:53:39 -05001236 .hpd = {
1237 .init = &evergreen_hpd_init,
1238 .fini = &evergreen_hpd_fini,
1239 .sense = &evergreen_hpd_sense,
1240 .set_polarity = &evergreen_hpd_set_polarity,
1241 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001242 .pm = {
1243 .misc = &evergreen_pm_misc,
1244 .prepare = &evergreen_pm_prepare,
1245 .finish = &evergreen_pm_finish,
1246 .init_profile = &r600_pm_init_profile,
1247 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001248 .get_engine_clock = &radeon_atom_get_engine_clock,
1249 .set_engine_clock = &radeon_atom_set_engine_clock,
1250 .get_memory_clock = &radeon_atom_get_memory_clock,
1251 .set_memory_clock = &radeon_atom_set_memory_clock,
1252 .get_pcie_lanes = &r600_get_pcie_lanes,
1253 .set_pcie_lanes = &r600_set_pcie_lanes,
1254 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001255 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001256 .pflip = {
1257 .pre_page_flip = &evergreen_pre_page_flip,
1258 .page_flip = &evergreen_page_flip,
1259 .post_page_flip = &evergreen_post_page_flip,
1260 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001261};
1262
Alex Deucher958261d2010-11-22 17:56:30 -05001263static struct radeon_asic sumo_asic = {
1264 .init = &evergreen_init,
1265 .fini = &evergreen_fini,
1266 .suspend = &evergreen_suspend,
1267 .resume = &evergreen_resume,
Alex Deucher958261d2010-11-22 17:56:30 -05001268 .asic_reset = &evergreen_asic_reset,
1269 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001270 .ioctl_wait_idle = r600_ioctl_wait_idle,
1271 .gui_idle = &r600_gui_idle,
1272 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001273 .gart = {
1274 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1275 .set_page = &rs600_gart_set_page,
1276 },
Christian König4c87bc22011-10-19 19:02:21 +02001277 .ring = {
1278 [RADEON_RING_TYPE_GFX_INDEX] = {
1279 .ib_execute = &evergreen_ring_ib_execute,
1280 .emit_fence = &r600_fence_ring_emit,
1281 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001282 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001283 .ring_test = &r600_ring_test,
1284 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001285 .is_lockup = &evergreen_gpu_is_lockup,
Christian Königeb0c19c2012-02-23 15:18:44 +01001286 },
Alex Deucher233d1ad2012-12-04 15:25:59 -05001287 [R600_RING_TYPE_DMA_INDEX] = {
1288 .ib_execute = &evergreen_dma_ring_ib_execute,
1289 .emit_fence = &evergreen_dma_fence_ring_emit,
1290 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1291 .cs_parse = NULL,
1292 .ring_test = &r600_dma_ring_test,
1293 .ib_test = &r600_dma_ib_test,
1294 .is_lockup = &r600_dma_is_lockup,
1295 }
Christian König4c87bc22011-10-19 19:02:21 +02001296 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001297 .irq = {
1298 .set = &evergreen_irq_set,
1299 .process = &evergreen_irq_process,
1300 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001301 .display = {
1302 .bandwidth_update = &evergreen_bandwidth_update,
1303 .get_vblank_counter = &evergreen_get_vblank_counter,
1304 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001305 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -04001306 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001307 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001308 .copy = {
1309 .blit = &r600_copy_blit,
1310 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
Alex Deucher233d1ad2012-12-04 15:25:59 -05001311 .dma = &evergreen_copy_dma,
1312 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
Alex Deucher27cd7762012-02-23 17:53:42 -05001313 .copy = &r600_copy_blit,
1314 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1315 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001316 .surface = {
1317 .set_reg = r600_set_surface_reg,
1318 .clear_reg = r600_clear_surface_reg,
1319 },
Alex Deucher901ea572012-02-23 17:53:39 -05001320 .hpd = {
1321 .init = &evergreen_hpd_init,
1322 .fini = &evergreen_hpd_fini,
1323 .sense = &evergreen_hpd_sense,
1324 .set_polarity = &evergreen_hpd_set_polarity,
1325 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001326 .pm = {
1327 .misc = &evergreen_pm_misc,
1328 .prepare = &evergreen_pm_prepare,
1329 .finish = &evergreen_pm_finish,
1330 .init_profile = &sumo_pm_init_profile,
1331 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001332 .get_engine_clock = &radeon_atom_get_engine_clock,
1333 .set_engine_clock = &radeon_atom_set_engine_clock,
1334 .get_memory_clock = NULL,
1335 .set_memory_clock = NULL,
1336 .get_pcie_lanes = NULL,
1337 .set_pcie_lanes = NULL,
1338 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001339 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001340 .pflip = {
1341 .pre_page_flip = &evergreen_pre_page_flip,
1342 .page_flip = &evergreen_page_flip,
1343 .post_page_flip = &evergreen_post_page_flip,
1344 },
Alex Deucher958261d2010-11-22 17:56:30 -05001345};
1346
Alex Deuchera43b7662011-01-06 21:19:33 -05001347static struct radeon_asic btc_asic = {
1348 .init = &evergreen_init,
1349 .fini = &evergreen_fini,
1350 .suspend = &evergreen_suspend,
1351 .resume = &evergreen_resume,
Alex Deuchera43b7662011-01-06 21:19:33 -05001352 .asic_reset = &evergreen_asic_reset,
1353 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001354 .ioctl_wait_idle = r600_ioctl_wait_idle,
1355 .gui_idle = &r600_gui_idle,
1356 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001357 .gart = {
1358 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1359 .set_page = &rs600_gart_set_page,
1360 },
Christian König4c87bc22011-10-19 19:02:21 +02001361 .ring = {
1362 [RADEON_RING_TYPE_GFX_INDEX] = {
1363 .ib_execute = &evergreen_ring_ib_execute,
1364 .emit_fence = &r600_fence_ring_emit,
1365 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001366 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001367 .ring_test = &r600_ring_test,
1368 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001369 .is_lockup = &evergreen_gpu_is_lockup,
Alex Deucher233d1ad2012-12-04 15:25:59 -05001370 },
1371 [R600_RING_TYPE_DMA_INDEX] = {
1372 .ib_execute = &evergreen_dma_ring_ib_execute,
1373 .emit_fence = &evergreen_dma_fence_ring_emit,
1374 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1375 .cs_parse = NULL,
1376 .ring_test = &r600_dma_ring_test,
1377 .ib_test = &r600_dma_ib_test,
1378 .is_lockup = &r600_dma_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001379 }
1380 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001381 .irq = {
1382 .set = &evergreen_irq_set,
1383 .process = &evergreen_irq_process,
1384 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001385 .display = {
1386 .bandwidth_update = &evergreen_bandwidth_update,
1387 .get_vblank_counter = &evergreen_get_vblank_counter,
1388 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001389 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -04001390 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001391 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001392 .copy = {
1393 .blit = &r600_copy_blit,
1394 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
Alex Deucher233d1ad2012-12-04 15:25:59 -05001395 .dma = &evergreen_copy_dma,
1396 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
Alex Deucher27cd7762012-02-23 17:53:42 -05001397 .copy = &r600_copy_blit,
1398 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1399 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001400 .surface = {
1401 .set_reg = r600_set_surface_reg,
1402 .clear_reg = r600_clear_surface_reg,
1403 },
Alex Deucher901ea572012-02-23 17:53:39 -05001404 .hpd = {
1405 .init = &evergreen_hpd_init,
1406 .fini = &evergreen_hpd_fini,
1407 .sense = &evergreen_hpd_sense,
1408 .set_polarity = &evergreen_hpd_set_polarity,
1409 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001410 .pm = {
1411 .misc = &evergreen_pm_misc,
1412 .prepare = &evergreen_pm_prepare,
1413 .finish = &evergreen_pm_finish,
Alex Deucher27810fb2012-10-01 19:25:11 -04001414 .init_profile = &btc_pm_init_profile,
Alex Deuchera02fa392012-02-23 17:53:41 -05001415 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001416 .get_engine_clock = &radeon_atom_get_engine_clock,
1417 .set_engine_clock = &radeon_atom_set_engine_clock,
1418 .get_memory_clock = &radeon_atom_get_memory_clock,
1419 .set_memory_clock = &radeon_atom_set_memory_clock,
1420 .get_pcie_lanes = NULL,
1421 .set_pcie_lanes = NULL,
1422 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001423 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001424 .pflip = {
1425 .pre_page_flip = &evergreen_pre_page_flip,
1426 .page_flip = &evergreen_page_flip,
1427 .post_page_flip = &evergreen_post_page_flip,
1428 },
Alex Deuchera43b7662011-01-06 21:19:33 -05001429};
1430
Alex Deuchere3487622011-03-02 20:07:36 -05001431static struct radeon_asic cayman_asic = {
1432 .init = &cayman_init,
1433 .fini = &cayman_fini,
1434 .suspend = &cayman_suspend,
1435 .resume = &cayman_resume,
Alex Deuchere3487622011-03-02 20:07:36 -05001436 .asic_reset = &cayman_asic_reset,
1437 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001438 .ioctl_wait_idle = r600_ioctl_wait_idle,
1439 .gui_idle = &r600_gui_idle,
1440 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001441 .gart = {
1442 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1443 .set_page = &rs600_gart_set_page,
1444 },
Christian König05b07142012-08-06 20:21:10 +02001445 .vm = {
1446 .init = &cayman_vm_init,
1447 .fini = &cayman_vm_fini,
Christian König2a6f1ab2012-08-11 15:00:30 +02001448 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
Christian König05b07142012-08-06 20:21:10 +02001449 .set_page = &cayman_vm_set_page,
1450 },
Christian König4c87bc22011-10-19 19:02:21 +02001451 .ring = {
1452 [RADEON_RING_TYPE_GFX_INDEX] = {
Jerome Glisse721604a2012-01-05 22:11:05 -05001453 .ib_execute = &cayman_ring_ib_execute,
1454 .ib_parse = &evergreen_ib_parse,
Alex Deucherb40e7e12011-11-17 14:57:50 -05001455 .emit_fence = &cayman_fence_ring_emit,
Christian König4c87bc22011-10-19 19:02:21 +02001456 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001457 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001458 .ring_test = &r600_ring_test,
1459 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001460 .is_lockup = &evergreen_gpu_is_lockup,
Christian König9b40e5d2012-08-08 12:22:43 +02001461 .vm_flush = &cayman_vm_flush,
Christian König4c87bc22011-10-19 19:02:21 +02001462 },
1463 [CAYMAN_RING_TYPE_CP1_INDEX] = {
Jerome Glisse721604a2012-01-05 22:11:05 -05001464 .ib_execute = &cayman_ring_ib_execute,
1465 .ib_parse = &evergreen_ib_parse,
Alex Deucherb40e7e12011-11-17 14:57:50 -05001466 .emit_fence = &cayman_fence_ring_emit,
Christian König4c87bc22011-10-19 19:02:21 +02001467 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001468 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001469 .ring_test = &r600_ring_test,
1470 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001471 .is_lockup = &evergreen_gpu_is_lockup,
Christian König9b40e5d2012-08-08 12:22:43 +02001472 .vm_flush = &cayman_vm_flush,
Christian König4c87bc22011-10-19 19:02:21 +02001473 },
1474 [CAYMAN_RING_TYPE_CP2_INDEX] = {
Jerome Glisse721604a2012-01-05 22:11:05 -05001475 .ib_execute = &cayman_ring_ib_execute,
1476 .ib_parse = &evergreen_ib_parse,
Alex Deucherb40e7e12011-11-17 14:57:50 -05001477 .emit_fence = &cayman_fence_ring_emit,
Christian König4c87bc22011-10-19 19:02:21 +02001478 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001479 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001480 .ring_test = &r600_ring_test,
1481 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001482 .is_lockup = &evergreen_gpu_is_lockup,
Christian König9b40e5d2012-08-08 12:22:43 +02001483 .vm_flush = &cayman_vm_flush,
Christian König4c87bc22011-10-19 19:02:21 +02001484 }
1485 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001486 .irq = {
1487 .set = &evergreen_irq_set,
1488 .process = &evergreen_irq_process,
1489 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001490 .display = {
1491 .bandwidth_update = &evergreen_bandwidth_update,
1492 .get_vblank_counter = &evergreen_get_vblank_counter,
1493 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001494 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -04001495 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001496 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001497 .copy = {
1498 .blit = &r600_copy_blit,
1499 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1500 .dma = NULL,
1501 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1502 .copy = &r600_copy_blit,
1503 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1504 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001505 .surface = {
1506 .set_reg = r600_set_surface_reg,
1507 .clear_reg = r600_clear_surface_reg,
1508 },
Alex Deucher901ea572012-02-23 17:53:39 -05001509 .hpd = {
1510 .init = &evergreen_hpd_init,
1511 .fini = &evergreen_hpd_fini,
1512 .sense = &evergreen_hpd_sense,
1513 .set_polarity = &evergreen_hpd_set_polarity,
1514 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001515 .pm = {
1516 .misc = &evergreen_pm_misc,
1517 .prepare = &evergreen_pm_prepare,
1518 .finish = &evergreen_pm_finish,
Alex Deucher27810fb2012-10-01 19:25:11 -04001519 .init_profile = &btc_pm_init_profile,
Alex Deuchera02fa392012-02-23 17:53:41 -05001520 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001521 .get_engine_clock = &radeon_atom_get_engine_clock,
1522 .set_engine_clock = &radeon_atom_set_engine_clock,
1523 .get_memory_clock = &radeon_atom_get_memory_clock,
1524 .set_memory_clock = &radeon_atom_set_memory_clock,
1525 .get_pcie_lanes = NULL,
1526 .set_pcie_lanes = NULL,
1527 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001528 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001529 .pflip = {
1530 .pre_page_flip = &evergreen_pre_page_flip,
1531 .page_flip = &evergreen_page_flip,
1532 .post_page_flip = &evergreen_post_page_flip,
1533 },
Alex Deuchere3487622011-03-02 20:07:36 -05001534};
1535
Alex Deucherbe63fe82012-03-20 17:18:40 -04001536static struct radeon_asic trinity_asic = {
1537 .init = &cayman_init,
1538 .fini = &cayman_fini,
1539 .suspend = &cayman_suspend,
1540 .resume = &cayman_resume,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001541 .asic_reset = &cayman_asic_reset,
1542 .vga_set_state = &r600_vga_set_state,
1543 .ioctl_wait_idle = r600_ioctl_wait_idle,
1544 .gui_idle = &r600_gui_idle,
1545 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1546 .gart = {
1547 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1548 .set_page = &rs600_gart_set_page,
1549 },
Christian König05b07142012-08-06 20:21:10 +02001550 .vm = {
1551 .init = &cayman_vm_init,
1552 .fini = &cayman_vm_fini,
Christian König2a6f1ab2012-08-11 15:00:30 +02001553 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
Christian König05b07142012-08-06 20:21:10 +02001554 .set_page = &cayman_vm_set_page,
1555 },
Alex Deucherbe63fe82012-03-20 17:18:40 -04001556 .ring = {
1557 [RADEON_RING_TYPE_GFX_INDEX] = {
1558 .ib_execute = &cayman_ring_ib_execute,
1559 .ib_parse = &evergreen_ib_parse,
1560 .emit_fence = &cayman_fence_ring_emit,
1561 .emit_semaphore = &r600_semaphore_ring_emit,
1562 .cs_parse = &evergreen_cs_parse,
1563 .ring_test = &r600_ring_test,
1564 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001565 .is_lockup = &evergreen_gpu_is_lockup,
Christian König9b40e5d2012-08-08 12:22:43 +02001566 .vm_flush = &cayman_vm_flush,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001567 },
1568 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1569 .ib_execute = &cayman_ring_ib_execute,
1570 .ib_parse = &evergreen_ib_parse,
1571 .emit_fence = &cayman_fence_ring_emit,
1572 .emit_semaphore = &r600_semaphore_ring_emit,
1573 .cs_parse = &evergreen_cs_parse,
1574 .ring_test = &r600_ring_test,
1575 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001576 .is_lockup = &evergreen_gpu_is_lockup,
Christian König9b40e5d2012-08-08 12:22:43 +02001577 .vm_flush = &cayman_vm_flush,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001578 },
1579 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1580 .ib_execute = &cayman_ring_ib_execute,
1581 .ib_parse = &evergreen_ib_parse,
1582 .emit_fence = &cayman_fence_ring_emit,
1583 .emit_semaphore = &r600_semaphore_ring_emit,
1584 .cs_parse = &evergreen_cs_parse,
1585 .ring_test = &r600_ring_test,
1586 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001587 .is_lockup = &evergreen_gpu_is_lockup,
Christian König9b40e5d2012-08-08 12:22:43 +02001588 .vm_flush = &cayman_vm_flush,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001589 }
1590 },
1591 .irq = {
1592 .set = &evergreen_irq_set,
1593 .process = &evergreen_irq_process,
1594 },
1595 .display = {
1596 .bandwidth_update = &dce6_bandwidth_update,
1597 .get_vblank_counter = &evergreen_get_vblank_counter,
1598 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001599 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -04001600 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001601 },
1602 .copy = {
1603 .blit = &r600_copy_blit,
1604 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1605 .dma = NULL,
1606 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1607 .copy = &r600_copy_blit,
1608 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1609 },
1610 .surface = {
1611 .set_reg = r600_set_surface_reg,
1612 .clear_reg = r600_clear_surface_reg,
1613 },
1614 .hpd = {
1615 .init = &evergreen_hpd_init,
1616 .fini = &evergreen_hpd_fini,
1617 .sense = &evergreen_hpd_sense,
1618 .set_polarity = &evergreen_hpd_set_polarity,
1619 },
1620 .pm = {
1621 .misc = &evergreen_pm_misc,
1622 .prepare = &evergreen_pm_prepare,
1623 .finish = &evergreen_pm_finish,
1624 .init_profile = &sumo_pm_init_profile,
1625 .get_dynpm_state = &r600_pm_get_dynpm_state,
1626 .get_engine_clock = &radeon_atom_get_engine_clock,
1627 .set_engine_clock = &radeon_atom_set_engine_clock,
1628 .get_memory_clock = NULL,
1629 .set_memory_clock = NULL,
1630 .get_pcie_lanes = NULL,
1631 .set_pcie_lanes = NULL,
1632 .set_clock_gating = NULL,
1633 },
1634 .pflip = {
1635 .pre_page_flip = &evergreen_pre_page_flip,
1636 .page_flip = &evergreen_page_flip,
1637 .post_page_flip = &evergreen_post_page_flip,
1638 },
1639};
1640
Alex Deucher02779c02012-03-20 17:18:25 -04001641static struct radeon_asic si_asic = {
1642 .init = &si_init,
1643 .fini = &si_fini,
1644 .suspend = &si_suspend,
1645 .resume = &si_resume,
Alex Deucher02779c02012-03-20 17:18:25 -04001646 .asic_reset = &si_asic_reset,
1647 .vga_set_state = &r600_vga_set_state,
1648 .ioctl_wait_idle = r600_ioctl_wait_idle,
1649 .gui_idle = &r600_gui_idle,
1650 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1651 .gart = {
1652 .tlb_flush = &si_pcie_gart_tlb_flush,
1653 .set_page = &rs600_gart_set_page,
1654 },
Christian König05b07142012-08-06 20:21:10 +02001655 .vm = {
1656 .init = &si_vm_init,
1657 .fini = &si_vm_fini,
Christian König2a6f1ab2012-08-11 15:00:30 +02001658 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
Alex Deucher82ffd922012-10-02 14:47:46 -04001659 .set_page = &si_vm_set_page,
Christian König05b07142012-08-06 20:21:10 +02001660 },
Alex Deucher02779c02012-03-20 17:18:25 -04001661 .ring = {
1662 [RADEON_RING_TYPE_GFX_INDEX] = {
1663 .ib_execute = &si_ring_ib_execute,
1664 .ib_parse = &si_ib_parse,
1665 .emit_fence = &si_fence_ring_emit,
1666 .emit_semaphore = &r600_semaphore_ring_emit,
1667 .cs_parse = NULL,
1668 .ring_test = &r600_ring_test,
1669 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001670 .is_lockup = &si_gpu_is_lockup,
Christian Königee60e292012-08-09 16:21:08 +02001671 .vm_flush = &si_vm_flush,
Alex Deucher02779c02012-03-20 17:18:25 -04001672 },
1673 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1674 .ib_execute = &si_ring_ib_execute,
1675 .ib_parse = &si_ib_parse,
1676 .emit_fence = &si_fence_ring_emit,
1677 .emit_semaphore = &r600_semaphore_ring_emit,
1678 .cs_parse = NULL,
1679 .ring_test = &r600_ring_test,
1680 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001681 .is_lockup = &si_gpu_is_lockup,
Christian Königee60e292012-08-09 16:21:08 +02001682 .vm_flush = &si_vm_flush,
Alex Deucher02779c02012-03-20 17:18:25 -04001683 },
1684 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1685 .ib_execute = &si_ring_ib_execute,
1686 .ib_parse = &si_ib_parse,
1687 .emit_fence = &si_fence_ring_emit,
1688 .emit_semaphore = &r600_semaphore_ring_emit,
1689 .cs_parse = NULL,
1690 .ring_test = &r600_ring_test,
1691 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001692 .is_lockup = &si_gpu_is_lockup,
Christian Königee60e292012-08-09 16:21:08 +02001693 .vm_flush = &si_vm_flush,
Alex Deucher02779c02012-03-20 17:18:25 -04001694 }
1695 },
1696 .irq = {
1697 .set = &si_irq_set,
1698 .process = &si_irq_process,
1699 },
1700 .display = {
1701 .bandwidth_update = &dce6_bandwidth_update,
1702 .get_vblank_counter = &evergreen_get_vblank_counter,
1703 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001704 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher6d92f812012-09-14 09:59:26 -04001705 .get_backlight_level = &atombios_get_backlight_level,
Alex Deucher02779c02012-03-20 17:18:25 -04001706 },
1707 .copy = {
1708 .blit = NULL,
1709 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1710 .dma = NULL,
1711 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1712 .copy = NULL,
1713 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1714 },
1715 .surface = {
1716 .set_reg = r600_set_surface_reg,
1717 .clear_reg = r600_clear_surface_reg,
1718 },
1719 .hpd = {
1720 .init = &evergreen_hpd_init,
1721 .fini = &evergreen_hpd_fini,
1722 .sense = &evergreen_hpd_sense,
1723 .set_polarity = &evergreen_hpd_set_polarity,
1724 },
1725 .pm = {
1726 .misc = &evergreen_pm_misc,
1727 .prepare = &evergreen_pm_prepare,
1728 .finish = &evergreen_pm_finish,
1729 .init_profile = &sumo_pm_init_profile,
1730 .get_dynpm_state = &r600_pm_get_dynpm_state,
1731 .get_engine_clock = &radeon_atom_get_engine_clock,
1732 .set_engine_clock = &radeon_atom_set_engine_clock,
1733 .get_memory_clock = &radeon_atom_get_memory_clock,
1734 .set_memory_clock = &radeon_atom_set_memory_clock,
1735 .get_pcie_lanes = NULL,
1736 .set_pcie_lanes = NULL,
1737 .set_clock_gating = NULL,
1738 },
1739 .pflip = {
1740 .pre_page_flip = &evergreen_pre_page_flip,
1741 .page_flip = &evergreen_page_flip,
1742 .post_page_flip = &evergreen_post_page_flip,
1743 },
1744};
1745
Alex Deucherabf1dc62012-07-17 14:02:36 -04001746/**
1747 * radeon_asic_init - register asic specific callbacks
1748 *
1749 * @rdev: radeon device pointer
1750 *
1751 * Registers the appropriate asic specific callbacks for each
1752 * chip family. Also sets other asics specific info like the number
1753 * of crtcs and the register aperture accessors (all asics).
1754 * Returns 0 for success.
1755 */
Daniel Vetter0a10c852010-03-11 21:19:14 +00001756int radeon_asic_init(struct radeon_device *rdev)
1757{
1758 radeon_register_accessor_init(rdev);
Alex Deucherba7e05e2011-06-16 18:14:22 +00001759
1760 /* set the number of crtcs */
1761 if (rdev->flags & RADEON_SINGLE_CRTC)
1762 rdev->num_crtc = 1;
1763 else
1764 rdev->num_crtc = 2;
1765
Daniel Vetter0a10c852010-03-11 21:19:14 +00001766 switch (rdev->family) {
1767 case CHIP_R100:
1768 case CHIP_RV100:
1769 case CHIP_RS100:
1770 case CHIP_RV200:
1771 case CHIP_RS200:
1772 rdev->asic = &r100_asic;
1773 break;
1774 case CHIP_R200:
1775 case CHIP_RV250:
1776 case CHIP_RS300:
1777 case CHIP_RV280:
1778 rdev->asic = &r200_asic;
1779 break;
1780 case CHIP_R300:
1781 case CHIP_R350:
1782 case CHIP_RV350:
1783 case CHIP_RV380:
1784 if (rdev->flags & RADEON_IS_PCIE)
1785 rdev->asic = &r300_asic_pcie;
1786 else
1787 rdev->asic = &r300_asic;
1788 break;
1789 case CHIP_R420:
1790 case CHIP_R423:
1791 case CHIP_RV410:
1792 rdev->asic = &r420_asic;
Alex Deucher07bb0842010-06-22 21:58:26 -04001793 /* handle macs */
1794 if (rdev->bios == NULL) {
Alex Deucher798bcf72012-02-23 17:53:48 -05001795 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1796 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1797 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1798 rdev->asic->pm.set_memory_clock = NULL;
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001799 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
Alex Deucher07bb0842010-06-22 21:58:26 -04001800 }
Daniel Vetter0a10c852010-03-11 21:19:14 +00001801 break;
1802 case CHIP_RS400:
1803 case CHIP_RS480:
1804 rdev->asic = &rs400_asic;
1805 break;
1806 case CHIP_RS600:
1807 rdev->asic = &rs600_asic;
1808 break;
1809 case CHIP_RS690:
1810 case CHIP_RS740:
1811 rdev->asic = &rs690_asic;
1812 break;
1813 case CHIP_RV515:
1814 rdev->asic = &rv515_asic;
1815 break;
1816 case CHIP_R520:
1817 case CHIP_RV530:
1818 case CHIP_RV560:
1819 case CHIP_RV570:
1820 case CHIP_R580:
1821 rdev->asic = &r520_asic;
1822 break;
1823 case CHIP_R600:
1824 case CHIP_RV610:
1825 case CHIP_RV630:
1826 case CHIP_RV620:
1827 case CHIP_RV635:
1828 case CHIP_RV670:
Alex Deucherf47299c2010-03-16 20:54:38 -04001829 rdev->asic = &r600_asic;
1830 break;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001831 case CHIP_RS780:
1832 case CHIP_RS880:
Alex Deucherf47299c2010-03-16 20:54:38 -04001833 rdev->asic = &rs780_asic;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001834 break;
1835 case CHIP_RV770:
1836 case CHIP_RV730:
1837 case CHIP_RV710:
1838 case CHIP_RV740:
1839 rdev->asic = &rv770_asic;
1840 break;
1841 case CHIP_CEDAR:
1842 case CHIP_REDWOOD:
1843 case CHIP_JUNIPER:
1844 case CHIP_CYPRESS:
1845 case CHIP_HEMLOCK:
Alex Deucherba7e05e2011-06-16 18:14:22 +00001846 /* set num crtcs */
1847 if (rdev->family == CHIP_CEDAR)
1848 rdev->num_crtc = 4;
1849 else
1850 rdev->num_crtc = 6;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001851 rdev->asic = &evergreen_asic;
1852 break;
Alex Deucher958261d2010-11-22 17:56:30 -05001853 case CHIP_PALM:
Alex Deucher89da5a32011-05-31 15:42:47 -04001854 case CHIP_SUMO:
1855 case CHIP_SUMO2:
Alex Deucher958261d2010-11-22 17:56:30 -05001856 rdev->asic = &sumo_asic;
1857 break;
Alex Deuchera43b7662011-01-06 21:19:33 -05001858 case CHIP_BARTS:
1859 case CHIP_TURKS:
1860 case CHIP_CAICOS:
Alex Deucherba7e05e2011-06-16 18:14:22 +00001861 /* set num crtcs */
1862 if (rdev->family == CHIP_CAICOS)
1863 rdev->num_crtc = 4;
1864 else
1865 rdev->num_crtc = 6;
Alex Deuchera43b7662011-01-06 21:19:33 -05001866 rdev->asic = &btc_asic;
1867 break;
Alex Deuchere3487622011-03-02 20:07:36 -05001868 case CHIP_CAYMAN:
1869 rdev->asic = &cayman_asic;
Alex Deucherba7e05e2011-06-16 18:14:22 +00001870 /* set num crtcs */
1871 rdev->num_crtc = 6;
Alex Deuchere3487622011-03-02 20:07:36 -05001872 break;
Alex Deucherbe63fe82012-03-20 17:18:40 -04001873 case CHIP_ARUBA:
1874 rdev->asic = &trinity_asic;
1875 /* set num crtcs */
1876 rdev->num_crtc = 4;
Alex Deucherbe63fe82012-03-20 17:18:40 -04001877 break;
Alex Deucher02779c02012-03-20 17:18:25 -04001878 case CHIP_TAHITI:
1879 case CHIP_PITCAIRN:
1880 case CHIP_VERDE:
1881 rdev->asic = &si_asic;
1882 /* set num crtcs */
1883 rdev->num_crtc = 6;
Alex Deucher02779c02012-03-20 17:18:25 -04001884 break;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001885 default:
1886 /* FIXME: not supported yet */
1887 return -EINVAL;
1888 }
1889
1890 if (rdev->flags & RADEON_IS_IGP) {
Alex Deucher798bcf72012-02-23 17:53:48 -05001891 rdev->asic->pm.get_memory_clock = NULL;
1892 rdev->asic->pm.set_memory_clock = NULL;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001893 }
1894
Daniel Vetter0a10c852010-03-11 21:19:14 +00001895 return 0;
1896}
1897