Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | |
| 29 | #include <linux/console.h> |
| 30 | #include <drm/drmP.h> |
| 31 | #include <drm/drm_crtc_helper.h> |
| 32 | #include <drm/radeon_drm.h> |
| 33 | #include <linux/vgaarb.h> |
| 34 | #include <linux/vga_switcheroo.h> |
| 35 | #include "radeon_reg.h" |
| 36 | #include "radeon.h" |
| 37 | #include "radeon_asic.h" |
| 38 | #include "atom.h" |
| 39 | |
| 40 | /* |
| 41 | * Registers accessors functions. |
| 42 | */ |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 43 | /** |
| 44 | * radeon_invalid_rreg - dummy reg read function |
| 45 | * |
| 46 | * @rdev: radeon device pointer |
| 47 | * @reg: offset of register |
| 48 | * |
| 49 | * Dummy register read function. Used for register blocks |
| 50 | * that certain asics don't have (all asics). |
| 51 | * Returns the value in the register. |
| 52 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
| 54 | { |
| 55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
| 56 | BUG_ON(1); |
| 57 | return 0; |
| 58 | } |
| 59 | |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 60 | /** |
| 61 | * radeon_invalid_wreg - dummy reg write function |
| 62 | * |
| 63 | * @rdev: radeon device pointer |
| 64 | * @reg: offset of register |
| 65 | * @v: value to write to the register |
| 66 | * |
| 67 | * Dummy register read function. Used for register blocks |
| 68 | * that certain asics don't have (all asics). |
| 69 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 71 | { |
| 72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
| 73 | reg, v); |
| 74 | BUG_ON(1); |
| 75 | } |
| 76 | |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 77 | /** |
| 78 | * radeon_register_accessor_init - sets up the register accessor callbacks |
| 79 | * |
| 80 | * @rdev: radeon device pointer |
| 81 | * |
| 82 | * Sets up the register accessor callbacks for various register |
| 83 | * apertures. Not all asics have all apertures (all asics). |
| 84 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
| 86 | { |
| 87 | rdev->mc_rreg = &radeon_invalid_rreg; |
| 88 | rdev->mc_wreg = &radeon_invalid_wreg; |
| 89 | rdev->pll_rreg = &radeon_invalid_rreg; |
| 90 | rdev->pll_wreg = &radeon_invalid_wreg; |
| 91 | rdev->pciep_rreg = &radeon_invalid_rreg; |
| 92 | rdev->pciep_wreg = &radeon_invalid_wreg; |
| 93 | |
| 94 | /* Don't change order as we are overridding accessor. */ |
| 95 | if (rdev->family < CHIP_RV515) { |
| 96 | rdev->pcie_reg_mask = 0xff; |
| 97 | } else { |
| 98 | rdev->pcie_reg_mask = 0x7ff; |
| 99 | } |
| 100 | /* FIXME: not sure here */ |
| 101 | if (rdev->family <= CHIP_R580) { |
| 102 | rdev->pll_rreg = &r100_pll_rreg; |
| 103 | rdev->pll_wreg = &r100_pll_wreg; |
| 104 | } |
| 105 | if (rdev->family >= CHIP_R420) { |
| 106 | rdev->mc_rreg = &r420_mc_rreg; |
| 107 | rdev->mc_wreg = &r420_mc_wreg; |
| 108 | } |
| 109 | if (rdev->family >= CHIP_RV515) { |
| 110 | rdev->mc_rreg = &rv515_mc_rreg; |
| 111 | rdev->mc_wreg = &rv515_mc_wreg; |
| 112 | } |
| 113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
| 114 | rdev->mc_rreg = &rs400_mc_rreg; |
| 115 | rdev->mc_wreg = &rs400_mc_wreg; |
| 116 | } |
| 117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
| 118 | rdev->mc_rreg = &rs690_mc_rreg; |
| 119 | rdev->mc_wreg = &rs690_mc_wreg; |
| 120 | } |
| 121 | if (rdev->family == CHIP_RS600) { |
| 122 | rdev->mc_rreg = &rs600_mc_rreg; |
| 123 | rdev->mc_wreg = &rs600_mc_wreg; |
| 124 | } |
Alex Deucher | b4df8be | 2011-04-12 13:40:18 -0400 | [diff] [blame] | 125 | if (rdev->family >= CHIP_R600) { |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 126 | rdev->pciep_rreg = &r600_pciep_rreg; |
| 127 | rdev->pciep_wreg = &r600_pciep_wreg; |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | |
| 132 | /* helper to disable agp */ |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 133 | /** |
| 134 | * radeon_agp_disable - AGP disable helper function |
| 135 | * |
| 136 | * @rdev: radeon device pointer |
| 137 | * |
| 138 | * Removes AGP flags and changes the gart callbacks on AGP |
| 139 | * cards when using the internal gart rather than AGP (all asics). |
| 140 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 141 | void radeon_agp_disable(struct radeon_device *rdev) |
| 142 | { |
| 143 | rdev->flags &= ~RADEON_IS_AGP; |
| 144 | if (rdev->family >= CHIP_R600) { |
| 145 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
| 146 | rdev->flags |= RADEON_IS_PCIE; |
| 147 | } else if (rdev->family >= CHIP_RV515 || |
| 148 | rdev->family == CHIP_RV380 || |
| 149 | rdev->family == CHIP_RV410 || |
| 150 | rdev->family == CHIP_R423) { |
| 151 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
| 152 | rdev->flags |= RADEON_IS_PCIE; |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 153 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
| 154 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 155 | } else { |
| 156 | DRM_INFO("Forcing AGP to PCI mode\n"); |
| 157 | rdev->flags |= RADEON_IS_PCI; |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 158 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
| 159 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 160 | } |
| 161 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| 162 | } |
| 163 | |
| 164 | /* |
| 165 | * ASIC |
| 166 | */ |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 167 | static struct radeon_asic r100_asic = { |
| 168 | .init = &r100_init, |
| 169 | .fini = &r100_fini, |
| 170 | .suspend = &r100_suspend, |
| 171 | .resume = &r100_resume, |
| 172 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 173 | .asic_reset = &r100_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 174 | .ioctl_wait_idle = NULL, |
| 175 | .gui_idle = &r100_gui_idle, |
| 176 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 177 | .gart = { |
| 178 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 179 | .set_page = &r100_pci_gart_set_page, |
| 180 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 181 | .ring = { |
| 182 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 183 | .ib_execute = &r100_ring_ib_execute, |
| 184 | .emit_fence = &r100_fence_ring_emit, |
| 185 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 186 | .cs_parse = &r100_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 187 | .ring_start = &r100_ring_start, |
| 188 | .ring_test = &r100_ring_test, |
| 189 | .ib_test = &r100_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 190 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 191 | } |
| 192 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 193 | .irq = { |
| 194 | .set = &r100_irq_set, |
| 195 | .process = &r100_irq_process, |
| 196 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 197 | .display = { |
| 198 | .bandwidth_update = &r100_bandwidth_update, |
| 199 | .get_vblank_counter = &r100_get_vblank_counter, |
| 200 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 201 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 202 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 203 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 204 | .copy = { |
| 205 | .blit = &r100_copy_blit, |
| 206 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 207 | .dma = NULL, |
| 208 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 209 | .copy = &r100_copy_blit, |
| 210 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 211 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 212 | .surface = { |
| 213 | .set_reg = r100_set_surface_reg, |
| 214 | .clear_reg = r100_clear_surface_reg, |
| 215 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 216 | .hpd = { |
| 217 | .init = &r100_hpd_init, |
| 218 | .fini = &r100_hpd_fini, |
| 219 | .sense = &r100_hpd_sense, |
| 220 | .set_polarity = &r100_hpd_set_polarity, |
| 221 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 222 | .pm = { |
| 223 | .misc = &r100_pm_misc, |
| 224 | .prepare = &r100_pm_prepare, |
| 225 | .finish = &r100_pm_finish, |
| 226 | .init_profile = &r100_pm_init_profile, |
| 227 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 228 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 229 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 230 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 231 | .set_memory_clock = NULL, |
| 232 | .get_pcie_lanes = NULL, |
| 233 | .set_pcie_lanes = NULL, |
| 234 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 235 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 236 | .pflip = { |
| 237 | .pre_page_flip = &r100_pre_page_flip, |
| 238 | .page_flip = &r100_page_flip, |
| 239 | .post_page_flip = &r100_post_page_flip, |
| 240 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 241 | }; |
| 242 | |
| 243 | static struct radeon_asic r200_asic = { |
| 244 | .init = &r100_init, |
| 245 | .fini = &r100_fini, |
| 246 | .suspend = &r100_suspend, |
| 247 | .resume = &r100_resume, |
| 248 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 249 | .asic_reset = &r100_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 250 | .ioctl_wait_idle = NULL, |
| 251 | .gui_idle = &r100_gui_idle, |
| 252 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 253 | .gart = { |
| 254 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 255 | .set_page = &r100_pci_gart_set_page, |
| 256 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 257 | .ring = { |
| 258 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 259 | .ib_execute = &r100_ring_ib_execute, |
| 260 | .emit_fence = &r100_fence_ring_emit, |
| 261 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 262 | .cs_parse = &r100_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 263 | .ring_start = &r100_ring_start, |
| 264 | .ring_test = &r100_ring_test, |
| 265 | .ib_test = &r100_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 266 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 267 | } |
| 268 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 269 | .irq = { |
| 270 | .set = &r100_irq_set, |
| 271 | .process = &r100_irq_process, |
| 272 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 273 | .display = { |
| 274 | .bandwidth_update = &r100_bandwidth_update, |
| 275 | .get_vblank_counter = &r100_get_vblank_counter, |
| 276 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 277 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 278 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 279 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 280 | .copy = { |
| 281 | .blit = &r100_copy_blit, |
| 282 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 283 | .dma = &r200_copy_dma, |
| 284 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 285 | .copy = &r100_copy_blit, |
| 286 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 287 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 288 | .surface = { |
| 289 | .set_reg = r100_set_surface_reg, |
| 290 | .clear_reg = r100_clear_surface_reg, |
| 291 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 292 | .hpd = { |
| 293 | .init = &r100_hpd_init, |
| 294 | .fini = &r100_hpd_fini, |
| 295 | .sense = &r100_hpd_sense, |
| 296 | .set_polarity = &r100_hpd_set_polarity, |
| 297 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 298 | .pm = { |
| 299 | .misc = &r100_pm_misc, |
| 300 | .prepare = &r100_pm_prepare, |
| 301 | .finish = &r100_pm_finish, |
| 302 | .init_profile = &r100_pm_init_profile, |
| 303 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 304 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 305 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 306 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 307 | .set_memory_clock = NULL, |
| 308 | .get_pcie_lanes = NULL, |
| 309 | .set_pcie_lanes = NULL, |
| 310 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 311 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 312 | .pflip = { |
| 313 | .pre_page_flip = &r100_pre_page_flip, |
| 314 | .page_flip = &r100_page_flip, |
| 315 | .post_page_flip = &r100_post_page_flip, |
| 316 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 317 | }; |
| 318 | |
| 319 | static struct radeon_asic r300_asic = { |
| 320 | .init = &r300_init, |
| 321 | .fini = &r300_fini, |
| 322 | .suspend = &r300_suspend, |
| 323 | .resume = &r300_resume, |
| 324 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 325 | .asic_reset = &r300_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 326 | .ioctl_wait_idle = NULL, |
| 327 | .gui_idle = &r100_gui_idle, |
| 328 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 329 | .gart = { |
| 330 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 331 | .set_page = &r100_pci_gart_set_page, |
| 332 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 333 | .ring = { |
| 334 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 335 | .ib_execute = &r100_ring_ib_execute, |
| 336 | .emit_fence = &r300_fence_ring_emit, |
| 337 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 338 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 339 | .ring_start = &r300_ring_start, |
| 340 | .ring_test = &r100_ring_test, |
| 341 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b5 | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 342 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 343 | } |
| 344 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 345 | .irq = { |
| 346 | .set = &r100_irq_set, |
| 347 | .process = &r100_irq_process, |
| 348 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 349 | .display = { |
| 350 | .bandwidth_update = &r100_bandwidth_update, |
| 351 | .get_vblank_counter = &r100_get_vblank_counter, |
| 352 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 353 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 354 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 355 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 356 | .copy = { |
| 357 | .blit = &r100_copy_blit, |
| 358 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 359 | .dma = &r200_copy_dma, |
| 360 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 361 | .copy = &r100_copy_blit, |
| 362 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 363 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 364 | .surface = { |
| 365 | .set_reg = r100_set_surface_reg, |
| 366 | .clear_reg = r100_clear_surface_reg, |
| 367 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 368 | .hpd = { |
| 369 | .init = &r100_hpd_init, |
| 370 | .fini = &r100_hpd_fini, |
| 371 | .sense = &r100_hpd_sense, |
| 372 | .set_polarity = &r100_hpd_set_polarity, |
| 373 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 374 | .pm = { |
| 375 | .misc = &r100_pm_misc, |
| 376 | .prepare = &r100_pm_prepare, |
| 377 | .finish = &r100_pm_finish, |
| 378 | .init_profile = &r100_pm_init_profile, |
| 379 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 380 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 381 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 382 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 383 | .set_memory_clock = NULL, |
| 384 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 385 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 386 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 387 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 388 | .pflip = { |
| 389 | .pre_page_flip = &r100_pre_page_flip, |
| 390 | .page_flip = &r100_page_flip, |
| 391 | .post_page_flip = &r100_post_page_flip, |
| 392 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 393 | }; |
| 394 | |
| 395 | static struct radeon_asic r300_asic_pcie = { |
| 396 | .init = &r300_init, |
| 397 | .fini = &r300_fini, |
| 398 | .suspend = &r300_suspend, |
| 399 | .resume = &r300_resume, |
| 400 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 401 | .asic_reset = &r300_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 402 | .ioctl_wait_idle = NULL, |
| 403 | .gui_idle = &r100_gui_idle, |
| 404 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 405 | .gart = { |
| 406 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 407 | .set_page = &rv370_pcie_gart_set_page, |
| 408 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 409 | .ring = { |
| 410 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 411 | .ib_execute = &r100_ring_ib_execute, |
| 412 | .emit_fence = &r300_fence_ring_emit, |
| 413 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 414 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 415 | .ring_start = &r300_ring_start, |
| 416 | .ring_test = &r100_ring_test, |
| 417 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b5 | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 418 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 419 | } |
| 420 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 421 | .irq = { |
| 422 | .set = &r100_irq_set, |
| 423 | .process = &r100_irq_process, |
| 424 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 425 | .display = { |
| 426 | .bandwidth_update = &r100_bandwidth_update, |
| 427 | .get_vblank_counter = &r100_get_vblank_counter, |
| 428 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 429 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 430 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 431 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 432 | .copy = { |
| 433 | .blit = &r100_copy_blit, |
| 434 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 435 | .dma = &r200_copy_dma, |
| 436 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 437 | .copy = &r100_copy_blit, |
| 438 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 439 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 440 | .surface = { |
| 441 | .set_reg = r100_set_surface_reg, |
| 442 | .clear_reg = r100_clear_surface_reg, |
| 443 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 444 | .hpd = { |
| 445 | .init = &r100_hpd_init, |
| 446 | .fini = &r100_hpd_fini, |
| 447 | .sense = &r100_hpd_sense, |
| 448 | .set_polarity = &r100_hpd_set_polarity, |
| 449 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 450 | .pm = { |
| 451 | .misc = &r100_pm_misc, |
| 452 | .prepare = &r100_pm_prepare, |
| 453 | .finish = &r100_pm_finish, |
| 454 | .init_profile = &r100_pm_init_profile, |
| 455 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 456 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 457 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 458 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 459 | .set_memory_clock = NULL, |
| 460 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 461 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 462 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 463 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 464 | .pflip = { |
| 465 | .pre_page_flip = &r100_pre_page_flip, |
| 466 | .page_flip = &r100_page_flip, |
| 467 | .post_page_flip = &r100_post_page_flip, |
| 468 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 469 | }; |
| 470 | |
| 471 | static struct radeon_asic r420_asic = { |
| 472 | .init = &r420_init, |
| 473 | .fini = &r420_fini, |
| 474 | .suspend = &r420_suspend, |
| 475 | .resume = &r420_resume, |
| 476 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 477 | .asic_reset = &r300_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 478 | .ioctl_wait_idle = NULL, |
| 479 | .gui_idle = &r100_gui_idle, |
| 480 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 481 | .gart = { |
| 482 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 483 | .set_page = &rv370_pcie_gart_set_page, |
| 484 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 485 | .ring = { |
| 486 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 487 | .ib_execute = &r100_ring_ib_execute, |
| 488 | .emit_fence = &r300_fence_ring_emit, |
| 489 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 490 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 491 | .ring_start = &r300_ring_start, |
| 492 | .ring_test = &r100_ring_test, |
| 493 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b5 | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 494 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 495 | } |
| 496 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 497 | .irq = { |
| 498 | .set = &r100_irq_set, |
| 499 | .process = &r100_irq_process, |
| 500 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 501 | .display = { |
| 502 | .bandwidth_update = &r100_bandwidth_update, |
| 503 | .get_vblank_counter = &r100_get_vblank_counter, |
| 504 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 505 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 506 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 507 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 508 | .copy = { |
| 509 | .blit = &r100_copy_blit, |
| 510 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 511 | .dma = &r200_copy_dma, |
| 512 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 513 | .copy = &r100_copy_blit, |
| 514 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 515 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 516 | .surface = { |
| 517 | .set_reg = r100_set_surface_reg, |
| 518 | .clear_reg = r100_clear_surface_reg, |
| 519 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 520 | .hpd = { |
| 521 | .init = &r100_hpd_init, |
| 522 | .fini = &r100_hpd_fini, |
| 523 | .sense = &r100_hpd_sense, |
| 524 | .set_polarity = &r100_hpd_set_polarity, |
| 525 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 526 | .pm = { |
| 527 | .misc = &r100_pm_misc, |
| 528 | .prepare = &r100_pm_prepare, |
| 529 | .finish = &r100_pm_finish, |
| 530 | .init_profile = &r420_pm_init_profile, |
| 531 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 532 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 533 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 534 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 535 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 536 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 537 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 538 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 539 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 540 | .pflip = { |
| 541 | .pre_page_flip = &r100_pre_page_flip, |
| 542 | .page_flip = &r100_page_flip, |
| 543 | .post_page_flip = &r100_post_page_flip, |
| 544 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 545 | }; |
| 546 | |
| 547 | static struct radeon_asic rs400_asic = { |
| 548 | .init = &rs400_init, |
| 549 | .fini = &rs400_fini, |
| 550 | .suspend = &rs400_suspend, |
| 551 | .resume = &rs400_resume, |
| 552 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 553 | .asic_reset = &r300_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 554 | .ioctl_wait_idle = NULL, |
| 555 | .gui_idle = &r100_gui_idle, |
| 556 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 557 | .gart = { |
| 558 | .tlb_flush = &rs400_gart_tlb_flush, |
| 559 | .set_page = &rs400_gart_set_page, |
| 560 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 561 | .ring = { |
| 562 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 563 | .ib_execute = &r100_ring_ib_execute, |
| 564 | .emit_fence = &r300_fence_ring_emit, |
| 565 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 566 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 567 | .ring_start = &r300_ring_start, |
| 568 | .ring_test = &r100_ring_test, |
| 569 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b5 | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 570 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 571 | } |
| 572 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 573 | .irq = { |
| 574 | .set = &r100_irq_set, |
| 575 | .process = &r100_irq_process, |
| 576 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 577 | .display = { |
| 578 | .bandwidth_update = &r100_bandwidth_update, |
| 579 | .get_vblank_counter = &r100_get_vblank_counter, |
| 580 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 581 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 582 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 583 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 584 | .copy = { |
| 585 | .blit = &r100_copy_blit, |
| 586 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 587 | .dma = &r200_copy_dma, |
| 588 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 589 | .copy = &r100_copy_blit, |
| 590 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 591 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 592 | .surface = { |
| 593 | .set_reg = r100_set_surface_reg, |
| 594 | .clear_reg = r100_clear_surface_reg, |
| 595 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 596 | .hpd = { |
| 597 | .init = &r100_hpd_init, |
| 598 | .fini = &r100_hpd_fini, |
| 599 | .sense = &r100_hpd_sense, |
| 600 | .set_polarity = &r100_hpd_set_polarity, |
| 601 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 602 | .pm = { |
| 603 | .misc = &r100_pm_misc, |
| 604 | .prepare = &r100_pm_prepare, |
| 605 | .finish = &r100_pm_finish, |
| 606 | .init_profile = &r100_pm_init_profile, |
| 607 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 608 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 609 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 610 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 611 | .set_memory_clock = NULL, |
| 612 | .get_pcie_lanes = NULL, |
| 613 | .set_pcie_lanes = NULL, |
| 614 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 615 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 616 | .pflip = { |
| 617 | .pre_page_flip = &r100_pre_page_flip, |
| 618 | .page_flip = &r100_page_flip, |
| 619 | .post_page_flip = &r100_post_page_flip, |
| 620 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 621 | }; |
| 622 | |
| 623 | static struct radeon_asic rs600_asic = { |
| 624 | .init = &rs600_init, |
| 625 | .fini = &rs600_fini, |
| 626 | .suspend = &rs600_suspend, |
| 627 | .resume = &rs600_resume, |
| 628 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 629 | .asic_reset = &rs600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 630 | .ioctl_wait_idle = NULL, |
| 631 | .gui_idle = &r100_gui_idle, |
| 632 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 633 | .gart = { |
| 634 | .tlb_flush = &rs600_gart_tlb_flush, |
| 635 | .set_page = &rs600_gart_set_page, |
| 636 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 637 | .ring = { |
| 638 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 639 | .ib_execute = &r100_ring_ib_execute, |
| 640 | .emit_fence = &r300_fence_ring_emit, |
| 641 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 642 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 643 | .ring_start = &r300_ring_start, |
| 644 | .ring_test = &r100_ring_test, |
| 645 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b5 | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 646 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 647 | } |
| 648 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 649 | .irq = { |
| 650 | .set = &rs600_irq_set, |
| 651 | .process = &rs600_irq_process, |
| 652 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 653 | .display = { |
| 654 | .bandwidth_update = &rs600_bandwidth_update, |
| 655 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 656 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 657 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 658 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 659 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 660 | .copy = { |
| 661 | .blit = &r100_copy_blit, |
| 662 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 663 | .dma = &r200_copy_dma, |
| 664 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 665 | .copy = &r100_copy_blit, |
| 666 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 667 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 668 | .surface = { |
| 669 | .set_reg = r100_set_surface_reg, |
| 670 | .clear_reg = r100_clear_surface_reg, |
| 671 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 672 | .hpd = { |
| 673 | .init = &rs600_hpd_init, |
| 674 | .fini = &rs600_hpd_fini, |
| 675 | .sense = &rs600_hpd_sense, |
| 676 | .set_polarity = &rs600_hpd_set_polarity, |
| 677 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 678 | .pm = { |
| 679 | .misc = &rs600_pm_misc, |
| 680 | .prepare = &rs600_pm_prepare, |
| 681 | .finish = &rs600_pm_finish, |
| 682 | .init_profile = &r420_pm_init_profile, |
| 683 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 684 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 685 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 686 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 687 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 688 | .get_pcie_lanes = NULL, |
| 689 | .set_pcie_lanes = NULL, |
| 690 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 691 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 692 | .pflip = { |
| 693 | .pre_page_flip = &rs600_pre_page_flip, |
| 694 | .page_flip = &rs600_page_flip, |
| 695 | .post_page_flip = &rs600_post_page_flip, |
| 696 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 697 | }; |
| 698 | |
| 699 | static struct radeon_asic rs690_asic = { |
| 700 | .init = &rs690_init, |
| 701 | .fini = &rs690_fini, |
| 702 | .suspend = &rs690_suspend, |
| 703 | .resume = &rs690_resume, |
| 704 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 705 | .asic_reset = &rs600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 706 | .ioctl_wait_idle = NULL, |
| 707 | .gui_idle = &r100_gui_idle, |
| 708 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 709 | .gart = { |
| 710 | .tlb_flush = &rs400_gart_tlb_flush, |
| 711 | .set_page = &rs400_gart_set_page, |
| 712 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 713 | .ring = { |
| 714 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 715 | .ib_execute = &r100_ring_ib_execute, |
| 716 | .emit_fence = &r300_fence_ring_emit, |
| 717 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 718 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 719 | .ring_start = &r300_ring_start, |
| 720 | .ring_test = &r100_ring_test, |
| 721 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b5 | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 722 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 723 | } |
| 724 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 725 | .irq = { |
| 726 | .set = &rs600_irq_set, |
| 727 | .process = &rs600_irq_process, |
| 728 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 729 | .display = { |
| 730 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 731 | .bandwidth_update = &rs690_bandwidth_update, |
| 732 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 733 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 734 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 735 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 736 | .copy = { |
| 737 | .blit = &r100_copy_blit, |
| 738 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 739 | .dma = &r200_copy_dma, |
| 740 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 741 | .copy = &r200_copy_dma, |
| 742 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 743 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 744 | .surface = { |
| 745 | .set_reg = r100_set_surface_reg, |
| 746 | .clear_reg = r100_clear_surface_reg, |
| 747 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 748 | .hpd = { |
| 749 | .init = &rs600_hpd_init, |
| 750 | .fini = &rs600_hpd_fini, |
| 751 | .sense = &rs600_hpd_sense, |
| 752 | .set_polarity = &rs600_hpd_set_polarity, |
| 753 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 754 | .pm = { |
| 755 | .misc = &rs600_pm_misc, |
| 756 | .prepare = &rs600_pm_prepare, |
| 757 | .finish = &rs600_pm_finish, |
| 758 | .init_profile = &r420_pm_init_profile, |
| 759 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 760 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 761 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 762 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 763 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 764 | .get_pcie_lanes = NULL, |
| 765 | .set_pcie_lanes = NULL, |
| 766 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 767 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 768 | .pflip = { |
| 769 | .pre_page_flip = &rs600_pre_page_flip, |
| 770 | .page_flip = &rs600_page_flip, |
| 771 | .post_page_flip = &rs600_post_page_flip, |
| 772 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 773 | }; |
| 774 | |
| 775 | static struct radeon_asic rv515_asic = { |
| 776 | .init = &rv515_init, |
| 777 | .fini = &rv515_fini, |
| 778 | .suspend = &rv515_suspend, |
| 779 | .resume = &rv515_resume, |
| 780 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 781 | .asic_reset = &rs600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 782 | .ioctl_wait_idle = NULL, |
| 783 | .gui_idle = &r100_gui_idle, |
| 784 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 785 | .gart = { |
| 786 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 787 | .set_page = &rv370_pcie_gart_set_page, |
| 788 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 789 | .ring = { |
| 790 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 791 | .ib_execute = &r100_ring_ib_execute, |
| 792 | .emit_fence = &r300_fence_ring_emit, |
| 793 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 794 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 795 | .ring_start = &rv515_ring_start, |
| 796 | .ring_test = &r100_ring_test, |
| 797 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b5 | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 798 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 799 | } |
| 800 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 801 | .irq = { |
| 802 | .set = &rs600_irq_set, |
| 803 | .process = &rs600_irq_process, |
| 804 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 805 | .display = { |
| 806 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 807 | .bandwidth_update = &rv515_bandwidth_update, |
| 808 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 809 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 810 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 811 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 812 | .copy = { |
| 813 | .blit = &r100_copy_blit, |
| 814 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 815 | .dma = &r200_copy_dma, |
| 816 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 817 | .copy = &r100_copy_blit, |
| 818 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 819 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 820 | .surface = { |
| 821 | .set_reg = r100_set_surface_reg, |
| 822 | .clear_reg = r100_clear_surface_reg, |
| 823 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 824 | .hpd = { |
| 825 | .init = &rs600_hpd_init, |
| 826 | .fini = &rs600_hpd_fini, |
| 827 | .sense = &rs600_hpd_sense, |
| 828 | .set_polarity = &rs600_hpd_set_polarity, |
| 829 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 830 | .pm = { |
| 831 | .misc = &rs600_pm_misc, |
| 832 | .prepare = &rs600_pm_prepare, |
| 833 | .finish = &rs600_pm_finish, |
| 834 | .init_profile = &r420_pm_init_profile, |
| 835 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 836 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 837 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 838 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 839 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 840 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 841 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 842 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 843 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 844 | .pflip = { |
| 845 | .pre_page_flip = &rs600_pre_page_flip, |
| 846 | .page_flip = &rs600_page_flip, |
| 847 | .post_page_flip = &rs600_post_page_flip, |
| 848 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 849 | }; |
| 850 | |
| 851 | static struct radeon_asic r520_asic = { |
| 852 | .init = &r520_init, |
| 853 | .fini = &rv515_fini, |
| 854 | .suspend = &rv515_suspend, |
| 855 | .resume = &r520_resume, |
| 856 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 857 | .asic_reset = &rs600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 858 | .ioctl_wait_idle = NULL, |
| 859 | .gui_idle = &r100_gui_idle, |
| 860 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 861 | .gart = { |
| 862 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 863 | .set_page = &rv370_pcie_gart_set_page, |
| 864 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 865 | .ring = { |
| 866 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 867 | .ib_execute = &r100_ring_ib_execute, |
| 868 | .emit_fence = &r300_fence_ring_emit, |
| 869 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 870 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 871 | .ring_start = &rv515_ring_start, |
| 872 | .ring_test = &r100_ring_test, |
| 873 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b5 | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 874 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 875 | } |
| 876 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 877 | .irq = { |
| 878 | .set = &rs600_irq_set, |
| 879 | .process = &rs600_irq_process, |
| 880 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 881 | .display = { |
| 882 | .bandwidth_update = &rv515_bandwidth_update, |
| 883 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 884 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 885 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 886 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 887 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 888 | .copy = { |
| 889 | .blit = &r100_copy_blit, |
| 890 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 891 | .dma = &r200_copy_dma, |
| 892 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 893 | .copy = &r100_copy_blit, |
| 894 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 895 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 896 | .surface = { |
| 897 | .set_reg = r100_set_surface_reg, |
| 898 | .clear_reg = r100_clear_surface_reg, |
| 899 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 900 | .hpd = { |
| 901 | .init = &rs600_hpd_init, |
| 902 | .fini = &rs600_hpd_fini, |
| 903 | .sense = &rs600_hpd_sense, |
| 904 | .set_polarity = &rs600_hpd_set_polarity, |
| 905 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 906 | .pm = { |
| 907 | .misc = &rs600_pm_misc, |
| 908 | .prepare = &rs600_pm_prepare, |
| 909 | .finish = &rs600_pm_finish, |
| 910 | .init_profile = &r420_pm_init_profile, |
| 911 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 912 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 913 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 914 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 915 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 916 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 917 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 918 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 919 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 920 | .pflip = { |
| 921 | .pre_page_flip = &rs600_pre_page_flip, |
| 922 | .page_flip = &rs600_page_flip, |
| 923 | .post_page_flip = &rs600_post_page_flip, |
| 924 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 925 | }; |
| 926 | |
| 927 | static struct radeon_asic r600_asic = { |
| 928 | .init = &r600_init, |
| 929 | .fini = &r600_fini, |
| 930 | .suspend = &r600_suspend, |
| 931 | .resume = &r600_resume, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 932 | .vga_set_state = &r600_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 933 | .asic_reset = &r600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 934 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 935 | .gui_idle = &r600_gui_idle, |
| 936 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 937 | .gart = { |
| 938 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 939 | .set_page = &rs600_gart_set_page, |
| 940 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 941 | .ring = { |
| 942 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 943 | .ib_execute = &r600_ring_ib_execute, |
| 944 | .emit_fence = &r600_fence_ring_emit, |
| 945 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 946 | .cs_parse = &r600_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 947 | .ring_test = &r600_ring_test, |
| 948 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 949 | .is_lockup = &r600_gpu_is_lockup, |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 950 | }, |
| 951 | [R600_RING_TYPE_DMA_INDEX] = { |
| 952 | .ib_execute = &r600_dma_ring_ib_execute, |
| 953 | .emit_fence = &r600_dma_fence_ring_emit, |
| 954 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
| 955 | .cs_parse = NULL, |
| 956 | .ring_test = &r600_dma_ring_test, |
| 957 | .ib_test = &r600_dma_ib_test, |
| 958 | .is_lockup = &r600_dma_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 959 | } |
| 960 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 961 | .irq = { |
| 962 | .set = &r600_irq_set, |
| 963 | .process = &r600_irq_process, |
| 964 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 965 | .display = { |
| 966 | .bandwidth_update = &rv515_bandwidth_update, |
| 967 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 968 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 969 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 970 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 971 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 972 | .copy = { |
| 973 | .blit = &r600_copy_blit, |
| 974 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 975 | .dma = &r600_copy_dma, |
| 976 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 977 | .copy = &r600_copy_blit, |
| 978 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 979 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 980 | .surface = { |
| 981 | .set_reg = r600_set_surface_reg, |
| 982 | .clear_reg = r600_clear_surface_reg, |
| 983 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 984 | .hpd = { |
| 985 | .init = &r600_hpd_init, |
| 986 | .fini = &r600_hpd_fini, |
| 987 | .sense = &r600_hpd_sense, |
| 988 | .set_polarity = &r600_hpd_set_polarity, |
| 989 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 990 | .pm = { |
| 991 | .misc = &r600_pm_misc, |
| 992 | .prepare = &rs600_pm_prepare, |
| 993 | .finish = &rs600_pm_finish, |
| 994 | .init_profile = &r600_pm_init_profile, |
| 995 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 996 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 997 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 998 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 999 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1000 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 1001 | .set_pcie_lanes = &r600_set_pcie_lanes, |
| 1002 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1003 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1004 | .pflip = { |
| 1005 | .pre_page_flip = &rs600_pre_page_flip, |
| 1006 | .page_flip = &rs600_page_flip, |
| 1007 | .post_page_flip = &rs600_post_page_flip, |
| 1008 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1009 | }; |
| 1010 | |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1011 | static struct radeon_asic rs780_asic = { |
| 1012 | .init = &r600_init, |
| 1013 | .fini = &r600_fini, |
| 1014 | .suspend = &r600_suspend, |
| 1015 | .resume = &r600_resume, |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1016 | .vga_set_state = &r600_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1017 | .asic_reset = &r600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1018 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1019 | .gui_idle = &r600_gui_idle, |
| 1020 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1021 | .gart = { |
| 1022 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 1023 | .set_page = &rs600_gart_set_page, |
| 1024 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1025 | .ring = { |
| 1026 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1027 | .ib_execute = &r600_ring_ib_execute, |
| 1028 | .emit_fence = &r600_fence_ring_emit, |
| 1029 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1030 | .cs_parse = &r600_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1031 | .ring_test = &r600_ring_test, |
| 1032 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1033 | .is_lockup = &r600_gpu_is_lockup, |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1034 | }, |
| 1035 | [R600_RING_TYPE_DMA_INDEX] = { |
| 1036 | .ib_execute = &r600_dma_ring_ib_execute, |
| 1037 | .emit_fence = &r600_dma_fence_ring_emit, |
| 1038 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
| 1039 | .cs_parse = NULL, |
| 1040 | .ring_test = &r600_dma_ring_test, |
| 1041 | .ib_test = &r600_dma_ib_test, |
| 1042 | .is_lockup = &r600_dma_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1043 | } |
| 1044 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1045 | .irq = { |
| 1046 | .set = &r600_irq_set, |
| 1047 | .process = &r600_irq_process, |
| 1048 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1049 | .display = { |
| 1050 | .bandwidth_update = &rs690_bandwidth_update, |
| 1051 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 1052 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1053 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1054 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1055 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1056 | .copy = { |
| 1057 | .blit = &r600_copy_blit, |
| 1058 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1059 | .dma = &r600_copy_dma, |
| 1060 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1061 | .copy = &r600_copy_blit, |
| 1062 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1063 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1064 | .surface = { |
| 1065 | .set_reg = r600_set_surface_reg, |
| 1066 | .clear_reg = r600_clear_surface_reg, |
| 1067 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1068 | .hpd = { |
| 1069 | .init = &r600_hpd_init, |
| 1070 | .fini = &r600_hpd_fini, |
| 1071 | .sense = &r600_hpd_sense, |
| 1072 | .set_polarity = &r600_hpd_set_polarity, |
| 1073 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1074 | .pm = { |
| 1075 | .misc = &r600_pm_misc, |
| 1076 | .prepare = &rs600_pm_prepare, |
| 1077 | .finish = &rs600_pm_finish, |
| 1078 | .init_profile = &rs780_pm_init_profile, |
| 1079 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1080 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1081 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1082 | .get_memory_clock = NULL, |
| 1083 | .set_memory_clock = NULL, |
| 1084 | .get_pcie_lanes = NULL, |
| 1085 | .set_pcie_lanes = NULL, |
| 1086 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1087 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1088 | .pflip = { |
| 1089 | .pre_page_flip = &rs600_pre_page_flip, |
| 1090 | .page_flip = &rs600_page_flip, |
| 1091 | .post_page_flip = &rs600_post_page_flip, |
| 1092 | }, |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1093 | }; |
| 1094 | |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1095 | static struct radeon_asic rv770_asic = { |
| 1096 | .init = &rv770_init, |
| 1097 | .fini = &rv770_fini, |
| 1098 | .suspend = &rv770_suspend, |
| 1099 | .resume = &rv770_resume, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1100 | .asic_reset = &r600_asic_reset, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1101 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1102 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1103 | .gui_idle = &r600_gui_idle, |
| 1104 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1105 | .gart = { |
| 1106 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 1107 | .set_page = &rs600_gart_set_page, |
| 1108 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1109 | .ring = { |
| 1110 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1111 | .ib_execute = &r600_ring_ib_execute, |
| 1112 | .emit_fence = &r600_fence_ring_emit, |
| 1113 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1114 | .cs_parse = &r600_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1115 | .ring_test = &r600_ring_test, |
| 1116 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1117 | .is_lockup = &r600_gpu_is_lockup, |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1118 | }, |
| 1119 | [R600_RING_TYPE_DMA_INDEX] = { |
| 1120 | .ib_execute = &r600_dma_ring_ib_execute, |
| 1121 | .emit_fence = &r600_dma_fence_ring_emit, |
| 1122 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
| 1123 | .cs_parse = NULL, |
| 1124 | .ring_test = &r600_dma_ring_test, |
| 1125 | .ib_test = &r600_dma_ib_test, |
| 1126 | .is_lockup = &r600_dma_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1127 | } |
| 1128 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1129 | .irq = { |
| 1130 | .set = &r600_irq_set, |
| 1131 | .process = &r600_irq_process, |
| 1132 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1133 | .display = { |
| 1134 | .bandwidth_update = &rv515_bandwidth_update, |
| 1135 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 1136 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1137 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1138 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1139 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1140 | .copy = { |
| 1141 | .blit = &r600_copy_blit, |
| 1142 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1143 | .dma = &r600_copy_dma, |
| 1144 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1145 | .copy = &r600_copy_blit, |
| 1146 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1147 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1148 | .surface = { |
| 1149 | .set_reg = r600_set_surface_reg, |
| 1150 | .clear_reg = r600_clear_surface_reg, |
| 1151 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1152 | .hpd = { |
| 1153 | .init = &r600_hpd_init, |
| 1154 | .fini = &r600_hpd_fini, |
| 1155 | .sense = &r600_hpd_sense, |
| 1156 | .set_polarity = &r600_hpd_set_polarity, |
| 1157 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1158 | .pm = { |
| 1159 | .misc = &rv770_pm_misc, |
| 1160 | .prepare = &rs600_pm_prepare, |
| 1161 | .finish = &rs600_pm_finish, |
| 1162 | .init_profile = &r600_pm_init_profile, |
| 1163 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1164 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1165 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1166 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1167 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1168 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 1169 | .set_pcie_lanes = &r600_set_pcie_lanes, |
| 1170 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1171 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1172 | .pflip = { |
| 1173 | .pre_page_flip = &rs600_pre_page_flip, |
| 1174 | .page_flip = &rv770_page_flip, |
| 1175 | .post_page_flip = &rs600_post_page_flip, |
| 1176 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1177 | }; |
| 1178 | |
| 1179 | static struct radeon_asic evergreen_asic = { |
| 1180 | .init = &evergreen_init, |
| 1181 | .fini = &evergreen_fini, |
| 1182 | .suspend = &evergreen_suspend, |
| 1183 | .resume = &evergreen_resume, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1184 | .asic_reset = &evergreen_asic_reset, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1185 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1186 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1187 | .gui_idle = &r600_gui_idle, |
| 1188 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1189 | .gart = { |
| 1190 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1191 | .set_page = &rs600_gart_set_page, |
| 1192 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1193 | .ring = { |
| 1194 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1195 | .ib_execute = &evergreen_ring_ib_execute, |
| 1196 | .emit_fence = &r600_fence_ring_emit, |
| 1197 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1198 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1199 | .ring_test = &r600_ring_test, |
| 1200 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1201 | .is_lockup = &evergreen_gpu_is_lockup, |
Alex Deucher | 233d1ad | 2012-12-04 15:25:59 -0500 | [diff] [blame^] | 1202 | }, |
| 1203 | [R600_RING_TYPE_DMA_INDEX] = { |
| 1204 | .ib_execute = &evergreen_dma_ring_ib_execute, |
| 1205 | .emit_fence = &evergreen_dma_fence_ring_emit, |
| 1206 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
| 1207 | .cs_parse = NULL, |
| 1208 | .ring_test = &r600_dma_ring_test, |
| 1209 | .ib_test = &r600_dma_ib_test, |
| 1210 | .is_lockup = &r600_dma_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1211 | } |
| 1212 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1213 | .irq = { |
| 1214 | .set = &evergreen_irq_set, |
| 1215 | .process = &evergreen_irq_process, |
| 1216 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1217 | .display = { |
| 1218 | .bandwidth_update = &evergreen_bandwidth_update, |
| 1219 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1220 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1221 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1222 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1223 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1224 | .copy = { |
| 1225 | .blit = &r600_copy_blit, |
| 1226 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Alex Deucher | 233d1ad | 2012-12-04 15:25:59 -0500 | [diff] [blame^] | 1227 | .dma = &evergreen_copy_dma, |
| 1228 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1229 | .copy = &r600_copy_blit, |
| 1230 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1231 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1232 | .surface = { |
| 1233 | .set_reg = r600_set_surface_reg, |
| 1234 | .clear_reg = r600_clear_surface_reg, |
| 1235 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1236 | .hpd = { |
| 1237 | .init = &evergreen_hpd_init, |
| 1238 | .fini = &evergreen_hpd_fini, |
| 1239 | .sense = &evergreen_hpd_sense, |
| 1240 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1241 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1242 | .pm = { |
| 1243 | .misc = &evergreen_pm_misc, |
| 1244 | .prepare = &evergreen_pm_prepare, |
| 1245 | .finish = &evergreen_pm_finish, |
| 1246 | .init_profile = &r600_pm_init_profile, |
| 1247 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1248 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1249 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1250 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1251 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1252 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 1253 | .set_pcie_lanes = &r600_set_pcie_lanes, |
| 1254 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1255 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1256 | .pflip = { |
| 1257 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1258 | .page_flip = &evergreen_page_flip, |
| 1259 | .post_page_flip = &evergreen_post_page_flip, |
| 1260 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1261 | }; |
| 1262 | |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1263 | static struct radeon_asic sumo_asic = { |
| 1264 | .init = &evergreen_init, |
| 1265 | .fini = &evergreen_fini, |
| 1266 | .suspend = &evergreen_suspend, |
| 1267 | .resume = &evergreen_resume, |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1268 | .asic_reset = &evergreen_asic_reset, |
| 1269 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1270 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1271 | .gui_idle = &r600_gui_idle, |
| 1272 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1273 | .gart = { |
| 1274 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1275 | .set_page = &rs600_gart_set_page, |
| 1276 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1277 | .ring = { |
| 1278 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1279 | .ib_execute = &evergreen_ring_ib_execute, |
| 1280 | .emit_fence = &r600_fence_ring_emit, |
| 1281 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1282 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1283 | .ring_test = &r600_ring_test, |
| 1284 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1285 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1286 | }, |
Alex Deucher | 233d1ad | 2012-12-04 15:25:59 -0500 | [diff] [blame^] | 1287 | [R600_RING_TYPE_DMA_INDEX] = { |
| 1288 | .ib_execute = &evergreen_dma_ring_ib_execute, |
| 1289 | .emit_fence = &evergreen_dma_fence_ring_emit, |
| 1290 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
| 1291 | .cs_parse = NULL, |
| 1292 | .ring_test = &r600_dma_ring_test, |
| 1293 | .ib_test = &r600_dma_ib_test, |
| 1294 | .is_lockup = &r600_dma_is_lockup, |
| 1295 | } |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1296 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1297 | .irq = { |
| 1298 | .set = &evergreen_irq_set, |
| 1299 | .process = &evergreen_irq_process, |
| 1300 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1301 | .display = { |
| 1302 | .bandwidth_update = &evergreen_bandwidth_update, |
| 1303 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1304 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1305 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1306 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1307 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1308 | .copy = { |
| 1309 | .blit = &r600_copy_blit, |
| 1310 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Alex Deucher | 233d1ad | 2012-12-04 15:25:59 -0500 | [diff] [blame^] | 1311 | .dma = &evergreen_copy_dma, |
| 1312 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1313 | .copy = &r600_copy_blit, |
| 1314 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1315 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1316 | .surface = { |
| 1317 | .set_reg = r600_set_surface_reg, |
| 1318 | .clear_reg = r600_clear_surface_reg, |
| 1319 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1320 | .hpd = { |
| 1321 | .init = &evergreen_hpd_init, |
| 1322 | .fini = &evergreen_hpd_fini, |
| 1323 | .sense = &evergreen_hpd_sense, |
| 1324 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1325 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1326 | .pm = { |
| 1327 | .misc = &evergreen_pm_misc, |
| 1328 | .prepare = &evergreen_pm_prepare, |
| 1329 | .finish = &evergreen_pm_finish, |
| 1330 | .init_profile = &sumo_pm_init_profile, |
| 1331 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1332 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1333 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1334 | .get_memory_clock = NULL, |
| 1335 | .set_memory_clock = NULL, |
| 1336 | .get_pcie_lanes = NULL, |
| 1337 | .set_pcie_lanes = NULL, |
| 1338 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1339 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1340 | .pflip = { |
| 1341 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1342 | .page_flip = &evergreen_page_flip, |
| 1343 | .post_page_flip = &evergreen_post_page_flip, |
| 1344 | }, |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1345 | }; |
| 1346 | |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1347 | static struct radeon_asic btc_asic = { |
| 1348 | .init = &evergreen_init, |
| 1349 | .fini = &evergreen_fini, |
| 1350 | .suspend = &evergreen_suspend, |
| 1351 | .resume = &evergreen_resume, |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1352 | .asic_reset = &evergreen_asic_reset, |
| 1353 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1354 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1355 | .gui_idle = &r600_gui_idle, |
| 1356 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1357 | .gart = { |
| 1358 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1359 | .set_page = &rs600_gart_set_page, |
| 1360 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1361 | .ring = { |
| 1362 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1363 | .ib_execute = &evergreen_ring_ib_execute, |
| 1364 | .emit_fence = &r600_fence_ring_emit, |
| 1365 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1366 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1367 | .ring_test = &r600_ring_test, |
| 1368 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1369 | .is_lockup = &evergreen_gpu_is_lockup, |
Alex Deucher | 233d1ad | 2012-12-04 15:25:59 -0500 | [diff] [blame^] | 1370 | }, |
| 1371 | [R600_RING_TYPE_DMA_INDEX] = { |
| 1372 | .ib_execute = &evergreen_dma_ring_ib_execute, |
| 1373 | .emit_fence = &evergreen_dma_fence_ring_emit, |
| 1374 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
| 1375 | .cs_parse = NULL, |
| 1376 | .ring_test = &r600_dma_ring_test, |
| 1377 | .ib_test = &r600_dma_ib_test, |
| 1378 | .is_lockup = &r600_dma_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1379 | } |
| 1380 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1381 | .irq = { |
| 1382 | .set = &evergreen_irq_set, |
| 1383 | .process = &evergreen_irq_process, |
| 1384 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1385 | .display = { |
| 1386 | .bandwidth_update = &evergreen_bandwidth_update, |
| 1387 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1388 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1389 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1390 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1391 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1392 | .copy = { |
| 1393 | .blit = &r600_copy_blit, |
| 1394 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Alex Deucher | 233d1ad | 2012-12-04 15:25:59 -0500 | [diff] [blame^] | 1395 | .dma = &evergreen_copy_dma, |
| 1396 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1397 | .copy = &r600_copy_blit, |
| 1398 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1399 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1400 | .surface = { |
| 1401 | .set_reg = r600_set_surface_reg, |
| 1402 | .clear_reg = r600_clear_surface_reg, |
| 1403 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1404 | .hpd = { |
| 1405 | .init = &evergreen_hpd_init, |
| 1406 | .fini = &evergreen_hpd_fini, |
| 1407 | .sense = &evergreen_hpd_sense, |
| 1408 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1409 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1410 | .pm = { |
| 1411 | .misc = &evergreen_pm_misc, |
| 1412 | .prepare = &evergreen_pm_prepare, |
| 1413 | .finish = &evergreen_pm_finish, |
Alex Deucher | 27810fb | 2012-10-01 19:25:11 -0400 | [diff] [blame] | 1414 | .init_profile = &btc_pm_init_profile, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1415 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1416 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1417 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1418 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1419 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1420 | .get_pcie_lanes = NULL, |
| 1421 | .set_pcie_lanes = NULL, |
| 1422 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1423 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1424 | .pflip = { |
| 1425 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1426 | .page_flip = &evergreen_page_flip, |
| 1427 | .post_page_flip = &evergreen_post_page_flip, |
| 1428 | }, |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1429 | }; |
| 1430 | |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1431 | static struct radeon_asic cayman_asic = { |
| 1432 | .init = &cayman_init, |
| 1433 | .fini = &cayman_fini, |
| 1434 | .suspend = &cayman_suspend, |
| 1435 | .resume = &cayman_resume, |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1436 | .asic_reset = &cayman_asic_reset, |
| 1437 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1438 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1439 | .gui_idle = &r600_gui_idle, |
| 1440 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1441 | .gart = { |
| 1442 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
| 1443 | .set_page = &rs600_gart_set_page, |
| 1444 | }, |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1445 | .vm = { |
| 1446 | .init = &cayman_vm_init, |
| 1447 | .fini = &cayman_vm_fini, |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1448 | .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1449 | .set_page = &cayman_vm_set_page, |
| 1450 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1451 | .ring = { |
| 1452 | [RADEON_RING_TYPE_GFX_INDEX] = { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1453 | .ib_execute = &cayman_ring_ib_execute, |
| 1454 | .ib_parse = &evergreen_ib_parse, |
Alex Deucher | b40e7e1 | 2011-11-17 14:57:50 -0500 | [diff] [blame] | 1455 | .emit_fence = &cayman_fence_ring_emit, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1456 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1457 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1458 | .ring_test = &r600_ring_test, |
| 1459 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1460 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 1461 | .vm_flush = &cayman_vm_flush, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1462 | }, |
| 1463 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1464 | .ib_execute = &cayman_ring_ib_execute, |
| 1465 | .ib_parse = &evergreen_ib_parse, |
Alex Deucher | b40e7e1 | 2011-11-17 14:57:50 -0500 | [diff] [blame] | 1466 | .emit_fence = &cayman_fence_ring_emit, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1467 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1468 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1469 | .ring_test = &r600_ring_test, |
| 1470 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1471 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 1472 | .vm_flush = &cayman_vm_flush, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1473 | }, |
| 1474 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1475 | .ib_execute = &cayman_ring_ib_execute, |
| 1476 | .ib_parse = &evergreen_ib_parse, |
Alex Deucher | b40e7e1 | 2011-11-17 14:57:50 -0500 | [diff] [blame] | 1477 | .emit_fence = &cayman_fence_ring_emit, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1478 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1479 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1480 | .ring_test = &r600_ring_test, |
| 1481 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1482 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 1483 | .vm_flush = &cayman_vm_flush, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1484 | } |
| 1485 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1486 | .irq = { |
| 1487 | .set = &evergreen_irq_set, |
| 1488 | .process = &evergreen_irq_process, |
| 1489 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1490 | .display = { |
| 1491 | .bandwidth_update = &evergreen_bandwidth_update, |
| 1492 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1493 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1494 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1495 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1496 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1497 | .copy = { |
| 1498 | .blit = &r600_copy_blit, |
| 1499 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1500 | .dma = NULL, |
| 1501 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1502 | .copy = &r600_copy_blit, |
| 1503 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1504 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1505 | .surface = { |
| 1506 | .set_reg = r600_set_surface_reg, |
| 1507 | .clear_reg = r600_clear_surface_reg, |
| 1508 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1509 | .hpd = { |
| 1510 | .init = &evergreen_hpd_init, |
| 1511 | .fini = &evergreen_hpd_fini, |
| 1512 | .sense = &evergreen_hpd_sense, |
| 1513 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1514 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1515 | .pm = { |
| 1516 | .misc = &evergreen_pm_misc, |
| 1517 | .prepare = &evergreen_pm_prepare, |
| 1518 | .finish = &evergreen_pm_finish, |
Alex Deucher | 27810fb | 2012-10-01 19:25:11 -0400 | [diff] [blame] | 1519 | .init_profile = &btc_pm_init_profile, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1520 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1521 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1522 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1523 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1524 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1525 | .get_pcie_lanes = NULL, |
| 1526 | .set_pcie_lanes = NULL, |
| 1527 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1528 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1529 | .pflip = { |
| 1530 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1531 | .page_flip = &evergreen_page_flip, |
| 1532 | .post_page_flip = &evergreen_post_page_flip, |
| 1533 | }, |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1534 | }; |
| 1535 | |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1536 | static struct radeon_asic trinity_asic = { |
| 1537 | .init = &cayman_init, |
| 1538 | .fini = &cayman_fini, |
| 1539 | .suspend = &cayman_suspend, |
| 1540 | .resume = &cayman_resume, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1541 | .asic_reset = &cayman_asic_reset, |
| 1542 | .vga_set_state = &r600_vga_set_state, |
| 1543 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1544 | .gui_idle = &r600_gui_idle, |
| 1545 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
| 1546 | .gart = { |
| 1547 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
| 1548 | .set_page = &rs600_gart_set_page, |
| 1549 | }, |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1550 | .vm = { |
| 1551 | .init = &cayman_vm_init, |
| 1552 | .fini = &cayman_vm_fini, |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1553 | .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1554 | .set_page = &cayman_vm_set_page, |
| 1555 | }, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1556 | .ring = { |
| 1557 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1558 | .ib_execute = &cayman_ring_ib_execute, |
| 1559 | .ib_parse = &evergreen_ib_parse, |
| 1560 | .emit_fence = &cayman_fence_ring_emit, |
| 1561 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1562 | .cs_parse = &evergreen_cs_parse, |
| 1563 | .ring_test = &r600_ring_test, |
| 1564 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1565 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 1566 | .vm_flush = &cayman_vm_flush, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1567 | }, |
| 1568 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
| 1569 | .ib_execute = &cayman_ring_ib_execute, |
| 1570 | .ib_parse = &evergreen_ib_parse, |
| 1571 | .emit_fence = &cayman_fence_ring_emit, |
| 1572 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1573 | .cs_parse = &evergreen_cs_parse, |
| 1574 | .ring_test = &r600_ring_test, |
| 1575 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1576 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 1577 | .vm_flush = &cayman_vm_flush, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1578 | }, |
| 1579 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
| 1580 | .ib_execute = &cayman_ring_ib_execute, |
| 1581 | .ib_parse = &evergreen_ib_parse, |
| 1582 | .emit_fence = &cayman_fence_ring_emit, |
| 1583 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1584 | .cs_parse = &evergreen_cs_parse, |
| 1585 | .ring_test = &r600_ring_test, |
| 1586 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1587 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 1588 | .vm_flush = &cayman_vm_flush, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1589 | } |
| 1590 | }, |
| 1591 | .irq = { |
| 1592 | .set = &evergreen_irq_set, |
| 1593 | .process = &evergreen_irq_process, |
| 1594 | }, |
| 1595 | .display = { |
| 1596 | .bandwidth_update = &dce6_bandwidth_update, |
| 1597 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1598 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1599 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1600 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1601 | }, |
| 1602 | .copy = { |
| 1603 | .blit = &r600_copy_blit, |
| 1604 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1605 | .dma = NULL, |
| 1606 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1607 | .copy = &r600_copy_blit, |
| 1608 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1609 | }, |
| 1610 | .surface = { |
| 1611 | .set_reg = r600_set_surface_reg, |
| 1612 | .clear_reg = r600_clear_surface_reg, |
| 1613 | }, |
| 1614 | .hpd = { |
| 1615 | .init = &evergreen_hpd_init, |
| 1616 | .fini = &evergreen_hpd_fini, |
| 1617 | .sense = &evergreen_hpd_sense, |
| 1618 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1619 | }, |
| 1620 | .pm = { |
| 1621 | .misc = &evergreen_pm_misc, |
| 1622 | .prepare = &evergreen_pm_prepare, |
| 1623 | .finish = &evergreen_pm_finish, |
| 1624 | .init_profile = &sumo_pm_init_profile, |
| 1625 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1626 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1627 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1628 | .get_memory_clock = NULL, |
| 1629 | .set_memory_clock = NULL, |
| 1630 | .get_pcie_lanes = NULL, |
| 1631 | .set_pcie_lanes = NULL, |
| 1632 | .set_clock_gating = NULL, |
| 1633 | }, |
| 1634 | .pflip = { |
| 1635 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1636 | .page_flip = &evergreen_page_flip, |
| 1637 | .post_page_flip = &evergreen_post_page_flip, |
| 1638 | }, |
| 1639 | }; |
| 1640 | |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1641 | static struct radeon_asic si_asic = { |
| 1642 | .init = &si_init, |
| 1643 | .fini = &si_fini, |
| 1644 | .suspend = &si_suspend, |
| 1645 | .resume = &si_resume, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1646 | .asic_reset = &si_asic_reset, |
| 1647 | .vga_set_state = &r600_vga_set_state, |
| 1648 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1649 | .gui_idle = &r600_gui_idle, |
| 1650 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
| 1651 | .gart = { |
| 1652 | .tlb_flush = &si_pcie_gart_tlb_flush, |
| 1653 | .set_page = &rs600_gart_set_page, |
| 1654 | }, |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1655 | .vm = { |
| 1656 | .init = &si_vm_init, |
| 1657 | .fini = &si_vm_fini, |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1658 | .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Alex Deucher | 82ffd92 | 2012-10-02 14:47:46 -0400 | [diff] [blame] | 1659 | .set_page = &si_vm_set_page, |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1660 | }, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1661 | .ring = { |
| 1662 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1663 | .ib_execute = &si_ring_ib_execute, |
| 1664 | .ib_parse = &si_ib_parse, |
| 1665 | .emit_fence = &si_fence_ring_emit, |
| 1666 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1667 | .cs_parse = NULL, |
| 1668 | .ring_test = &r600_ring_test, |
| 1669 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1670 | .is_lockup = &si_gpu_is_lockup, |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 1671 | .vm_flush = &si_vm_flush, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1672 | }, |
| 1673 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
| 1674 | .ib_execute = &si_ring_ib_execute, |
| 1675 | .ib_parse = &si_ib_parse, |
| 1676 | .emit_fence = &si_fence_ring_emit, |
| 1677 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1678 | .cs_parse = NULL, |
| 1679 | .ring_test = &r600_ring_test, |
| 1680 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1681 | .is_lockup = &si_gpu_is_lockup, |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 1682 | .vm_flush = &si_vm_flush, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1683 | }, |
| 1684 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
| 1685 | .ib_execute = &si_ring_ib_execute, |
| 1686 | .ib_parse = &si_ib_parse, |
| 1687 | .emit_fence = &si_fence_ring_emit, |
| 1688 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1689 | .cs_parse = NULL, |
| 1690 | .ring_test = &r600_ring_test, |
| 1691 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1692 | .is_lockup = &si_gpu_is_lockup, |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 1693 | .vm_flush = &si_vm_flush, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1694 | } |
| 1695 | }, |
| 1696 | .irq = { |
| 1697 | .set = &si_irq_set, |
| 1698 | .process = &si_irq_process, |
| 1699 | }, |
| 1700 | .display = { |
| 1701 | .bandwidth_update = &dce6_bandwidth_update, |
| 1702 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1703 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1704 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1705 | .get_backlight_level = &atombios_get_backlight_level, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1706 | }, |
| 1707 | .copy = { |
| 1708 | .blit = NULL, |
| 1709 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1710 | .dma = NULL, |
| 1711 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1712 | .copy = NULL, |
| 1713 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1714 | }, |
| 1715 | .surface = { |
| 1716 | .set_reg = r600_set_surface_reg, |
| 1717 | .clear_reg = r600_clear_surface_reg, |
| 1718 | }, |
| 1719 | .hpd = { |
| 1720 | .init = &evergreen_hpd_init, |
| 1721 | .fini = &evergreen_hpd_fini, |
| 1722 | .sense = &evergreen_hpd_sense, |
| 1723 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1724 | }, |
| 1725 | .pm = { |
| 1726 | .misc = &evergreen_pm_misc, |
| 1727 | .prepare = &evergreen_pm_prepare, |
| 1728 | .finish = &evergreen_pm_finish, |
| 1729 | .init_profile = &sumo_pm_init_profile, |
| 1730 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1731 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1732 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1733 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1734 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1735 | .get_pcie_lanes = NULL, |
| 1736 | .set_pcie_lanes = NULL, |
| 1737 | .set_clock_gating = NULL, |
| 1738 | }, |
| 1739 | .pflip = { |
| 1740 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1741 | .page_flip = &evergreen_page_flip, |
| 1742 | .post_page_flip = &evergreen_post_page_flip, |
| 1743 | }, |
| 1744 | }; |
| 1745 | |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 1746 | /** |
| 1747 | * radeon_asic_init - register asic specific callbacks |
| 1748 | * |
| 1749 | * @rdev: radeon device pointer |
| 1750 | * |
| 1751 | * Registers the appropriate asic specific callbacks for each |
| 1752 | * chip family. Also sets other asics specific info like the number |
| 1753 | * of crtcs and the register aperture accessors (all asics). |
| 1754 | * Returns 0 for success. |
| 1755 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1756 | int radeon_asic_init(struct radeon_device *rdev) |
| 1757 | { |
| 1758 | radeon_register_accessor_init(rdev); |
Alex Deucher | ba7e05e | 2011-06-16 18:14:22 +0000 | [diff] [blame] | 1759 | |
| 1760 | /* set the number of crtcs */ |
| 1761 | if (rdev->flags & RADEON_SINGLE_CRTC) |
| 1762 | rdev->num_crtc = 1; |
| 1763 | else |
| 1764 | rdev->num_crtc = 2; |
| 1765 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1766 | switch (rdev->family) { |
| 1767 | case CHIP_R100: |
| 1768 | case CHIP_RV100: |
| 1769 | case CHIP_RS100: |
| 1770 | case CHIP_RV200: |
| 1771 | case CHIP_RS200: |
| 1772 | rdev->asic = &r100_asic; |
| 1773 | break; |
| 1774 | case CHIP_R200: |
| 1775 | case CHIP_RV250: |
| 1776 | case CHIP_RS300: |
| 1777 | case CHIP_RV280: |
| 1778 | rdev->asic = &r200_asic; |
| 1779 | break; |
| 1780 | case CHIP_R300: |
| 1781 | case CHIP_R350: |
| 1782 | case CHIP_RV350: |
| 1783 | case CHIP_RV380: |
| 1784 | if (rdev->flags & RADEON_IS_PCIE) |
| 1785 | rdev->asic = &r300_asic_pcie; |
| 1786 | else |
| 1787 | rdev->asic = &r300_asic; |
| 1788 | break; |
| 1789 | case CHIP_R420: |
| 1790 | case CHIP_R423: |
| 1791 | case CHIP_RV410: |
| 1792 | rdev->asic = &r420_asic; |
Alex Deucher | 07bb084 | 2010-06-22 21:58:26 -0400 | [diff] [blame] | 1793 | /* handle macs */ |
| 1794 | if (rdev->bios == NULL) { |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1795 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
| 1796 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; |
| 1797 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; |
| 1798 | rdev->asic->pm.set_memory_clock = NULL; |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1799 | rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; |
Alex Deucher | 07bb084 | 2010-06-22 21:58:26 -0400 | [diff] [blame] | 1800 | } |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1801 | break; |
| 1802 | case CHIP_RS400: |
| 1803 | case CHIP_RS480: |
| 1804 | rdev->asic = &rs400_asic; |
| 1805 | break; |
| 1806 | case CHIP_RS600: |
| 1807 | rdev->asic = &rs600_asic; |
| 1808 | break; |
| 1809 | case CHIP_RS690: |
| 1810 | case CHIP_RS740: |
| 1811 | rdev->asic = &rs690_asic; |
| 1812 | break; |
| 1813 | case CHIP_RV515: |
| 1814 | rdev->asic = &rv515_asic; |
| 1815 | break; |
| 1816 | case CHIP_R520: |
| 1817 | case CHIP_RV530: |
| 1818 | case CHIP_RV560: |
| 1819 | case CHIP_RV570: |
| 1820 | case CHIP_R580: |
| 1821 | rdev->asic = &r520_asic; |
| 1822 | break; |
| 1823 | case CHIP_R600: |
| 1824 | case CHIP_RV610: |
| 1825 | case CHIP_RV630: |
| 1826 | case CHIP_RV620: |
| 1827 | case CHIP_RV635: |
| 1828 | case CHIP_RV670: |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1829 | rdev->asic = &r600_asic; |
| 1830 | break; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1831 | case CHIP_RS780: |
| 1832 | case CHIP_RS880: |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1833 | rdev->asic = &rs780_asic; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1834 | break; |
| 1835 | case CHIP_RV770: |
| 1836 | case CHIP_RV730: |
| 1837 | case CHIP_RV710: |
| 1838 | case CHIP_RV740: |
| 1839 | rdev->asic = &rv770_asic; |
| 1840 | break; |
| 1841 | case CHIP_CEDAR: |
| 1842 | case CHIP_REDWOOD: |
| 1843 | case CHIP_JUNIPER: |
| 1844 | case CHIP_CYPRESS: |
| 1845 | case CHIP_HEMLOCK: |
Alex Deucher | ba7e05e | 2011-06-16 18:14:22 +0000 | [diff] [blame] | 1846 | /* set num crtcs */ |
| 1847 | if (rdev->family == CHIP_CEDAR) |
| 1848 | rdev->num_crtc = 4; |
| 1849 | else |
| 1850 | rdev->num_crtc = 6; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1851 | rdev->asic = &evergreen_asic; |
| 1852 | break; |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1853 | case CHIP_PALM: |
Alex Deucher | 89da5a3 | 2011-05-31 15:42:47 -0400 | [diff] [blame] | 1854 | case CHIP_SUMO: |
| 1855 | case CHIP_SUMO2: |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1856 | rdev->asic = &sumo_asic; |
| 1857 | break; |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1858 | case CHIP_BARTS: |
| 1859 | case CHIP_TURKS: |
| 1860 | case CHIP_CAICOS: |
Alex Deucher | ba7e05e | 2011-06-16 18:14:22 +0000 | [diff] [blame] | 1861 | /* set num crtcs */ |
| 1862 | if (rdev->family == CHIP_CAICOS) |
| 1863 | rdev->num_crtc = 4; |
| 1864 | else |
| 1865 | rdev->num_crtc = 6; |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1866 | rdev->asic = &btc_asic; |
| 1867 | break; |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1868 | case CHIP_CAYMAN: |
| 1869 | rdev->asic = &cayman_asic; |
Alex Deucher | ba7e05e | 2011-06-16 18:14:22 +0000 | [diff] [blame] | 1870 | /* set num crtcs */ |
| 1871 | rdev->num_crtc = 6; |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1872 | break; |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1873 | case CHIP_ARUBA: |
| 1874 | rdev->asic = &trinity_asic; |
| 1875 | /* set num crtcs */ |
| 1876 | rdev->num_crtc = 4; |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1877 | break; |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1878 | case CHIP_TAHITI: |
| 1879 | case CHIP_PITCAIRN: |
| 1880 | case CHIP_VERDE: |
| 1881 | rdev->asic = &si_asic; |
| 1882 | /* set num crtcs */ |
| 1883 | rdev->num_crtc = 6; |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1884 | break; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1885 | default: |
| 1886 | /* FIXME: not supported yet */ |
| 1887 | return -EINVAL; |
| 1888 | } |
| 1889 | |
| 1890 | if (rdev->flags & RADEON_IS_IGP) { |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1891 | rdev->asic->pm.get_memory_clock = NULL; |
| 1892 | rdev->asic->pm.set_memory_clock = NULL; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1893 | } |
| 1894 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1895 | return 0; |
| 1896 | } |
| 1897 | |