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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
Thiemo Seufere30ec452008-01-28 20:05:38 +00008 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
Maciej W. Rozycki619b6e12007-10-23 12:43:25 +01009 * Copyright (C) 2005, 2007 Maciej W. Rozycki
Ralf Baechle41c594a2006-04-05 09:45:45 +010010 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 *
12 * ... and the days got worse and worse and now you see
13 * I've gone completly out of my mind.
14 *
15 * They're coming to take me a away haha
16 * they're coming to take me a away hoho hihi haha
17 * to the funny farm where code is beautiful all the time ...
18 *
19 * (Condolences to Napoleon XIV)
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 */
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/string.h>
25#include <linux/init.h>
26
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <asm/mmu_context.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <asm/war.h>
29
Thiemo Seufere30ec452008-01-28 20:05:38 +000030#include "uasm.h"
31
Ralf Baechleaeffdbb2007-10-11 23:46:14 +010032static inline int r45k_bvahwbug(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070033{
34 /* XXX: We should probe for the presence of this bug, but we don't. */
35 return 0;
36}
37
Ralf Baechleaeffdbb2007-10-11 23:46:14 +010038static inline int r4k_250MHZhwbug(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039{
40 /* XXX: We should probe for the presence of this bug, but we don't. */
41 return 0;
42}
43
Ralf Baechleaeffdbb2007-10-11 23:46:14 +010044static inline int __maybe_unused bcm1250_m3_war(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070045{
46 return BCM1250_M3_WAR;
47}
48
Ralf Baechleaeffdbb2007-10-11 23:46:14 +010049static inline int __maybe_unused r10000_llsc_war(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070050{
51 return R10000_LLSC_WAR;
52}
53
54/*
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +010055 * Found by experiment: At least some revisions of the 4kc throw under
56 * some circumstances a machine check exception, triggered by invalid
57 * values in the index register. Delaying the tlbp instruction until
58 * after the next branch, plus adding an additional nop in front of
59 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
60 * why; it's not an issue caused by the core RTL.
61 *
62 */
Ralf Baechle234fcd12008-03-08 09:56:28 +000063static int __cpuinit m4kc_tlbp_war(void)
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +010064{
65 return (current_cpu_data.processor_id & 0xffff00) ==
66 (PRID_COMP_MIPS | PRID_IMP_4KC);
67}
68
Thiemo Seufere30ec452008-01-28 20:05:38 +000069/* Handle labels (which must be positive integers). */
Linus Torvalds1da177e2005-04-16 15:20:36 -070070enum label_id {
Thiemo Seufere30ec452008-01-28 20:05:38 +000071 label_second_part = 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 label_leave,
Atsushi Nemoto656be922006-10-26 00:08:31 +090073#ifdef MODULE_START
74 label_module_alloc,
75#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 label_vmalloc,
77 label_vmalloc_done,
78 label_tlbw_hazard,
79 label_split,
80 label_nopage_tlbl,
81 label_nopage_tlbs,
82 label_nopage_tlbm,
83 label_smp_pgtable_change,
84 label_r3000_write_probe_fail,
Linus Torvalds1da177e2005-04-16 15:20:36 -070085};
86
Thiemo Seufere30ec452008-01-28 20:05:38 +000087UASM_L_LA(_second_part)
88UASM_L_LA(_leave)
Atsushi Nemoto656be922006-10-26 00:08:31 +090089#ifdef MODULE_START
Thiemo Seufere30ec452008-01-28 20:05:38 +000090UASM_L_LA(_module_alloc)
Atsushi Nemoto656be922006-10-26 00:08:31 +090091#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +000092UASM_L_LA(_vmalloc)
93UASM_L_LA(_vmalloc_done)
94UASM_L_LA(_tlbw_hazard)
95UASM_L_LA(_split)
96UASM_L_LA(_nopage_tlbl)
97UASM_L_LA(_nopage_tlbs)
98UASM_L_LA(_nopage_tlbm)
99UASM_L_LA(_smp_pgtable_change)
100UASM_L_LA(_r3000_write_probe_fail)
Atsushi Nemoto656be922006-10-26 00:08:31 +0900101
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +0200102/*
103 * For debug purposes.
104 */
105static inline void dump_handler(const u32 *handler, int count)
106{
107 int i;
108
109 pr_debug("\t.set push\n");
110 pr_debug("\t.set noreorder\n");
111
112 for (i = 0; i < count; i++)
113 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
114
115 pr_debug("\t.set pop\n");
116}
117
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118/* The only general purpose registers allowed in TLB handlers. */
119#define K0 26
120#define K1 27
121
122/* Some CP0 registers */
Ralf Baechle41c594a2006-04-05 09:45:45 +0100123#define C0_INDEX 0, 0
124#define C0_ENTRYLO0 2, 0
125#define C0_TCBIND 2, 2
126#define C0_ENTRYLO1 3, 0
127#define C0_CONTEXT 4, 0
128#define C0_BADVADDR 8, 0
129#define C0_ENTRYHI 10, 0
130#define C0_EPC 14, 0
131#define C0_XCONTEXT 20, 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
Ralf Baechle875d43e2005-09-03 15:56:16 -0700133#ifdef CONFIG_64BIT
Thiemo Seufere30ec452008-01-28 20:05:38 +0000134# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000136# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137#endif
138
139/* The worst case length of the handler is around 18 instructions for
140 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
141 * Maximum space available is 32 instructions for R3000 and 64
142 * instructions for R4000.
143 *
144 * We deliberately chose a buffer size of 128, so we won't scribble
145 * over anything important on overflow before we panic.
146 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000147static u32 tlb_handler[128] __cpuinitdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148
149/* simply assume worst case size for labels and relocs */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000150static struct uasm_label labels[128] __cpuinitdata;
151static struct uasm_reloc relocs[128] __cpuinitdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152
153/*
154 * The R3000 TLB handler is simple.
155 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000156static void __cpuinit build_r3000_tlb_refill_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157{
158 long pgdc = (long)pgd_current;
159 u32 *p;
160
161 memset(tlb_handler, 0, sizeof(tlb_handler));
162 p = tlb_handler;
163
Thiemo Seufere30ec452008-01-28 20:05:38 +0000164 uasm_i_mfc0(&p, K0, C0_BADVADDR);
165 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
166 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
167 uasm_i_srl(&p, K0, K0, 22); /* load delay */
168 uasm_i_sll(&p, K0, K0, 2);
169 uasm_i_addu(&p, K1, K1, K0);
170 uasm_i_mfc0(&p, K0, C0_CONTEXT);
171 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
172 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
173 uasm_i_addu(&p, K1, K1, K0);
174 uasm_i_lw(&p, K0, 0, K1);
175 uasm_i_nop(&p); /* load delay */
176 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
177 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
178 uasm_i_tlbwr(&p); /* cp0 delay */
179 uasm_i_jr(&p, K1);
180 uasm_i_rfe(&p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181
182 if (p > tlb_handler + 32)
183 panic("TLB refill handler space exceeded");
184
Thiemo Seufere30ec452008-01-28 20:05:38 +0000185 pr_debug("Wrote TLB refill handler (%u instructions).\n",
186 (unsigned int)(p - tlb_handler));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187
Ralf Baechle91b05e62006-03-29 18:53:00 +0100188 memcpy((void *)ebase, tlb_handler, 0x80);
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +0200189
190 dump_handler((u32 *)ebase, 32);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191}
192
193/*
194 * The R4000 TLB handler is much more complicated. We have two
195 * consecutive handler areas with 32 instructions space each.
196 * Since they aren't used at the same time, we can overflow in the
197 * other one.To keep things simple, we first assume linear space,
198 * then we relocate it to the final handler layout as needed.
199 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000200static u32 final_handler[64] __cpuinitdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201
202/*
203 * Hazards
204 *
205 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
206 * 2. A timing hazard exists for the TLBP instruction.
207 *
208 * stalling_instruction
209 * TLBP
210 *
211 * The JTLB is being read for the TLBP throughout the stall generated by the
212 * previous instruction. This is not really correct as the stalling instruction
213 * can modify the address used to access the JTLB. The failure symptom is that
214 * the TLBP instruction will use an address created for the stalling instruction
215 * and not the address held in C0_ENHI and thus report the wrong results.
216 *
217 * The software work-around is to not allow the instruction preceding the TLBP
218 * to stall - make it an NOP or some other instruction guaranteed not to stall.
219 *
220 * Errata 2 will not be fixed. This errata is also on the R5000.
221 *
222 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
223 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000224static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225{
Ralf Baechle10cc3522007-10-11 23:46:15 +0100226 switch (current_cpu_type()) {
Thiemo Seuferf5b4d952005-09-09 17:11:50 +0000227 /* Found by experiment: R4600 v2.0 needs this, too. */
228 case CPU_R4600:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 case CPU_R5000:
230 case CPU_R5000A:
231 case CPU_NEVADA:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000232 uasm_i_nop(p);
233 uasm_i_tlbp(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 break;
235
236 default:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000237 uasm_i_tlbp(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 break;
239 }
240}
241
242/*
243 * Write random or indexed TLB entry, and care about the hazards from
244 * the preceeding mtc0 and for the following eret.
245 */
246enum tlb_write_entry { tlb_random, tlb_indexed };
247
Ralf Baechle234fcd12008-03-08 09:56:28 +0000248static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
Thiemo Seufere30ec452008-01-28 20:05:38 +0000249 struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250 enum tlb_write_entry wmode)
251{
252 void(*tlbw)(u32 **) = NULL;
253
254 switch (wmode) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000255 case tlb_random: tlbw = uasm_i_tlbwr; break;
256 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 }
258
Ralf Baechle161548b2008-01-29 10:14:54 +0000259 if (cpu_has_mips_r2) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000260 uasm_i_ehb(p);
Ralf Baechle161548b2008-01-29 10:14:54 +0000261 tlbw(p);
262 return;
263 }
264
Ralf Baechle10cc3522007-10-11 23:46:15 +0100265 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266 case CPU_R4000PC:
267 case CPU_R4000SC:
268 case CPU_R4000MC:
269 case CPU_R4400PC:
270 case CPU_R4400SC:
271 case CPU_R4400MC:
272 /*
273 * This branch uses up a mtc0 hazard nop slot and saves
274 * two nops after the tlbw instruction.
275 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000276 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000278 uasm_l_tlbw_hazard(l, *p);
279 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 break;
281
282 case CPU_R4600:
283 case CPU_R4700:
284 case CPU_R5000:
285 case CPU_R5000A:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000286 uasm_i_nop(p);
Maciej W. Rozycki2c93e122005-06-30 10:51:01 +0000287 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000288 uasm_i_nop(p);
Maciej W. Rozycki2c93e122005-06-30 10:51:01 +0000289 break;
290
291 case CPU_R4300:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 case CPU_5KC:
293 case CPU_TX49XX:
294 case CPU_AU1000:
295 case CPU_AU1100:
296 case CPU_AU1500:
297 case CPU_AU1550:
Pete Popove3ad1c22005-03-01 06:33:16 +0000298 case CPU_AU1200:
Manuel Lauss237cfee2007-12-06 09:07:55 +0100299 case CPU_AU1210:
300 case CPU_AU1250:
Pete Popovbdf21b12005-07-14 17:47:57 +0000301 case CPU_PR4450:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000302 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 tlbw(p);
304 break;
305
306 case CPU_R10000:
307 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -0400308 case CPU_R14000:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309 case CPU_4KC:
310 case CPU_SB1:
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700311 case CPU_SB1A:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 case CPU_4KSC:
313 case CPU_20KC:
314 case CPU_25KF:
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200315 case CPU_BCM3302:
316 case CPU_BCM4710:
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800317 case CPU_LOONGSON2:
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +0100318 if (m4kc_tlbp_war())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000319 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 tlbw(p);
321 break;
322
323 case CPU_NEVADA:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000324 uasm_i_nop(p); /* QED specifies 2 nops hazard */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 /*
326 * This branch uses up a mtc0 hazard nop slot and saves
327 * a nop after the tlbw instruction.
328 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000329 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000331 uasm_l_tlbw_hazard(l, *p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 break;
333
334 case CPU_RM7000:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000335 uasm_i_nop(p);
336 uasm_i_nop(p);
337 uasm_i_nop(p);
338 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339 tlbw(p);
340 break;
341
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342 case CPU_RM9000:
343 /*
344 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
345 * use of the JTLB for instructions should not occur for 4
346 * cpu cycles and use for data translations should not occur
347 * for 3 cpu cycles.
348 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000349 uasm_i_ssnop(p);
350 uasm_i_ssnop(p);
351 uasm_i_ssnop(p);
352 uasm_i_ssnop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000354 uasm_i_ssnop(p);
355 uasm_i_ssnop(p);
356 uasm_i_ssnop(p);
357 uasm_i_ssnop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 break;
359
360 case CPU_VR4111:
361 case CPU_VR4121:
362 case CPU_VR4122:
363 case CPU_VR4181:
364 case CPU_VR4181A:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000365 uasm_i_nop(p);
366 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000368 uasm_i_nop(p);
369 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 break;
371
372 case CPU_VR4131:
373 case CPU_VR4133:
Ralf Baechle7623deb2005-08-29 16:49:55 +0000374 case CPU_R5432:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000375 uasm_i_nop(p);
376 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 tlbw(p);
378 break;
379
380 default:
381 panic("No TLB refill handler yet (CPU type: %d)",
382 current_cpu_data.cputype);
383 break;
384 }
385}
386
Ralf Baechle875d43e2005-09-03 15:56:16 -0700387#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388/*
389 * TMP and PTR are scratch.
390 * TMP will be clobbered, PTR will hold the pmd entry.
391 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000392static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000393build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 unsigned int tmp, unsigned int ptr)
395{
396 long pgdc = (long)pgd_current;
397
398 /*
399 * The vmalloc handling is not in the hotpath.
400 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000401 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900402#ifdef MODULE_START
Thiemo Seufere30ec452008-01-28 20:05:38 +0000403 uasm_il_bltz(p, r, tmp, label_module_alloc);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900404#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000405 uasm_il_bltz(p, r, tmp, label_vmalloc);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900406#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000407 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408
409#ifdef CONFIG_SMP
Ralf Baechle41c594a2006-04-05 09:45:45 +0100410# ifdef CONFIG_MIPS_MT_SMTC
411 /*
412 * SMTC uses TCBind value as "CPU" index
413 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000414 uasm_i_mfc0(p, ptr, C0_TCBIND);
415 uasm_i_dsrl(p, ptr, ptr, 19);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100416# else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 /*
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +0000418 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419 * stored in CONTEXT.
420 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000421 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
422 uasm_i_dsrl(p, ptr, ptr, 23);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100423#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000424 UASM_i_LA_mostly(p, tmp, pgdc);
425 uasm_i_daddu(p, ptr, ptr, tmp);
426 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
427 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000429 UASM_i_LA_mostly(p, ptr, pgdc);
430 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431#endif
432
Thiemo Seufere30ec452008-01-28 20:05:38 +0000433 uasm_l_vmalloc_done(l, *p);
Ralf Baechle242954b2006-10-24 02:29:01 +0100434
435 if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000436 uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3);
Ralf Baechle242954b2006-10-24 02:29:01 +0100437 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000438 uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32);
Ralf Baechle242954b2006-10-24 02:29:01 +0100439
Thiemo Seufere30ec452008-01-28 20:05:38 +0000440 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
441 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
442 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
443 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
444 uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
445 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
446 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447}
448
449/*
450 * BVADDR is the faulting address, PTR is scratch.
451 * PTR will hold the pgd for vmalloc.
452 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000453static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000454build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 unsigned int bvaddr, unsigned int ptr)
456{
457 long swpd = (long)swapper_pg_dir;
458
Atsushi Nemoto656be922006-10-26 00:08:31 +0900459#ifdef MODULE_START
460 long modd = (long)module_pg_dir;
461
Thiemo Seufere30ec452008-01-28 20:05:38 +0000462 uasm_l_module_alloc(l, *p);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900463 /*
464 * Assumption:
465 * VMALLOC_START >= 0xc000000000000000UL
466 * MODULE_START >= 0xe000000000000000UL
467 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000468 UASM_i_SLL(p, ptr, bvaddr, 2);
469 uasm_il_bgez(p, r, ptr, label_vmalloc);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900470
Thiemo Seufere30ec452008-01-28 20:05:38 +0000471 if (uasm_in_compat_space_p(MODULE_START) &&
472 !uasm_rel_lo(MODULE_START)) {
473 uasm_i_lui(p, ptr, uasm_rel_hi(MODULE_START)); /* delay slot */
Atsushi Nemoto656be922006-10-26 00:08:31 +0900474 } else {
475 /* unlikely configuration */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000476 uasm_i_nop(p); /* delay slot */
477 UASM_i_LA(p, ptr, MODULE_START);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900478 }
Thiemo Seufere30ec452008-01-28 20:05:38 +0000479 uasm_i_dsubu(p, bvaddr, bvaddr, ptr);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900480
Thiemo Seufere30ec452008-01-28 20:05:38 +0000481 if (uasm_in_compat_space_p(modd) && !uasm_rel_lo(modd)) {
482 uasm_il_b(p, r, label_vmalloc_done);
483 uasm_i_lui(p, ptr, uasm_rel_hi(modd));
Atsushi Nemoto656be922006-10-26 00:08:31 +0900484 } else {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000485 UASM_i_LA_mostly(p, ptr, modd);
486 uasm_il_b(p, r, label_vmalloc_done);
487 if (uasm_in_compat_space_p(modd))
488 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(modd));
Maciej W. Rozycki619b6e12007-10-23 12:43:25 +0100489 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000490 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(modd));
Atsushi Nemoto656be922006-10-26 00:08:31 +0900491 }
492
Thiemo Seufere30ec452008-01-28 20:05:38 +0000493 uasm_l_vmalloc(l, *p);
494 if (uasm_in_compat_space_p(MODULE_START) &&
495 !uasm_rel_lo(MODULE_START) &&
Atsushi Nemoto656be922006-10-26 00:08:31 +0900496 MODULE_START << 32 == VMALLOC_START)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000497 uasm_i_dsll32(p, ptr, ptr, 0); /* typical case */
Atsushi Nemoto656be922006-10-26 00:08:31 +0900498 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000499 UASM_i_LA(p, ptr, VMALLOC_START);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900500#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000501 uasm_l_vmalloc(l, *p);
502 UASM_i_LA(p, ptr, VMALLOC_START);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900503#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000504 uasm_i_dsubu(p, bvaddr, bvaddr, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505
Thiemo Seufere30ec452008-01-28 20:05:38 +0000506 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
507 uasm_il_b(p, r, label_vmalloc_done);
508 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 } else {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000510 UASM_i_LA_mostly(p, ptr, swpd);
511 uasm_il_b(p, r, label_vmalloc_done);
512 if (uasm_in_compat_space_p(swpd))
513 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
Maciej W. Rozycki619b6e12007-10-23 12:43:25 +0100514 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000515 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516 }
517}
518
Ralf Baechle875d43e2005-09-03 15:56:16 -0700519#else /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520
521/*
522 * TMP and PTR are scratch.
523 * TMP will be clobbered, PTR will hold the pgd entry.
524 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000525static void __cpuinit __maybe_unused
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
527{
528 long pgdc = (long)pgd_current;
529
530 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
531#ifdef CONFIG_SMP
Ralf Baechle41c594a2006-04-05 09:45:45 +0100532#ifdef CONFIG_MIPS_MT_SMTC
533 /*
534 * SMTC uses TCBind value as "CPU" index
535 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000536 uasm_i_mfc0(p, ptr, C0_TCBIND);
537 UASM_i_LA_mostly(p, tmp, pgdc);
538 uasm_i_srl(p, ptr, ptr, 19);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100539#else
540 /*
541 * smp_processor_id() << 3 is stored in CONTEXT.
542 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000543 uasm_i_mfc0(p, ptr, C0_CONTEXT);
544 UASM_i_LA_mostly(p, tmp, pgdc);
545 uasm_i_srl(p, ptr, ptr, 23);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100546#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000547 uasm_i_addu(p, ptr, tmp, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000549 UASM_i_LA_mostly(p, ptr, pgdc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000551 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
552 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
553 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
554 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
555 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556}
557
Ralf Baechle875d43e2005-09-03 15:56:16 -0700558#endif /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559
Ralf Baechle234fcd12008-03-08 09:56:28 +0000560static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561{
Ralf Baechle242954b2006-10-24 02:29:01 +0100562 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
564
Ralf Baechle10cc3522007-10-11 23:46:15 +0100565 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566 case CPU_VR41XX:
567 case CPU_VR4111:
568 case CPU_VR4121:
569 case CPU_VR4122:
570 case CPU_VR4131:
571 case CPU_VR4181:
572 case CPU_VR4181A:
573 case CPU_VR4133:
574 shift += 2;
575 break;
576
577 default:
578 break;
579 }
580
581 if (shift)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000582 UASM_i_SRL(p, ctx, ctx, shift);
583 uasm_i_andi(p, ctx, ctx, mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584}
585
Ralf Baechle234fcd12008-03-08 09:56:28 +0000586static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587{
588 /*
589 * Bug workaround for the Nevada. It seems as if under certain
590 * circumstances the move from cp0_context might produce a
591 * bogus result when the mfc0 instruction and its consumer are
592 * in a different cacheline or a load instruction, probably any
593 * memory reference, is between them.
594 */
Ralf Baechle10cc3522007-10-11 23:46:15 +0100595 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596 case CPU_NEVADA:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000597 UASM_i_LW(p, ptr, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598 GET_CONTEXT(p, tmp); /* get context reg */
599 break;
600
601 default:
602 GET_CONTEXT(p, tmp); /* get context reg */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000603 UASM_i_LW(p, ptr, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 break;
605 }
606
607 build_adjust_context(p, tmp);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000608 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609}
610
Ralf Baechle234fcd12008-03-08 09:56:28 +0000611static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612 unsigned int ptep)
613{
614 /*
615 * 64bit address support (36bit on a 32bit CPU) in a 32bit
616 * Kernel is a special case. Only a few CPUs use it.
617 */
618#ifdef CONFIG_64BIT_PHYS_ADDR
619 if (cpu_has_64bits) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000620 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
621 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
622 uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
623 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
624 uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
625 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626 } else {
627 int pte_off_even = sizeof(pte_t) / 2;
628 int pte_off_odd = pte_off_even + sizeof(pte_t);
629
630 /* The pte entries are pre-shifted */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000631 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
632 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
633 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
634 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635 }
636#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000637 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
638 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 if (r45k_bvahwbug())
640 build_tlb_probe_entry(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000641 UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642 if (r4k_250MHZhwbug())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000643 uasm_i_mtc0(p, 0, C0_ENTRYLO0);
644 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
645 UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 if (r45k_bvahwbug())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000647 uasm_i_mfc0(p, tmp, C0_INDEX);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 if (r4k_250MHZhwbug())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000649 uasm_i_mtc0(p, 0, C0_ENTRYLO1);
650 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651#endif
652}
653
Ralf Baechle234fcd12008-03-08 09:56:28 +0000654static void __cpuinit build_r4000_tlb_refill_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655{
656 u32 *p = tlb_handler;
Thiemo Seufere30ec452008-01-28 20:05:38 +0000657 struct uasm_label *l = labels;
658 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 u32 *f;
660 unsigned int final_len;
661
662 memset(tlb_handler, 0, sizeof(tlb_handler));
663 memset(labels, 0, sizeof(labels));
664 memset(relocs, 0, sizeof(relocs));
665 memset(final_handler, 0, sizeof(final_handler));
666
667 /*
668 * create the plain linear handler
669 */
670 if (bcm1250_m3_war()) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000671 UASM_i_MFC0(&p, K0, C0_BADVADDR);
672 UASM_i_MFC0(&p, K1, C0_ENTRYHI);
673 uasm_i_xor(&p, K0, K0, K1);
674 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
675 uasm_il_bnez(&p, &r, K0, label_leave);
676 /* No need for uasm_i_nop */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677 }
678
Ralf Baechle875d43e2005-09-03 15:56:16 -0700679#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
681#else
682 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
683#endif
684
685 build_get_ptep(&p, K0, K1);
686 build_update_entries(&p, K0, K1);
687 build_tlb_write_entry(&p, &l, &r, tlb_random);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000688 uasm_l_leave(&l, p);
689 uasm_i_eret(&p); /* return from trap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690
Ralf Baechle875d43e2005-09-03 15:56:16 -0700691#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
693#endif
694
695 /*
696 * Overflow check: For the 64bit handler, we need at least one
697 * free instruction slot for the wrap-around branch. In worst
698 * case, if the intended insertion point is a delay slot, we
Matt LaPlante4b3f6862006-10-03 22:21:02 +0200699 * need three, with the second nop'ed and the third being
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700 * unused.
701 */
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800702 /* Loongson2 ebase is different than r4k, we have more space */
703#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704 if ((p - tlb_handler) > 64)
705 panic("TLB refill handler space exceeded");
706#else
707 if (((p - tlb_handler) > 63)
708 || (((p - tlb_handler) > 61)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000709 && uasm_insn_has_bdelay(relocs, tlb_handler + 29)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710 panic("TLB refill handler space exceeded");
711#endif
712
713 /*
714 * Now fold the handler in the TLB refill handler space.
715 */
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800716#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 f = final_handler;
718 /* Simplest case, just copy the handler. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000719 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 final_len = p - tlb_handler;
Ralf Baechle875d43e2005-09-03 15:56:16 -0700721#else /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722 f = final_handler + 32;
723 if ((p - tlb_handler) <= 32) {
724 /* Just copy the handler. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000725 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726 final_len = p - tlb_handler;
727 } else {
728 u32 *split = tlb_handler + 30;
729
730 /*
731 * Find the split point.
732 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000733 if (uasm_insn_has_bdelay(relocs, split - 1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734 split--;
735
736 /* Copy first part of the handler. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000737 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738 f += split - tlb_handler;
739
740 /* Insert branch. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000741 uasm_l_split(&l, final_handler);
742 uasm_il_b(&f, &r, label_split);
743 if (uasm_insn_has_bdelay(relocs, split))
744 uasm_i_nop(&f);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 else {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000746 uasm_copy_handler(relocs, labels, split, split + 1, f);
747 uasm_move_labels(labels, f, f + 1, -1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748 f++;
749 split++;
750 }
751
752 /* Copy the rest of the handler. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000753 uasm_copy_handler(relocs, labels, split, p, final_handler);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754 final_len = (f - (final_handler + 32)) + (p - split);
755 }
Ralf Baechle875d43e2005-09-03 15:56:16 -0700756#endif /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757
Thiemo Seufere30ec452008-01-28 20:05:38 +0000758 uasm_resolve_relocs(relocs, labels);
759 pr_debug("Wrote TLB refill handler (%u instructions).\n",
760 final_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761
Ralf Baechle91b05e62006-03-29 18:53:00 +0100762 memcpy((void *)ebase, final_handler, 0x100);
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +0200763
764 dump_handler((u32 *)ebase, 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765}
766
767/*
768 * TLB load/store/modify handlers.
769 *
770 * Only the fastpath gets synthesized at runtime, the slowpath for
771 * do_page_fault remains normal asm.
772 */
773extern void tlb_do_page_fault_0(void);
774extern void tlb_do_page_fault_1(void);
775
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776/*
777 * 128 instructions for the fastpath handler is generous and should
778 * never be exceeded.
779 */
780#define FASTPATH_SIZE 128
781
Franck Bui-Huucbdbe072007-10-18 09:11:16 +0200782u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
783u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
784u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785
Ralf Baechle234fcd12008-03-08 09:56:28 +0000786static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000787iPTE_LW(u32 **p, struct uasm_label **l, unsigned int pte, unsigned int ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788{
789#ifdef CONFIG_SMP
790# ifdef CONFIG_64BIT_PHYS_ADDR
791 if (cpu_has_64bits)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000792 uasm_i_lld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 else
794# endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000795 UASM_i_LL(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796#else
797# ifdef CONFIG_64BIT_PHYS_ADDR
798 if (cpu_has_64bits)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000799 uasm_i_ld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800 else
801# endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000802 UASM_i_LW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803#endif
804}
805
Ralf Baechle234fcd12008-03-08 09:56:28 +0000806static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000807iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000808 unsigned int mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000810#ifdef CONFIG_64BIT_PHYS_ADDR
811 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
812#endif
813
Thiemo Seufere30ec452008-01-28 20:05:38 +0000814 uasm_i_ori(p, pte, pte, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815#ifdef CONFIG_SMP
816# ifdef CONFIG_64BIT_PHYS_ADDR
817 if (cpu_has_64bits)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000818 uasm_i_scd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819 else
820# endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000821 UASM_i_SC(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822
823 if (r10000_llsc_war())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000824 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000826 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827
828# ifdef CONFIG_64BIT_PHYS_ADDR
829 if (!cpu_has_64bits) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000830 /* no uasm_i_nop needed */
831 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
832 uasm_i_ori(p, pte, pte, hwmode);
833 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
834 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
835 /* no uasm_i_nop needed */
836 uasm_i_lw(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 } else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000838 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839# else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000840 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841# endif
842#else
843# ifdef CONFIG_64BIT_PHYS_ADDR
844 if (cpu_has_64bits)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000845 uasm_i_sd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846 else
847# endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000848 UASM_i_SW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849
850# ifdef CONFIG_64BIT_PHYS_ADDR
851 if (!cpu_has_64bits) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000852 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
853 uasm_i_ori(p, pte, pte, hwmode);
854 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
855 uasm_i_lw(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 }
857# endif
858#endif
859}
860
861/*
862 * Check if PTE is present, if not then jump to LABEL. PTR points to
863 * the page table where this PTE is located, PTE will be re-loaded
864 * with it's original value.
865 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000866static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000867build_pte_present(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700868 unsigned int pte, unsigned int ptr, enum label_id lid)
869{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000870 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
871 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
872 uasm_il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000873 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874}
875
876/* Make PTE valid, store result in PTR. */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000877static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000878build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879 unsigned int ptr)
880{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000881 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
882
883 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884}
885
886/*
887 * Check if PTE can be written to, if not branch to LABEL. Regardless
888 * restore PTE with value from PTR when done.
889 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000890static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000891build_pte_writable(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892 unsigned int pte, unsigned int ptr, enum label_id lid)
893{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000894 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
895 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
896 uasm_il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000897 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898}
899
900/* Make PTE writable, update software status bits as well, then store
901 * at PTR.
902 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000903static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000904build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905 unsigned int ptr)
906{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000907 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
908 | _PAGE_DIRTY);
909
910 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911}
912
913/*
914 * Check if PTE can be modified, if not branch to LABEL. Regardless
915 * restore PTE with value from PTR when done.
916 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000917static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000918build_pte_modifiable(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919 unsigned int pte, unsigned int ptr, enum label_id lid)
920{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000921 uasm_i_andi(p, pte, pte, _PAGE_WRITE);
922 uasm_il_beqz(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000923 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924}
925
926/*
927 * R3000 style TLB load/store/modify handlers.
928 */
929
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +0000930/*
931 * This places the pte into ENTRYLO0 and writes it with tlbwi.
932 * Then it returns.
933 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000934static void __cpuinit
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +0000935build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000937 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
938 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
939 uasm_i_tlbwi(p);
940 uasm_i_jr(p, tmp);
941 uasm_i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942}
943
944/*
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +0000945 * This places the pte into ENTRYLO0 and writes it with tlbwi
946 * or tlbwr as appropriate. This is because the index register
947 * may have the probe fail bit set as a result of a trap on a
948 * kseg2 access, i.e. without refill. Then it returns.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000950static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000951build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
952 struct uasm_reloc **r, unsigned int pte,
953 unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000955 uasm_i_mfc0(p, tmp, C0_INDEX);
956 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
957 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
958 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
959 uasm_i_tlbwi(p); /* cp0 delay */
960 uasm_i_jr(p, tmp);
961 uasm_i_rfe(p); /* branch delay */
962 uasm_l_r3000_write_probe_fail(l, *p);
963 uasm_i_tlbwr(p); /* cp0 delay */
964 uasm_i_jr(p, tmp);
965 uasm_i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700966}
967
Ralf Baechle234fcd12008-03-08 09:56:28 +0000968static void __cpuinit
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
970 unsigned int ptr)
971{
972 long pgdc = (long)pgd_current;
973
Thiemo Seufere30ec452008-01-28 20:05:38 +0000974 uasm_i_mfc0(p, pte, C0_BADVADDR);
975 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
976 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
977 uasm_i_srl(p, pte, pte, 22); /* load delay */
978 uasm_i_sll(p, pte, pte, 2);
979 uasm_i_addu(p, ptr, ptr, pte);
980 uasm_i_mfc0(p, pte, C0_CONTEXT);
981 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
982 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
983 uasm_i_addu(p, ptr, ptr, pte);
984 uasm_i_lw(p, pte, 0, ptr);
985 uasm_i_tlbp(p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986}
987
Ralf Baechle234fcd12008-03-08 09:56:28 +0000988static void __cpuinit build_r3000_tlb_load_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700989{
990 u32 *p = handle_tlbl;
Thiemo Seufere30ec452008-01-28 20:05:38 +0000991 struct uasm_label *l = labels;
992 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993
994 memset(handle_tlbl, 0, sizeof(handle_tlbl));
995 memset(labels, 0, sizeof(labels));
996 memset(relocs, 0, sizeof(relocs));
997
998 build_r3000_tlbchange_handler_head(&p, K0, K1);
999 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
Thiemo Seufere30ec452008-01-28 20:05:38 +00001000 uasm_i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001 build_make_valid(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001002 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003
Thiemo Seufere30ec452008-01-28 20:05:38 +00001004 uasm_l_nopage_tlbl(&l, p);
1005 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1006 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007
1008 if ((p - handle_tlbl) > FASTPATH_SIZE)
1009 panic("TLB load handler fastpath space exceeded");
1010
Thiemo Seufere30ec452008-01-28 20:05:38 +00001011 uasm_resolve_relocs(relocs, labels);
1012 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1013 (unsigned int)(p - handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001014
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001015 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016}
1017
Ralf Baechle234fcd12008-03-08 09:56:28 +00001018static void __cpuinit build_r3000_tlb_store_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019{
1020 u32 *p = handle_tlbs;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001021 struct uasm_label *l = labels;
1022 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001023
1024 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1025 memset(labels, 0, sizeof(labels));
1026 memset(relocs, 0, sizeof(relocs));
1027
1028 build_r3000_tlbchange_handler_head(&p, K0, K1);
1029 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
Thiemo Seufere30ec452008-01-28 20:05:38 +00001030 uasm_i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001032 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033
Thiemo Seufere30ec452008-01-28 20:05:38 +00001034 uasm_l_nopage_tlbs(&l, p);
1035 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1036 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037
1038 if ((p - handle_tlbs) > FASTPATH_SIZE)
1039 panic("TLB store handler fastpath space exceeded");
1040
Thiemo Seufere30ec452008-01-28 20:05:38 +00001041 uasm_resolve_relocs(relocs, labels);
1042 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1043 (unsigned int)(p - handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001045 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046}
1047
Ralf Baechle234fcd12008-03-08 09:56:28 +00001048static void __cpuinit build_r3000_tlb_modify_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049{
1050 u32 *p = handle_tlbm;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001051 struct uasm_label *l = labels;
1052 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053
1054 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1055 memset(labels, 0, sizeof(labels));
1056 memset(relocs, 0, sizeof(relocs));
1057
1058 build_r3000_tlbchange_handler_head(&p, K0, K1);
1059 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
Thiemo Seufere30ec452008-01-28 20:05:38 +00001060 uasm_i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001062 build_r3000_pte_reload_tlbwi(&p, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063
Thiemo Seufere30ec452008-01-28 20:05:38 +00001064 uasm_l_nopage_tlbm(&l, p);
1065 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1066 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067
1068 if ((p - handle_tlbm) > FASTPATH_SIZE)
1069 panic("TLB modify handler fastpath space exceeded");
1070
Thiemo Seufere30ec452008-01-28 20:05:38 +00001071 uasm_resolve_relocs(relocs, labels);
1072 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1073 (unsigned int)(p - handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001075 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076}
1077
1078/*
1079 * R4000 style TLB load/store/modify handlers.
1080 */
Ralf Baechle234fcd12008-03-08 09:56:28 +00001081static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +00001082build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1083 struct uasm_reloc **r, unsigned int pte,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084 unsigned int ptr)
1085{
Ralf Baechle875d43e2005-09-03 15:56:16 -07001086#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1088#else
1089 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1090#endif
1091
Thiemo Seufere30ec452008-01-28 20:05:38 +00001092 UASM_i_MFC0(p, pte, C0_BADVADDR);
1093 UASM_i_LW(p, ptr, 0, ptr);
1094 UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1095 uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1096 UASM_i_ADDU(p, ptr, ptr, pte);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097
1098#ifdef CONFIG_SMP
Thiemo Seufere30ec452008-01-28 20:05:38 +00001099 uasm_l_smp_pgtable_change(l, *p);
1100#endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001101 iPTE_LW(p, l, pte, ptr); /* get even pte */
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001102 if (!m4kc_tlbp_war())
1103 build_tlb_probe_entry(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104}
1105
Ralf Baechle234fcd12008-03-08 09:56:28 +00001106static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +00001107build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1108 struct uasm_reloc **r, unsigned int tmp,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109 unsigned int ptr)
1110{
Thiemo Seufere30ec452008-01-28 20:05:38 +00001111 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1112 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113 build_update_entries(p, tmp, ptr);
1114 build_tlb_write_entry(p, l, r, tlb_indexed);
Thiemo Seufere30ec452008-01-28 20:05:38 +00001115 uasm_l_leave(l, *p);
1116 uasm_i_eret(p); /* return from trap */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117
Ralf Baechle875d43e2005-09-03 15:56:16 -07001118#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1120#endif
1121}
1122
Ralf Baechle234fcd12008-03-08 09:56:28 +00001123static void __cpuinit build_r4000_tlb_load_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124{
1125 u32 *p = handle_tlbl;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001126 struct uasm_label *l = labels;
1127 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128
1129 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1130 memset(labels, 0, sizeof(labels));
1131 memset(relocs, 0, sizeof(relocs));
1132
1133 if (bcm1250_m3_war()) {
Thiemo Seufere30ec452008-01-28 20:05:38 +00001134 UASM_i_MFC0(&p, K0, C0_BADVADDR);
1135 UASM_i_MFC0(&p, K1, C0_ENTRYHI);
1136 uasm_i_xor(&p, K0, K0, K1);
1137 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1138 uasm_il_bnez(&p, &r, K0, label_leave);
1139 /* No need for uasm_i_nop */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140 }
1141
1142 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1143 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001144 if (m4kc_tlbp_war())
1145 build_tlb_probe_entry(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 build_make_valid(&p, &r, K0, K1);
1147 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1148
Thiemo Seufere30ec452008-01-28 20:05:38 +00001149 uasm_l_nopage_tlbl(&l, p);
1150 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1151 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152
1153 if ((p - handle_tlbl) > FASTPATH_SIZE)
1154 panic("TLB load handler fastpath space exceeded");
1155
Thiemo Seufere30ec452008-01-28 20:05:38 +00001156 uasm_resolve_relocs(relocs, labels);
1157 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1158 (unsigned int)(p - handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001160 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161}
1162
Ralf Baechle234fcd12008-03-08 09:56:28 +00001163static void __cpuinit build_r4000_tlb_store_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164{
1165 u32 *p = handle_tlbs;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001166 struct uasm_label *l = labels;
1167 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168
1169 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1170 memset(labels, 0, sizeof(labels));
1171 memset(relocs, 0, sizeof(relocs));
1172
1173 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1174 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001175 if (m4kc_tlbp_war())
1176 build_tlb_probe_entry(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001177 build_make_write(&p, &r, K0, K1);
1178 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1179
Thiemo Seufere30ec452008-01-28 20:05:38 +00001180 uasm_l_nopage_tlbs(&l, p);
1181 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1182 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183
1184 if ((p - handle_tlbs) > FASTPATH_SIZE)
1185 panic("TLB store handler fastpath space exceeded");
1186
Thiemo Seufere30ec452008-01-28 20:05:38 +00001187 uasm_resolve_relocs(relocs, labels);
1188 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1189 (unsigned int)(p - handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001191 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001192}
1193
Ralf Baechle234fcd12008-03-08 09:56:28 +00001194static void __cpuinit build_r4000_tlb_modify_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001195{
1196 u32 *p = handle_tlbm;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001197 struct uasm_label *l = labels;
1198 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001199
1200 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1201 memset(labels, 0, sizeof(labels));
1202 memset(relocs, 0, sizeof(relocs));
1203
1204 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1205 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001206 if (m4kc_tlbp_war())
1207 build_tlb_probe_entry(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208 /* Present and writable bits set, set accessed and dirty bits. */
1209 build_make_write(&p, &r, K0, K1);
1210 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1211
Thiemo Seufere30ec452008-01-28 20:05:38 +00001212 uasm_l_nopage_tlbm(&l, p);
1213 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1214 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215
1216 if ((p - handle_tlbm) > FASTPATH_SIZE)
1217 panic("TLB modify handler fastpath space exceeded");
1218
Thiemo Seufere30ec452008-01-28 20:05:38 +00001219 uasm_resolve_relocs(relocs, labels);
1220 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1221 (unsigned int)(p - handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001223 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001224}
1225
Ralf Baechle234fcd12008-03-08 09:56:28 +00001226void __cpuinit build_tlb_refill_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227{
1228 /*
1229 * The refill handler is generated per-CPU, multi-node systems
1230 * may have local storage for it. The other handlers are only
1231 * needed once.
1232 */
1233 static int run_once = 0;
1234
Ralf Baechle10cc3522007-10-11 23:46:15 +01001235 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236 case CPU_R2000:
1237 case CPU_R3000:
1238 case CPU_R3000A:
1239 case CPU_R3081E:
1240 case CPU_TX3912:
1241 case CPU_TX3922:
1242 case CPU_TX3927:
1243 build_r3000_tlb_refill_handler();
1244 if (!run_once) {
1245 build_r3000_tlb_load_handler();
1246 build_r3000_tlb_store_handler();
1247 build_r3000_tlb_modify_handler();
1248 run_once++;
1249 }
1250 break;
1251
1252 case CPU_R6000:
1253 case CPU_R6000A:
1254 panic("No R6000 TLB refill handler yet");
1255 break;
1256
1257 case CPU_R8000:
1258 panic("No R8000 TLB refill handler yet");
1259 break;
1260
1261 default:
1262 build_r4000_tlb_refill_handler();
1263 if (!run_once) {
1264 build_r4000_tlb_load_handler();
1265 build_r4000_tlb_store_handler();
1266 build_r4000_tlb_modify_handler();
1267 run_once++;
1268 }
1269 }
1270}
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001271
Ralf Baechle234fcd12008-03-08 09:56:28 +00001272void __cpuinit flush_tlb_handlers(void)
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001273{
1274 flush_icache_range((unsigned long)handle_tlbl,
1275 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
1276 flush_icache_range((unsigned long)handle_tlbs,
1277 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
1278 flush_icache_range((unsigned long)handle_tlbm,
1279 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
1280}