Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Marvell Xenon SDHC as a platform device |
| 3 | * |
| 4 | * Copyright (C) 2016 Marvell, All Rights Reserved. |
| 5 | * |
| 6 | * Author: Hu Ziji <huziji@marvell.com> |
| 7 | * Date: 2016-8-24 |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation version 2. |
| 12 | * |
| 13 | * Inspired by Jisheng Zhang <jszhang@marvell.com> |
| 14 | * Special thanks to Video BG4 project team. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/ktime.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/of.h> |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 21 | #include <linux/pm.h> |
| 22 | #include <linux/pm_runtime.h> |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 23 | |
| 24 | #include "sdhci-pltfm.h" |
| 25 | #include "sdhci-xenon.h" |
| 26 | |
| 27 | static int xenon_enable_internal_clk(struct sdhci_host *host) |
| 28 | { |
| 29 | u32 reg; |
| 30 | ktime_t timeout; |
| 31 | |
| 32 | reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); |
| 33 | reg |= SDHCI_CLOCK_INT_EN; |
| 34 | sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL); |
| 35 | /* Wait max 20 ms */ |
| 36 | timeout = ktime_add_ms(ktime_get(), 20); |
Adrian Hunter | 3d49c3d | 2018-12-10 10:56:26 +0200 | [diff] [blame] | 37 | while (1) { |
| 38 | bool timedout = ktime_after(ktime_get(), timeout); |
| 39 | |
| 40 | reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 41 | if (reg & SDHCI_CLOCK_INT_STABLE) |
| 42 | break; |
| 43 | if (timedout) { |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 44 | dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); |
| 45 | return -ETIMEDOUT; |
| 46 | } |
| 47 | usleep_range(900, 1100); |
| 48 | } |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | /* Set SDCLK-off-while-idle */ |
| 54 | static void xenon_set_sdclk_off_idle(struct sdhci_host *host, |
| 55 | unsigned char sdhc_id, bool enable) |
| 56 | { |
| 57 | u32 reg; |
| 58 | u32 mask; |
| 59 | |
| 60 | reg = sdhci_readl(host, XENON_SYS_OP_CTRL); |
| 61 | /* Get the bit shift basing on the SDHC index */ |
| 62 | mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id)); |
| 63 | if (enable) |
| 64 | reg |= mask; |
| 65 | else |
| 66 | reg &= ~mask; |
| 67 | |
| 68 | sdhci_writel(host, reg, XENON_SYS_OP_CTRL); |
| 69 | } |
| 70 | |
| 71 | /* Enable/Disable the Auto Clock Gating function */ |
| 72 | static void xenon_set_acg(struct sdhci_host *host, bool enable) |
| 73 | { |
| 74 | u32 reg; |
| 75 | |
| 76 | reg = sdhci_readl(host, XENON_SYS_OP_CTRL); |
| 77 | if (enable) |
| 78 | reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK; |
| 79 | else |
| 80 | reg |= XENON_AUTO_CLKGATE_DISABLE_MASK; |
| 81 | sdhci_writel(host, reg, XENON_SYS_OP_CTRL); |
| 82 | } |
| 83 | |
| 84 | /* Enable this SDHC */ |
| 85 | static void xenon_enable_sdhc(struct sdhci_host *host, |
| 86 | unsigned char sdhc_id) |
| 87 | { |
| 88 | u32 reg; |
| 89 | |
| 90 | reg = sdhci_readl(host, XENON_SYS_OP_CTRL); |
| 91 | reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT); |
| 92 | sdhci_writel(host, reg, XENON_SYS_OP_CTRL); |
| 93 | |
| 94 | host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; |
| 95 | /* |
| 96 | * Force to clear BUS_TEST to |
| 97 | * skip bus_test_pre and bus_test_post |
| 98 | */ |
| 99 | host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; |
| 100 | } |
| 101 | |
| 102 | /* Disable this SDHC */ |
| 103 | static void xenon_disable_sdhc(struct sdhci_host *host, |
| 104 | unsigned char sdhc_id) |
| 105 | { |
| 106 | u32 reg; |
| 107 | |
| 108 | reg = sdhci_readl(host, XENON_SYS_OP_CTRL); |
| 109 | reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT); |
| 110 | sdhci_writel(host, reg, XENON_SYS_OP_CTRL); |
| 111 | } |
| 112 | |
| 113 | /* Enable Parallel Transfer Mode */ |
| 114 | static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host, |
| 115 | unsigned char sdhc_id) |
| 116 | { |
| 117 | u32 reg; |
| 118 | |
| 119 | reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); |
| 120 | reg |= BIT(sdhc_id); |
| 121 | sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); |
| 122 | } |
| 123 | |
| 124 | /* Mask command conflict error */ |
| 125 | static void xenon_mask_cmd_conflict_err(struct sdhci_host *host) |
| 126 | { |
| 127 | u32 reg; |
| 128 | |
| 129 | reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); |
| 130 | reg |= XENON_MASK_CMD_CONFLICT_ERR; |
| 131 | sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); |
| 132 | } |
| 133 | |
| 134 | static void xenon_retune_setup(struct sdhci_host *host) |
| 135 | { |
| 136 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 137 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 138 | u32 reg; |
| 139 | |
| 140 | /* Disable the Re-Tuning Request functionality */ |
| 141 | reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL); |
| 142 | reg &= ~XENON_RETUNING_COMPATIBLE; |
| 143 | sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL); |
| 144 | |
| 145 | /* Disable the Re-tuning Interrupt */ |
| 146 | reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); |
| 147 | reg &= ~SDHCI_INT_RETUNE; |
| 148 | sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE); |
| 149 | reg = sdhci_readl(host, SDHCI_INT_ENABLE); |
| 150 | reg &= ~SDHCI_INT_RETUNE; |
| 151 | sdhci_writel(host, reg, SDHCI_INT_ENABLE); |
| 152 | |
| 153 | /* Force to use Tuning Mode 1 */ |
| 154 | host->tuning_mode = SDHCI_TUNING_MODE_1; |
| 155 | /* Set re-tuning period */ |
| 156 | host->tuning_count = 1 << (priv->tuning_count - 1); |
| 157 | } |
| 158 | |
| 159 | /* |
| 160 | * Operations inside struct sdhci_ops |
| 161 | */ |
| 162 | /* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */ |
| 163 | static void xenon_reset_exit(struct sdhci_host *host, |
| 164 | unsigned char sdhc_id, u8 mask) |
| 165 | { |
| 166 | /* Only SOFTWARE RESET ALL will clear the register setting */ |
| 167 | if (!(mask & SDHCI_RESET_ALL)) |
| 168 | return; |
| 169 | |
| 170 | /* Disable tuning request and auto-retuning again */ |
| 171 | xenon_retune_setup(host); |
| 172 | |
| 173 | xenon_set_acg(host, true); |
| 174 | |
| 175 | xenon_set_sdclk_off_idle(host, sdhc_id, false); |
| 176 | |
| 177 | xenon_mask_cmd_conflict_err(host); |
| 178 | } |
| 179 | |
| 180 | static void xenon_reset(struct sdhci_host *host, u8 mask) |
| 181 | { |
| 182 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 183 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 184 | |
| 185 | sdhci_reset(host, mask); |
| 186 | xenon_reset_exit(host, priv->sdhc_id, mask); |
| 187 | } |
| 188 | |
| 189 | /* |
| 190 | * Xenon defines different values for HS200 and HS400 |
| 191 | * in Host_Control_2 |
| 192 | */ |
| 193 | static void xenon_set_uhs_signaling(struct sdhci_host *host, |
| 194 | unsigned int timing) |
| 195 | { |
| 196 | u16 ctrl_2; |
| 197 | |
| 198 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 199 | /* Select Bus Speed Mode for host */ |
| 200 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
| 201 | if (timing == MMC_TIMING_MMC_HS200) |
| 202 | ctrl_2 |= XENON_CTRL_HS200; |
| 203 | else if (timing == MMC_TIMING_UHS_SDR104) |
| 204 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 205 | else if (timing == MMC_TIMING_UHS_SDR12) |
| 206 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
| 207 | else if (timing == MMC_TIMING_UHS_SDR25) |
| 208 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 209 | else if (timing == MMC_TIMING_UHS_SDR50) |
| 210 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; |
| 211 | else if ((timing == MMC_TIMING_UHS_DDR50) || |
| 212 | (timing == MMC_TIMING_MMC_DDR52)) |
| 213 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
| 214 | else if (timing == MMC_TIMING_MMC_HS400) |
| 215 | ctrl_2 |= XENON_CTRL_HS400; |
| 216 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 217 | } |
| 218 | |
Zhoujie Wu | 99c14fc | 2017-08-21 11:02:09 -0700 | [diff] [blame] | 219 | static void xenon_set_power(struct sdhci_host *host, unsigned char mode, |
| 220 | unsigned short vdd) |
| 221 | { |
| 222 | struct mmc_host *mmc = host->mmc; |
| 223 | u8 pwr = host->pwr; |
| 224 | |
| 225 | sdhci_set_power_noreg(host, mode, vdd); |
| 226 | |
| 227 | if (host->pwr == pwr) |
| 228 | return; |
| 229 | |
| 230 | if (host->pwr == 0) |
| 231 | vdd = 0; |
| 232 | |
| 233 | if (!IS_ERR(mmc->supply.vmmc)) |
| 234 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); |
| 235 | } |
| 236 | |
Zhoujie Wu | 8d876bf | 2017-12-18 14:38:47 -0800 | [diff] [blame] | 237 | static void xenon_voltage_switch(struct sdhci_host *host) |
| 238 | { |
| 239 | /* Wait for 5ms after set 1.8V signal enable bit */ |
| 240 | usleep_range(5000, 5500); |
Marek Behún | 82e242c | 2020-04-20 10:04:44 +0200 | [diff] [blame] | 241 | |
| 242 | /* |
| 243 | * For some reason the controller's Host Control2 register reports |
| 244 | * the bit representing 1.8V signaling as 0 when read after it was |
| 245 | * written as 1. Subsequent read reports 1. |
| 246 | * |
| 247 | * Since this may cause some issues, do an empty read of the Host |
| 248 | * Control2 register here to circumvent this. |
| 249 | */ |
| 250 | sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Zhoujie Wu | 8d876bf | 2017-12-18 14:38:47 -0800 | [diff] [blame] | 251 | } |
| 252 | |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 253 | static const struct sdhci_ops sdhci_xenon_ops = { |
Zhoujie Wu | 8d876bf | 2017-12-18 14:38:47 -0800 | [diff] [blame] | 254 | .voltage_switch = xenon_voltage_switch, |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 255 | .set_clock = sdhci_set_clock, |
Zhoujie Wu | 99c14fc | 2017-08-21 11:02:09 -0700 | [diff] [blame] | 256 | .set_power = xenon_set_power, |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 257 | .set_bus_width = sdhci_set_bus_width, |
| 258 | .reset = xenon_reset, |
| 259 | .set_uhs_signaling = xenon_set_uhs_signaling, |
| 260 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
| 261 | }; |
| 262 | |
| 263 | static const struct sdhci_pltfm_data sdhci_xenon_pdata = { |
| 264 | .ops = &sdhci_xenon_ops, |
| 265 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
| 266 | SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | |
| 267 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
| 268 | }; |
| 269 | |
| 270 | /* |
| 271 | * Xenon Specific Operations in mmc_host_ops |
| 272 | */ |
| 273 | static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 274 | { |
| 275 | struct sdhci_host *host = mmc_priv(mmc); |
| 276 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 277 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 278 | u32 reg; |
| 279 | |
| 280 | /* |
| 281 | * HS400/HS200/eMMC HS doesn't have Preset Value register. |
| 282 | * However, sdhci_set_ios will read HS400/HS200 Preset register. |
| 283 | * Disable Preset Value register for HS400/HS200. |
| 284 | * eMMC HS with preset_enabled set will trigger a bug in |
| 285 | * get_preset_value(). |
| 286 | */ |
| 287 | if ((ios->timing == MMC_TIMING_MMC_HS400) || |
| 288 | (ios->timing == MMC_TIMING_MMC_HS200) || |
| 289 | (ios->timing == MMC_TIMING_MMC_HS)) { |
| 290 | host->preset_enabled = false; |
| 291 | host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
| 292 | host->flags &= ~SDHCI_PV_ENABLED; |
| 293 | |
| 294 | reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 295 | reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 296 | sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); |
| 297 | } else { |
| 298 | host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
| 299 | } |
| 300 | |
| 301 | sdhci_set_ios(mmc, ios); |
Hu Ziji | 06c8b66 | 2017-03-30 17:23:00 +0200 | [diff] [blame] | 302 | xenon_phy_adj(host, ios); |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 303 | |
| 304 | if (host->clock > XENON_DEFAULT_SDCLK_FREQ) |
| 305 | xenon_set_sdclk_off_idle(host, priv->sdhc_id, true); |
| 306 | } |
| 307 | |
| 308 | static int xenon_start_signal_voltage_switch(struct mmc_host *mmc, |
| 309 | struct mmc_ios *ios) |
| 310 | { |
| 311 | struct sdhci_host *host = mmc_priv(mmc); |
| 312 | |
| 313 | /* |
| 314 | * Before SD/SDIO set signal voltage, SD bus clock should be |
| 315 | * disabled. However, sdhci_set_clock will also disable the Internal |
| 316 | * clock in mmc_set_signal_voltage(). |
| 317 | * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated. |
| 318 | * Thus here manually enable internal clock. |
| 319 | * |
| 320 | * After switch completes, it is unnecessary to disable internal clock, |
| 321 | * since keeping internal clock active obeys SD spec. |
| 322 | */ |
| 323 | xenon_enable_internal_clk(host); |
| 324 | |
Hu Ziji | 298269c | 2017-03-30 17:23:01 +0200 | [diff] [blame] | 325 | xenon_soc_pad_ctrl(host, ios->signal_voltage); |
| 326 | |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 327 | /* |
| 328 | * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable. |
| 329 | * Thus SDHCI_CTRL_VDD_180 bit might not work then. |
| 330 | * Skip the standard voltage switch to avoid any issue. |
| 331 | */ |
| 332 | if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV) |
| 333 | return 0; |
| 334 | |
| 335 | return sdhci_start_signal_voltage_switch(mmc, ios); |
| 336 | } |
| 337 | |
| 338 | /* |
| 339 | * Update card type. |
| 340 | * priv->init_card_type will be used in PHY timing adjustment. |
| 341 | */ |
| 342 | static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card) |
| 343 | { |
| 344 | struct sdhci_host *host = mmc_priv(mmc); |
| 345 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 346 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 347 | |
| 348 | /* Update card type*/ |
| 349 | priv->init_card_type = card->type; |
| 350 | } |
| 351 | |
| 352 | static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode) |
| 353 | { |
| 354 | struct sdhci_host *host = mmc_priv(mmc); |
| 355 | |
Zhoujie Wu | 468c648 | 2017-07-21 11:30:58 -0700 | [diff] [blame] | 356 | if (host->timing == MMC_TIMING_UHS_DDR50 || |
| 357 | host->timing == MMC_TIMING_MMC_DDR52) |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 358 | return 0; |
| 359 | |
| 360 | /* |
| 361 | * Currently force Xenon driver back to support mode 1 only, |
| 362 | * even though Xenon might claim to support mode 2 or mode 3. |
| 363 | * It requires more time to test mode 2/mode 3 on more platforms. |
| 364 | */ |
| 365 | if (host->tuning_mode != SDHCI_TUNING_MODE_1) |
| 366 | xenon_retune_setup(host); |
| 367 | |
| 368 | return sdhci_execute_tuning(mmc, opcode); |
| 369 | } |
| 370 | |
| 371 | static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable) |
| 372 | { |
| 373 | struct sdhci_host *host = mmc_priv(mmc); |
| 374 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 375 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 376 | u32 reg; |
| 377 | u8 sdhc_id = priv->sdhc_id; |
| 378 | |
| 379 | sdhci_enable_sdio_irq(mmc, enable); |
| 380 | |
| 381 | if (enable) { |
| 382 | /* |
| 383 | * Set SDIO Card Inserted indication |
| 384 | * to enable detecting SDIO async irq. |
| 385 | */ |
| 386 | reg = sdhci_readl(host, XENON_SYS_CFG_INFO); |
| 387 | reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT)); |
| 388 | sdhci_writel(host, reg, XENON_SYS_CFG_INFO); |
| 389 | } else { |
| 390 | /* Clear SDIO Card Inserted indication */ |
| 391 | reg = sdhci_readl(host, XENON_SYS_CFG_INFO); |
| 392 | reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT)); |
| 393 | sdhci_writel(host, reg, XENON_SYS_CFG_INFO); |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | static void xenon_replace_mmc_host_ops(struct sdhci_host *host) |
| 398 | { |
| 399 | host->mmc_host_ops.set_ios = xenon_set_ios; |
| 400 | host->mmc_host_ops.start_signal_voltage_switch = |
| 401 | xenon_start_signal_voltage_switch; |
| 402 | host->mmc_host_ops.init_card = xenon_init_card; |
| 403 | host->mmc_host_ops.execute_tuning = xenon_execute_tuning; |
| 404 | host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq; |
| 405 | } |
| 406 | |
| 407 | /* |
| 408 | * Parse Xenon specific DT properties: |
| 409 | * sdhc-id: the index of current SDHC. |
| 410 | * Refer to XENON_SYS_CFG_INFO register |
| 411 | * tun-count: the interval between re-tuning |
| 412 | */ |
| 413 | static int xenon_probe_dt(struct platform_device *pdev) |
| 414 | { |
| 415 | struct device_node *np = pdev->dev.of_node; |
| 416 | struct sdhci_host *host = platform_get_drvdata(pdev); |
| 417 | struct mmc_host *mmc = host->mmc; |
| 418 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 419 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 420 | u32 sdhc_id, nr_sdhc; |
| 421 | u32 tuning_count; |
| 422 | |
| 423 | /* Disable HS200 on Armada AP806 */ |
| 424 | if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci")) |
| 425 | host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; |
| 426 | |
| 427 | sdhc_id = 0x0; |
| 428 | if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) { |
| 429 | nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO); |
| 430 | nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK; |
| 431 | if (unlikely(sdhc_id > nr_sdhc)) { |
| 432 | dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n", |
| 433 | sdhc_id, nr_sdhc); |
| 434 | return -EINVAL; |
| 435 | } |
| 436 | } |
| 437 | priv->sdhc_id = sdhc_id; |
| 438 | |
| 439 | tuning_count = XENON_DEF_TUNING_COUNT; |
| 440 | if (!of_property_read_u32(np, "marvell,xenon-tun-count", |
| 441 | &tuning_count)) { |
| 442 | if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) { |
| 443 | dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n", |
| 444 | XENON_DEF_TUNING_COUNT); |
| 445 | tuning_count = XENON_DEF_TUNING_COUNT; |
| 446 | } |
| 447 | } |
| 448 | priv->tuning_count = tuning_count; |
| 449 | |
Hu Ziji | 06c8b66 | 2017-03-30 17:23:00 +0200 | [diff] [blame] | 450 | return xenon_phy_parse_dt(np, host); |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 451 | } |
| 452 | |
| 453 | static int xenon_sdhc_prepare(struct sdhci_host *host) |
| 454 | { |
| 455 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 456 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 457 | u8 sdhc_id = priv->sdhc_id; |
| 458 | |
| 459 | /* Enable SDHC */ |
| 460 | xenon_enable_sdhc(host, sdhc_id); |
| 461 | |
| 462 | /* Enable ACG */ |
| 463 | xenon_set_acg(host, true); |
| 464 | |
| 465 | /* Enable Parallel Transfer Mode */ |
| 466 | xenon_enable_sdhc_parallel_tran(host, sdhc_id); |
| 467 | |
| 468 | /* Disable SDCLK-Off-While-Idle before card init */ |
| 469 | xenon_set_sdclk_off_idle(host, sdhc_id, false); |
| 470 | |
| 471 | xenon_mask_cmd_conflict_err(host); |
| 472 | |
| 473 | return 0; |
| 474 | } |
| 475 | |
| 476 | static void xenon_sdhc_unprepare(struct sdhci_host *host) |
| 477 | { |
| 478 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 479 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 480 | u8 sdhc_id = priv->sdhc_id; |
| 481 | |
| 482 | /* disable SDHC */ |
| 483 | xenon_disable_sdhc(host, sdhc_id); |
| 484 | } |
| 485 | |
| 486 | static int xenon_probe(struct platform_device *pdev) |
| 487 | { |
| 488 | struct sdhci_pltfm_host *pltfm_host; |
| 489 | struct sdhci_host *host; |
Gregory CLEMENT | bb16ea1 | 2017-10-02 16:58:52 +0200 | [diff] [blame] | 490 | struct xenon_priv *priv; |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 491 | int err; |
| 492 | |
| 493 | host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata, |
| 494 | sizeof(struct xenon_priv)); |
| 495 | if (IS_ERR(host)) |
| 496 | return PTR_ERR(host); |
| 497 | |
| 498 | pltfm_host = sdhci_priv(host); |
Gregory CLEMENT | bb16ea1 | 2017-10-02 16:58:52 +0200 | [diff] [blame] | 499 | priv = sdhci_pltfm_priv(pltfm_host); |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 500 | |
| 501 | /* |
| 502 | * Link Xenon specific mmc_host_ops function, |
| 503 | * to replace standard ones in sdhci_ops. |
| 504 | */ |
| 505 | xenon_replace_mmc_host_ops(host); |
| 506 | |
| 507 | pltfm_host->clk = devm_clk_get(&pdev->dev, "core"); |
| 508 | if (IS_ERR(pltfm_host->clk)) { |
| 509 | err = PTR_ERR(pltfm_host->clk); |
| 510 | dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err); |
| 511 | goto free_pltfm; |
| 512 | } |
| 513 | err = clk_prepare_enable(pltfm_host->clk); |
| 514 | if (err) |
| 515 | goto free_pltfm; |
| 516 | |
Gregory CLEMENT | bb16ea1 | 2017-10-02 16:58:52 +0200 | [diff] [blame] | 517 | priv->axi_clk = devm_clk_get(&pdev->dev, "axi"); |
| 518 | if (IS_ERR(priv->axi_clk)) { |
| 519 | err = PTR_ERR(priv->axi_clk); |
| 520 | if (err == -EPROBE_DEFER) |
| 521 | goto err_clk; |
| 522 | } else { |
| 523 | err = clk_prepare_enable(priv->axi_clk); |
| 524 | if (err) |
| 525 | goto err_clk; |
| 526 | } |
| 527 | |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 528 | err = mmc_of_parse(host->mmc); |
| 529 | if (err) |
Gregory CLEMENT | bb16ea1 | 2017-10-02 16:58:52 +0200 | [diff] [blame] | 530 | goto err_clk_axi; |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 531 | |
| 532 | sdhci_get_of_property(pdev); |
| 533 | |
| 534 | xenon_set_acg(host, false); |
| 535 | |
| 536 | /* Xenon specific dt parse */ |
| 537 | err = xenon_probe_dt(pdev); |
| 538 | if (err) |
Gregory CLEMENT | bb16ea1 | 2017-10-02 16:58:52 +0200 | [diff] [blame] | 539 | goto err_clk_axi; |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 540 | |
| 541 | err = xenon_sdhc_prepare(host); |
| 542 | if (err) |
Gregory CLEMENT | bb16ea1 | 2017-10-02 16:58:52 +0200 | [diff] [blame] | 543 | goto err_clk_axi; |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 544 | |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 545 | pm_runtime_get_noresume(&pdev->dev); |
| 546 | pm_runtime_set_active(&pdev->dev); |
| 547 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
| 548 | pm_runtime_use_autosuspend(&pdev->dev); |
| 549 | pm_runtime_enable(&pdev->dev); |
| 550 | pm_suspend_ignore_children(&pdev->dev, 1); |
| 551 | |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 552 | err = sdhci_add_host(host); |
| 553 | if (err) |
| 554 | goto remove_sdhc; |
| 555 | |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 556 | pm_runtime_put_autosuspend(&pdev->dev); |
| 557 | |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 558 | return 0; |
| 559 | |
| 560 | remove_sdhc: |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 561 | pm_runtime_disable(&pdev->dev); |
| 562 | pm_runtime_put_noidle(&pdev->dev); |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 563 | xenon_sdhc_unprepare(host); |
Gregory CLEMENT | bb16ea1 | 2017-10-02 16:58:52 +0200 | [diff] [blame] | 564 | err_clk_axi: |
| 565 | clk_disable_unprepare(priv->axi_clk); |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 566 | err_clk: |
| 567 | clk_disable_unprepare(pltfm_host->clk); |
| 568 | free_pltfm: |
| 569 | sdhci_pltfm_free(pdev); |
| 570 | return err; |
| 571 | } |
| 572 | |
| 573 | static int xenon_remove(struct platform_device *pdev) |
| 574 | { |
| 575 | struct sdhci_host *host = platform_get_drvdata(pdev); |
| 576 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Gregory CLEMENT | bb16ea1 | 2017-10-02 16:58:52 +0200 | [diff] [blame] | 577 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 578 | |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 579 | pm_runtime_get_sync(&pdev->dev); |
| 580 | pm_runtime_disable(&pdev->dev); |
| 581 | pm_runtime_put_noidle(&pdev->dev); |
| 582 | |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 583 | sdhci_remove_host(host, 0); |
| 584 | |
Hu Ziji | 4cc59df | 2017-04-28 10:34:59 +0800 | [diff] [blame] | 585 | xenon_sdhc_unprepare(host); |
Gregory CLEMENT | bb16ea1 | 2017-10-02 16:58:52 +0200 | [diff] [blame] | 586 | clk_disable_unprepare(priv->axi_clk); |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 587 | clk_disable_unprepare(pltfm_host->clk); |
| 588 | |
| 589 | sdhci_pltfm_free(pdev); |
| 590 | |
| 591 | return 0; |
| 592 | } |
| 593 | |
Hu Ziji | a0fd95b | 2017-07-12 15:16:19 -0700 | [diff] [blame] | 594 | #ifdef CONFIG_PM_SLEEP |
| 595 | static int xenon_suspend(struct device *dev) |
| 596 | { |
| 597 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 598 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 599 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
Hu Ziji | a0fd95b | 2017-07-12 15:16:19 -0700 | [diff] [blame] | 600 | int ret; |
| 601 | |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 602 | ret = pm_runtime_force_suspend(dev); |
Hu Ziji | a0fd95b | 2017-07-12 15:16:19 -0700 | [diff] [blame] | 603 | |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 604 | priv->restore_needed = true; |
Hu Ziji | a0fd95b | 2017-07-12 15:16:19 -0700 | [diff] [blame] | 605 | return ret; |
| 606 | } |
Hu Ziji | a0fd95b | 2017-07-12 15:16:19 -0700 | [diff] [blame] | 607 | #endif |
| 608 | |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 609 | #ifdef CONFIG_PM |
| 610 | static int xenon_runtime_suspend(struct device *dev) |
| 611 | { |
| 612 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 613 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 614 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 615 | int ret; |
| 616 | |
| 617 | ret = sdhci_runtime_suspend_host(host); |
| 618 | if (ret) |
| 619 | return ret; |
| 620 | |
| 621 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
| 622 | mmc_retune_needed(host->mmc); |
| 623 | |
| 624 | clk_disable_unprepare(pltfm_host->clk); |
| 625 | /* |
| 626 | * Need to update the priv->clock here, or when runtime resume |
| 627 | * back, phy don't aware the clock change and won't adjust phy |
| 628 | * which will cause cmd err |
| 629 | */ |
| 630 | priv->clock = 0; |
| 631 | return 0; |
| 632 | } |
| 633 | |
| 634 | static int xenon_runtime_resume(struct device *dev) |
| 635 | { |
| 636 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 637 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 638 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 639 | int ret; |
| 640 | |
| 641 | ret = clk_prepare_enable(pltfm_host->clk); |
| 642 | if (ret) { |
| 643 | dev_err(dev, "can't enable mainck\n"); |
| 644 | return ret; |
| 645 | } |
| 646 | |
| 647 | if (priv->restore_needed) { |
| 648 | ret = xenon_sdhc_prepare(host); |
| 649 | if (ret) |
| 650 | goto out; |
| 651 | priv->restore_needed = false; |
| 652 | } |
| 653 | |
| 654 | ret = sdhci_runtime_resume_host(host); |
| 655 | if (ret) |
| 656 | goto out; |
| 657 | return 0; |
| 658 | out: |
| 659 | clk_disable_unprepare(pltfm_host->clk); |
| 660 | return ret; |
| 661 | } |
| 662 | #endif /* CONFIG_PM */ |
| 663 | |
| 664 | static const struct dev_pm_ops sdhci_xenon_dev_pm_ops = { |
| 665 | SET_SYSTEM_SLEEP_PM_OPS(xenon_suspend, |
| 666 | pm_runtime_force_resume) |
| 667 | SET_RUNTIME_PM_OPS(xenon_runtime_suspend, |
| 668 | xenon_runtime_resume, |
| 669 | NULL) |
| 670 | }; |
Hu Ziji | a0fd95b | 2017-07-12 15:16:19 -0700 | [diff] [blame] | 671 | |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 672 | static const struct of_device_id sdhci_xenon_dt_ids[] = { |
| 673 | { .compatible = "marvell,armada-ap806-sdhci",}, |
| 674 | { .compatible = "marvell,armada-cp110-sdhci",}, |
| 675 | { .compatible = "marvell,armada-3700-sdhci",}, |
| 676 | {} |
| 677 | }; |
| 678 | MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids); |
| 679 | |
| 680 | static struct platform_driver sdhci_xenon_driver = { |
| 681 | .driver = { |
| 682 | .name = "xenon-sdhci", |
| 683 | .of_match_table = sdhci_xenon_dt_ids, |
Zhoujie Wu | a027b2c | 2017-08-29 11:54:49 -0700 | [diff] [blame] | 684 | .pm = &sdhci_xenon_dev_pm_ops, |
Hu Ziji | 3a3748d | 2017-03-30 17:22:59 +0200 | [diff] [blame] | 685 | }, |
| 686 | .probe = xenon_probe, |
| 687 | .remove = xenon_remove, |
| 688 | }; |
| 689 | |
| 690 | module_platform_driver(sdhci_xenon_driver); |
| 691 | |
| 692 | MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC"); |
| 693 | MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>"); |
| 694 | MODULE_LICENSE("GPL v2"); |