blob: d99af4ef9c6444f73e7044c7447557fbca4b4ee1 [file] [log] [blame]
Stephen Warrena7db2c12011-10-25 02:01:28 +00001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Stephen Warrena7db2c12011-10-25 02:01:28 +00005
6/ {
7 model = "Compulab TrimSlice board";
8 compatible = "compulab,trimslice", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000c500/rtc@56";
12 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080013 serial0 = &uarta;
Stephen Warren553c0a22013-12-09 14:43:59 -070014 };
15
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060016 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060017 reg = <0x00000000 0x40000000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +000018 };
19
Stephen Warren58ecb232013-11-25 17:53:16 -070020 host1x@50000000 {
21 hdmi@54280000 {
Thierry Redingdced3e32012-09-20 10:39:20 +020022 status = "okay";
23
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
26
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070028 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
29 GPIO_ACTIVE_HIGH>;
Thierry Redingdced3e32012-09-20 10:39:20 +020030 };
31 };
32
Stephen Warren58ecb232013-11-25 17:53:16 -070033 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060034 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
36
37 state_default: pinmux {
38 ata {
39 nvidia,pins = "ata";
40 nvidia,function = "ide";
41 };
42 atb {
43 nvidia,pins = "atb", "gma";
44 nvidia,function = "sdio4";
45 };
46 atc {
47 nvidia,pins = "atc", "gmb";
48 nvidia,function = "nand";
49 };
50 atd {
51 nvidia,pins = "atd", "ate", "gme", "pta";
52 nvidia,function = "gmi";
53 };
54 cdev1 {
55 nvidia,pins = "cdev1";
56 nvidia,function = "plla_out";
57 };
58 cdev2 {
59 nvidia,pins = "cdev2";
60 nvidia,function = "pllp_out4";
61 };
62 crtp {
63 nvidia,pins = "crtp";
64 nvidia,function = "crt";
65 };
66 csus {
67 nvidia,pins = "csus";
68 nvidia,function = "vi_sensor_clk";
69 };
70 dap1 {
71 nvidia,pins = "dap1";
72 nvidia,function = "dap1";
73 };
74 dap2 {
75 nvidia,pins = "dap2";
76 nvidia,function = "dap2";
77 };
78 dap3 {
79 nvidia,pins = "dap3";
80 nvidia,function = "dap3";
81 };
82 dap4 {
83 nvidia,pins = "dap4";
84 nvidia,function = "dap4";
85 };
86 ddc {
87 nvidia,pins = "ddc";
88 nvidia,function = "i2c2";
89 };
90 dta {
91 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
92 nvidia,function = "vi";
93 };
94 dtf {
95 nvidia,pins = "dtf";
96 nvidia,function = "i2c3";
97 };
98 gmc {
99 nvidia,pins = "gmc", "gmd";
100 nvidia,function = "sflash";
101 };
102 gpu {
103 nvidia,pins = "gpu";
104 nvidia,function = "uarta";
105 };
106 gpu7 {
107 nvidia,pins = "gpu7";
108 nvidia,function = "rtck";
109 };
110 gpv {
111 nvidia,pins = "gpv", "slxa", "slxk";
112 nvidia,function = "pcie";
113 };
114 hdint {
115 nvidia,pins = "hdint";
116 nvidia,function = "hdmi";
117 };
118 i2cp {
119 nvidia,pins = "i2cp";
120 nvidia,function = "i2cp";
121 };
122 irrx {
123 nvidia,pins = "irrx", "irtx";
124 nvidia,function = "uartb";
125 };
126 kbca {
127 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
128 "kbce", "kbcf";
129 nvidia,function = "kbc";
130 };
131 lcsn {
132 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
133 "ld3", "ld4", "ld5", "ld6", "ld7",
134 "ld8", "ld9", "ld10", "ld11", "ld12",
135 "ld13", "ld14", "ld15", "ld16", "ld17",
136 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
137 "lhs", "lm0", "lm1", "lpp", "lpw0",
138 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
139 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
140 "lvs";
141 nvidia,function = "displaya";
142 };
143 owc {
144 nvidia,pins = "owc", "uac";
145 nvidia,function = "rsvd2";
146 };
147 pmc {
148 nvidia,pins = "pmc";
149 nvidia,function = "pwr_on";
150 };
151 rm {
152 nvidia,pins = "rm";
153 nvidia,function = "i2c1";
154 };
155 sdb {
156 nvidia,pins = "sdb", "sdc", "sdd";
157 nvidia,function = "pwm";
158 };
159 sdio1 {
160 nvidia,pins = "sdio1";
161 nvidia,function = "sdio1";
162 };
163 slxc {
164 nvidia,pins = "slxc", "slxd";
165 nvidia,function = "sdio3";
166 };
167 spdi {
168 nvidia,pins = "spdi", "spdo";
169 nvidia,function = "spdif";
170 };
171 spia {
172 nvidia,pins = "spia", "spib", "spic";
173 nvidia,function = "spi2";
174 };
175 spid {
176 nvidia,pins = "spid", "spie", "spif";
177 nvidia,function = "spi1";
178 };
179 spig {
180 nvidia,pins = "spig", "spih";
181 nvidia,function = "spi2_alt";
182 };
183 uaa {
184 nvidia,pins = "uaa", "uab", "uda";
185 nvidia,function = "ulpi";
186 };
187 uad {
188 nvidia,pins = "uad";
189 nvidia,function = "irda";
190 };
191 uca {
192 nvidia,pins = "uca", "ucb";
193 nvidia,function = "uartc";
194 };
195 conf_ata {
196 nvidia,pins = "ata", "atc", "atd", "ate",
197 "crtp", "dap2", "dap3", "dap4", "dta",
198 "dtb", "dtc", "dtd", "dte", "gmb",
199 "gme", "i2cp", "pta", "slxc", "slxd",
200 "spdi", "spdo", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600203 };
204 conf_atb {
Stephen Warren563da212012-04-13 16:35:20 -0600205 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
206 "gma", "gmc", "gmd", "gpu", "gpu7",
207 "gpv", "sdio1", "slxa", "slxk", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
209 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600210 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600211 conf_ck32 {
212 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
213 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600215 };
Stephen Warren563da212012-04-13 16:35:20 -0600216 conf_csus {
217 nvidia,pins = "csus", "spia", "spib",
218 "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530219 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren563da212012-04-13 16:35:20 -0600221 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600222 conf_ddc {
223 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530224 nvidia,pull = <TEGRA_PIN_PULL_UP>;
225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600226 };
227 conf_hdint {
228 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
229 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
230 "lvp0", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530231 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600232 };
233 conf_irrx {
234 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
235 "kbcc", "kbcd", "kbce", "kbcf", "owc",
236 "spic", "spie", "spig", "spih", "uaa",
237 "uab", "uad", "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530238 nvidia,pull = <TEGRA_PIN_PULL_UP>;
239 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600240 };
241 conf_lc {
242 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530243 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600244 };
245 conf_ld0 {
246 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
247 "ld5", "ld6", "ld7", "ld8", "ld9",
248 "ld10", "ld11", "ld12", "ld13", "ld14",
249 "ld15", "ld16", "ld17", "ldi", "lhp0",
250 "lhp1", "lhp2", "lhs", "lm0", "lpp",
251 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
252 "lvs", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530253 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600254 };
255 conf_ld17_0 {
256 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
257 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530258 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600259 };
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700260 conf_spif {
261 nvidia,pins = "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530262 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
263 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700264 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600265 };
266 };
267
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600268 i2s@70002800 {
269 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600270 };
271
272 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600273 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600274 };
275
Thierry Redingdced3e32012-09-20 10:39:20 +0200276 dvi_ddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600277 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200278 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000279 };
280
Stephen Warrenfea221e2012-11-12 12:51:22 -0700281 spi@7000c380 {
282 status = "okay";
283 spi-max-frequency = <48000000>;
284 spi-flash@0 {
285 compatible = "winbond,w25q80bl";
286 reg = <0>;
287 spi-max-frequency = <48000000>;
288 };
289 };
290
Thierry Redingdced3e32012-09-20 10:39:20 +0200291 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600292 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200293 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000294 };
295
296 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600297 status = "okay";
Stephen Warrena7db2c12011-10-25 02:01:28 +0000298 clock-frequency = <400000>;
Stephen Warren081cc0a2012-04-27 09:22:44 -0600299
Stephen Warren22bfe102012-04-27 13:24:03 -0600300 codec: codec@1a {
301 compatible = "ti,tlv320aic23";
302 reg = <0x1a>;
303 };
304
Stephen Warren081cc0a2012-04-27 09:22:44 -0600305 rtc@56 {
306 compatible = "emmicro,em3027";
307 reg = <0x56>;
308 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000309 };
310
Stephen Warren58ecb232013-11-25 17:53:16 -0700311 pmc@7000e400 {
Joseph Lo47d2d632013-08-12 17:40:07 +0800312 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800313 nvidia,cpu-pwr-good-time = <5000>;
314 nvidia,cpu-pwr-off-time = <5000>;
315 nvidia,core-pwr-good-time = <3845 3845>;
316 nvidia,core-pwr-off-time = <3875>;
317 nvidia,sys-clock-req-active-high;
318 };
319
Stephen Warren58ecb232013-11-25 17:53:16 -0700320 pcie-controller@80003000 {
Thierry Reding1798efd2013-08-09 16:49:23 +0200321 status = "okay";
Thierry Redingcca86142014-05-28 16:49:12 +0200322
323 avdd-pex-supply = <&pci_vdd_reg>;
324 vdd-pex-supply = <&pci_vdd_reg>;
325 avdd-pex-pll-supply = <&pci_vdd_reg>;
326 avdd-plle-supply = <&pci_vdd_reg>;
327 vddio-pex-clk-supply = <&pci_clk_reg>;
328
Thierry Reding1798efd2013-08-09 16:49:23 +0200329 pci@1,0 {
330 status = "okay";
331 };
332 };
333
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600334 usb@c5000000 {
335 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700336 };
337
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530338 usb-phy@c5000000 {
339 status = "okay";
340 vbus-supply = <&vbus_reg>;
341 };
342
Stephen Warrenc04abb32012-05-11 17:03:26 -0600343 usb@c5004000 {
Stephen Warrena6a3dd12012-07-25 14:02:43 -0600344 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700345 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
346 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530347 };
348
349 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530350 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700351 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
352 GPIO_ACTIVE_LOW>;
Stephen Warren31c1ec92011-11-21 14:44:10 -0700353 };
354
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600355 usb@c5008000 {
356 status = "okay";
Stephen Warren1292c122011-11-21 14:44:11 -0700357 };
358
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530359 usb-phy@c5008000 {
360 status = "okay";
361 };
362
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600363 sdhci@c8000000 {
364 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200365 bus-width = <4>;
Stephen Warren1292c122011-11-21 14:44:11 -0700366 };
367
Stephen Warrena7db2c12011-10-25 02:01:28 +0000368 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600369 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700370 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
371 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200372 bus-width = <4>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000373 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600374
Joseph Lo7021d122013-04-03 19:31:27 +0800375 clocks {
376 compatible = "simple-bus";
377 #address-cells = <1>;
378 #size-cells = <0>;
379
Stephen Warren58ecb232013-11-25 17:53:16 -0700380 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800381 compatible = "fixed-clock";
382 reg=<0>;
383 #clock-cells = <0>;
384 clock-frequency = <32768>;
385 };
386 };
387
Joseph Lo5741a252013-04-03 19:31:48 +0800388 gpio-keys {
389 compatible = "gpio-keys";
390
391 power {
392 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700393 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530394 linux,code = <KEY_POWER>;
Joseph Lo5741a252013-04-03 19:31:48 +0800395 gpio-key,wakeup;
396 };
397 };
398
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700399 poweroff {
400 compatible = "gpio-poweroff";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700401 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700402 };
403
Thierry Redingdced3e32012-09-20 10:39:20 +0200404 regulators {
405 compatible = "simple-bus";
406 #address-cells = <1>;
407 #size-cells = <0>;
408
409 hdmi_vdd_reg: regulator@0 {
410 compatible = "regulator-fixed";
411 reg = <0>;
412 regulator-name = "avdd_hdmi";
413 regulator-min-microvolt = <3300000>;
414 regulator-max-microvolt = <3300000>;
415 regulator-always-on;
416 };
417
418 hdmi_pll_reg: regulator@1 {
419 compatible = "regulator-fixed";
420 reg = <1>;
421 regulator-name = "avdd_hdmi_pll";
422 regulator-min-microvolt = <1800000>;
423 regulator-max-microvolt = <1800000>;
424 regulator-always-on;
425 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530426
427 vbus_reg: regulator@2 {
428 compatible = "regulator-fixed";
429 reg = <2>;
430 regulator-name = "usb1_vbus";
431 regulator-min-microvolt = <5000000>;
432 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600433 enable-active-high;
Stephen Warren23f95ef2013-08-01 12:26:01 -0600434 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
Stephen Warren30ca2222013-08-20 14:00:13 -0600435 regulator-always-on;
436 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530437 };
Thierry Reding1798efd2013-08-09 16:49:23 +0200438
439 pci_clk_reg: regulator@3 {
440 compatible = "regulator-fixed";
441 reg = <3>;
442 regulator-name = "pci_clk";
443 regulator-min-microvolt = <3300000>;
444 regulator-max-microvolt = <3300000>;
445 regulator-always-on;
446 };
447
448 pci_vdd_reg: regulator@4 {
449 compatible = "regulator-fixed";
450 reg = <4>;
451 regulator-name = "pci_vdd";
452 regulator-min-microvolt = <1050000>;
453 regulator-max-microvolt = <1050000>;
454 regulator-always-on;
455 };
Thierry Redingdced3e32012-09-20 10:39:20 +0200456 };
457
Stephen Warrenc04abb32012-05-11 17:03:26 -0600458 sound {
459 compatible = "nvidia,tegra-audio-trimslice";
460 nvidia,i2s-controller = <&tegra_i2s1>;
461 nvidia,audio-codec = <&codec>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600462
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300463 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
464 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
465 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600466 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600467 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000468};