Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
Laxman Dewangan | 6bccbd5 | 2013-12-02 18:39:57 +0530 | [diff] [blame] | 3 | #include <dt-bindings/input/input.h> |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 4 | #include "tegra20.dtsi" |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 5 | |
| 6 | / { |
| 7 | model = "Compulab TrimSlice board"; |
| 8 | compatible = "compulab,trimslice", "nvidia,tegra20"; |
| 9 | |
Stephen Warren | 553c0a2 | 2013-12-09 14:43:59 -0700 | [diff] [blame] | 10 | aliases { |
| 11 | rtc0 = "/i2c@7000c500/rtc@56"; |
| 12 | rtc1 = "/rtc@7000e000"; |
Olof Johansson | c4574aa | 2014-11-11 12:49:30 -0800 | [diff] [blame] | 13 | serial0 = &uarta; |
Stephen Warren | 553c0a2 | 2013-12-09 14:43:59 -0700 | [diff] [blame] | 14 | }; |
| 15 | |
Stephen Warren | f9eb26a | 2012-05-11 16:17:47 -0600 | [diff] [blame] | 16 | memory { |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 17 | reg = <0x00000000 0x40000000>; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 18 | }; |
| 19 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 20 | host1x@50000000 { |
| 21 | hdmi@54280000 { |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 22 | status = "okay"; |
| 23 | |
| 24 | vdd-supply = <&hdmi_vdd_reg>; |
| 25 | pll-supply = <&hdmi_pll_reg>; |
| 26 | |
| 27 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 28 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 29 | GPIO_ACTIVE_HIGH>; |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 30 | }; |
| 31 | }; |
| 32 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 33 | pinmux@70000014 { |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 34 | pinctrl-names = "default"; |
| 35 | pinctrl-0 = <&state_default>; |
| 36 | |
| 37 | state_default: pinmux { |
| 38 | ata { |
| 39 | nvidia,pins = "ata"; |
| 40 | nvidia,function = "ide"; |
| 41 | }; |
| 42 | atb { |
| 43 | nvidia,pins = "atb", "gma"; |
| 44 | nvidia,function = "sdio4"; |
| 45 | }; |
| 46 | atc { |
| 47 | nvidia,pins = "atc", "gmb"; |
| 48 | nvidia,function = "nand"; |
| 49 | }; |
| 50 | atd { |
| 51 | nvidia,pins = "atd", "ate", "gme", "pta"; |
| 52 | nvidia,function = "gmi"; |
| 53 | }; |
| 54 | cdev1 { |
| 55 | nvidia,pins = "cdev1"; |
| 56 | nvidia,function = "plla_out"; |
| 57 | }; |
| 58 | cdev2 { |
| 59 | nvidia,pins = "cdev2"; |
| 60 | nvidia,function = "pllp_out4"; |
| 61 | }; |
| 62 | crtp { |
| 63 | nvidia,pins = "crtp"; |
| 64 | nvidia,function = "crt"; |
| 65 | }; |
| 66 | csus { |
| 67 | nvidia,pins = "csus"; |
| 68 | nvidia,function = "vi_sensor_clk"; |
| 69 | }; |
| 70 | dap1 { |
| 71 | nvidia,pins = "dap1"; |
| 72 | nvidia,function = "dap1"; |
| 73 | }; |
| 74 | dap2 { |
| 75 | nvidia,pins = "dap2"; |
| 76 | nvidia,function = "dap2"; |
| 77 | }; |
| 78 | dap3 { |
| 79 | nvidia,pins = "dap3"; |
| 80 | nvidia,function = "dap3"; |
| 81 | }; |
| 82 | dap4 { |
| 83 | nvidia,pins = "dap4"; |
| 84 | nvidia,function = "dap4"; |
| 85 | }; |
| 86 | ddc { |
| 87 | nvidia,pins = "ddc"; |
| 88 | nvidia,function = "i2c2"; |
| 89 | }; |
| 90 | dta { |
| 91 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; |
| 92 | nvidia,function = "vi"; |
| 93 | }; |
| 94 | dtf { |
| 95 | nvidia,pins = "dtf"; |
| 96 | nvidia,function = "i2c3"; |
| 97 | }; |
| 98 | gmc { |
| 99 | nvidia,pins = "gmc", "gmd"; |
| 100 | nvidia,function = "sflash"; |
| 101 | }; |
| 102 | gpu { |
| 103 | nvidia,pins = "gpu"; |
| 104 | nvidia,function = "uarta"; |
| 105 | }; |
| 106 | gpu7 { |
| 107 | nvidia,pins = "gpu7"; |
| 108 | nvidia,function = "rtck"; |
| 109 | }; |
| 110 | gpv { |
| 111 | nvidia,pins = "gpv", "slxa", "slxk"; |
| 112 | nvidia,function = "pcie"; |
| 113 | }; |
| 114 | hdint { |
| 115 | nvidia,pins = "hdint"; |
| 116 | nvidia,function = "hdmi"; |
| 117 | }; |
| 118 | i2cp { |
| 119 | nvidia,pins = "i2cp"; |
| 120 | nvidia,function = "i2cp"; |
| 121 | }; |
| 122 | irrx { |
| 123 | nvidia,pins = "irrx", "irtx"; |
| 124 | nvidia,function = "uartb"; |
| 125 | }; |
| 126 | kbca { |
| 127 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 128 | "kbce", "kbcf"; |
| 129 | nvidia,function = "kbc"; |
| 130 | }; |
| 131 | lcsn { |
| 132 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", |
| 133 | "ld3", "ld4", "ld5", "ld6", "ld7", |
| 134 | "ld8", "ld9", "ld10", "ld11", "ld12", |
| 135 | "ld13", "ld14", "ld15", "ld16", "ld17", |
| 136 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", |
| 137 | "lhs", "lm0", "lm1", "lpp", "lpw0", |
| 138 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", |
| 139 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", |
| 140 | "lvs"; |
| 141 | nvidia,function = "displaya"; |
| 142 | }; |
| 143 | owc { |
| 144 | nvidia,pins = "owc", "uac"; |
| 145 | nvidia,function = "rsvd2"; |
| 146 | }; |
| 147 | pmc { |
| 148 | nvidia,pins = "pmc"; |
| 149 | nvidia,function = "pwr_on"; |
| 150 | }; |
| 151 | rm { |
| 152 | nvidia,pins = "rm"; |
| 153 | nvidia,function = "i2c1"; |
| 154 | }; |
| 155 | sdb { |
| 156 | nvidia,pins = "sdb", "sdc", "sdd"; |
| 157 | nvidia,function = "pwm"; |
| 158 | }; |
| 159 | sdio1 { |
| 160 | nvidia,pins = "sdio1"; |
| 161 | nvidia,function = "sdio1"; |
| 162 | }; |
| 163 | slxc { |
| 164 | nvidia,pins = "slxc", "slxd"; |
| 165 | nvidia,function = "sdio3"; |
| 166 | }; |
| 167 | spdi { |
| 168 | nvidia,pins = "spdi", "spdo"; |
| 169 | nvidia,function = "spdif"; |
| 170 | }; |
| 171 | spia { |
| 172 | nvidia,pins = "spia", "spib", "spic"; |
| 173 | nvidia,function = "spi2"; |
| 174 | }; |
| 175 | spid { |
| 176 | nvidia,pins = "spid", "spie", "spif"; |
| 177 | nvidia,function = "spi1"; |
| 178 | }; |
| 179 | spig { |
| 180 | nvidia,pins = "spig", "spih"; |
| 181 | nvidia,function = "spi2_alt"; |
| 182 | }; |
| 183 | uaa { |
| 184 | nvidia,pins = "uaa", "uab", "uda"; |
| 185 | nvidia,function = "ulpi"; |
| 186 | }; |
| 187 | uad { |
| 188 | nvidia,pins = "uad"; |
| 189 | nvidia,function = "irda"; |
| 190 | }; |
| 191 | uca { |
| 192 | nvidia,pins = "uca", "ucb"; |
| 193 | nvidia,function = "uartc"; |
| 194 | }; |
| 195 | conf_ata { |
| 196 | nvidia,pins = "ata", "atc", "atd", "ate", |
| 197 | "crtp", "dap2", "dap3", "dap4", "dta", |
| 198 | "dtb", "dtc", "dtd", "dte", "gmb", |
| 199 | "gme", "i2cp", "pta", "slxc", "slxd", |
| 200 | "spdi", "spdo", "uda"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 201 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 202 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 203 | }; |
| 204 | conf_atb { |
Stephen Warren | 563da21 | 2012-04-13 16:35:20 -0600 | [diff] [blame] | 205 | nvidia,pins = "atb", "cdev1", "cdev2", "dap1", |
| 206 | "gma", "gmc", "gmd", "gpu", "gpu7", |
| 207 | "gpv", "sdio1", "slxa", "slxk", "uac"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 208 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 209 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 210 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 211 | conf_ck32 { |
| 212 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
| 213 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 214 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 215 | }; |
Stephen Warren | 563da21 | 2012-04-13 16:35:20 -0600 | [diff] [blame] | 216 | conf_csus { |
| 217 | nvidia,pins = "csus", "spia", "spib", |
| 218 | "spid", "spif"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 219 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 220 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 563da21 | 2012-04-13 16:35:20 -0600 | [diff] [blame] | 221 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 222 | conf_ddc { |
| 223 | nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 224 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 225 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 226 | }; |
| 227 | conf_hdint { |
| 228 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
| 229 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", |
| 230 | "lvp0", "pmc"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 231 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 232 | }; |
| 233 | conf_irrx { |
| 234 | nvidia,pins = "irrx", "irtx", "kbca", "kbcb", |
| 235 | "kbcc", "kbcd", "kbce", "kbcf", "owc", |
| 236 | "spic", "spie", "spig", "spih", "uaa", |
| 237 | "uab", "uad", "uca", "ucb"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 238 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 239 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 240 | }; |
| 241 | conf_lc { |
| 242 | nvidia,pins = "lc", "ls"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 243 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 244 | }; |
| 245 | conf_ld0 { |
| 246 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 247 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 248 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 249 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 250 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
| 251 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", |
| 252 | "lvs", "sdb"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 253 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 254 | }; |
| 255 | conf_ld17_0 { |
| 256 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 257 | "ld23_22"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 258 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 259 | }; |
Stephen Warren | bff1ea7 | 2012-12-06 14:23:52 -0700 | [diff] [blame] | 260 | conf_spif { |
| 261 | nvidia,pins = "spif"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 262 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 263 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | bff1ea7 | 2012-12-06 14:23:52 -0700 | [diff] [blame] | 264 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 265 | }; |
| 266 | }; |
| 267 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 268 | i2s@70002800 { |
| 269 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 270 | }; |
| 271 | |
| 272 | serial@70006000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 273 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 274 | }; |
| 275 | |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 276 | dvi_ddc: i2c@7000c000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 277 | status = "okay"; |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 278 | clock-frequency = <100000>; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 279 | }; |
| 280 | |
Stephen Warren | fea221e | 2012-11-12 12:51:22 -0700 | [diff] [blame] | 281 | spi@7000c380 { |
| 282 | status = "okay"; |
| 283 | spi-max-frequency = <48000000>; |
| 284 | spi-flash@0 { |
| 285 | compatible = "winbond,w25q80bl"; |
| 286 | reg = <0>; |
| 287 | spi-max-frequency = <48000000>; |
| 288 | }; |
| 289 | }; |
| 290 | |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 291 | hdmi_ddc: i2c@7000c400 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 292 | status = "okay"; |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 293 | clock-frequency = <100000>; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 294 | }; |
| 295 | |
| 296 | i2c@7000c500 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 297 | status = "okay"; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 298 | clock-frequency = <400000>; |
Stephen Warren | 081cc0a | 2012-04-27 09:22:44 -0600 | [diff] [blame] | 299 | |
Stephen Warren | 22bfe10 | 2012-04-27 13:24:03 -0600 | [diff] [blame] | 300 | codec: codec@1a { |
| 301 | compatible = "ti,tlv320aic23"; |
| 302 | reg = <0x1a>; |
| 303 | }; |
| 304 | |
Stephen Warren | 081cc0a | 2012-04-27 09:22:44 -0600 | [diff] [blame] | 305 | rtc@56 { |
| 306 | compatible = "emmicro,em3027"; |
| 307 | reg = <0x56>; |
| 308 | }; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 309 | }; |
| 310 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 311 | pmc@7000e400 { |
Joseph Lo | 47d2d63 | 2013-08-12 17:40:07 +0800 | [diff] [blame] | 312 | nvidia,suspend-mode = <1>; |
Joseph Lo | a44a019 | 2013-04-03 19:31:52 +0800 | [diff] [blame] | 313 | nvidia,cpu-pwr-good-time = <5000>; |
| 314 | nvidia,cpu-pwr-off-time = <5000>; |
| 315 | nvidia,core-pwr-good-time = <3845 3845>; |
| 316 | nvidia,core-pwr-off-time = <3875>; |
| 317 | nvidia,sys-clock-req-active-high; |
| 318 | }; |
| 319 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 320 | pcie-controller@80003000 { |
Thierry Reding | 1798efd | 2013-08-09 16:49:23 +0200 | [diff] [blame] | 321 | status = "okay"; |
Thierry Reding | cca8614 | 2014-05-28 16:49:12 +0200 | [diff] [blame] | 322 | |
| 323 | avdd-pex-supply = <&pci_vdd_reg>; |
| 324 | vdd-pex-supply = <&pci_vdd_reg>; |
| 325 | avdd-pex-pll-supply = <&pci_vdd_reg>; |
| 326 | avdd-plle-supply = <&pci_vdd_reg>; |
| 327 | vddio-pex-clk-supply = <&pci_clk_reg>; |
| 328 | |
Thierry Reding | 1798efd | 2013-08-09 16:49:23 +0200 | [diff] [blame] | 329 | pci@1,0 { |
| 330 | status = "okay"; |
| 331 | }; |
| 332 | }; |
| 333 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 334 | usb@c5000000 { |
| 335 | status = "okay"; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 336 | }; |
| 337 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 338 | usb-phy@c5000000 { |
| 339 | status = "okay"; |
| 340 | vbus-supply = <&vbus_reg>; |
| 341 | }; |
| 342 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 343 | usb@c5004000 { |
Stephen Warren | a6a3dd1 | 2012-07-25 14:02:43 -0600 | [diff] [blame] | 344 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 345 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 346 | GPIO_ACTIVE_LOW>; |
Venu Byravarasu | 9dffe3b | 2013-05-16 19:42:56 +0530 | [diff] [blame] | 347 | }; |
| 348 | |
| 349 | usb-phy@c5004000 { |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 350 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 351 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 352 | GPIO_ACTIVE_LOW>; |
Stephen Warren | 31c1ec9 | 2011-11-21 14:44:10 -0700 | [diff] [blame] | 353 | }; |
| 354 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 355 | usb@c5008000 { |
| 356 | status = "okay"; |
Stephen Warren | 1292c12 | 2011-11-21 14:44:11 -0700 | [diff] [blame] | 357 | }; |
| 358 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 359 | usb-phy@c5008000 { |
| 360 | status = "okay"; |
| 361 | }; |
| 362 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 363 | sdhci@c8000000 { |
| 364 | status = "okay"; |
Arnd Bergmann | deb88cc | 2012-05-14 22:35:04 +0200 | [diff] [blame] | 365 | bus-width = <4>; |
Stephen Warren | 1292c12 | 2011-11-21 14:44:11 -0700 | [diff] [blame] | 366 | }; |
| 367 | |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 368 | sdhci@c8000600 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 369 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 370 | cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; |
| 371 | wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; |
Arnd Bergmann | deb88cc | 2012-05-14 22:35:04 +0200 | [diff] [blame] | 372 | bus-width = <4>; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 373 | }; |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 374 | |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 375 | clocks { |
| 376 | compatible = "simple-bus"; |
| 377 | #address-cells = <1>; |
| 378 | #size-cells = <0>; |
| 379 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 380 | clk32k_in: clock@0 { |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 381 | compatible = "fixed-clock"; |
| 382 | reg=<0>; |
| 383 | #clock-cells = <0>; |
| 384 | clock-frequency = <32768>; |
| 385 | }; |
| 386 | }; |
| 387 | |
Joseph Lo | 5741a25 | 2013-04-03 19:31:48 +0800 | [diff] [blame] | 388 | gpio-keys { |
| 389 | compatible = "gpio-keys"; |
| 390 | |
| 391 | power { |
| 392 | label = "Power"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 393 | gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; |
Laxman Dewangan | 6bccbd5 | 2013-12-02 18:39:57 +0530 | [diff] [blame] | 394 | linux,code = <KEY_POWER>; |
Joseph Lo | 5741a25 | 2013-04-03 19:31:48 +0800 | [diff] [blame] | 395 | gpio-key,wakeup; |
| 396 | }; |
| 397 | }; |
| 398 | |
Stephen Warren | bff1ea7 | 2012-12-06 14:23:52 -0700 | [diff] [blame] | 399 | poweroff { |
| 400 | compatible = "gpio-poweroff"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 401 | gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; |
Stephen Warren | bff1ea7 | 2012-12-06 14:23:52 -0700 | [diff] [blame] | 402 | }; |
| 403 | |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 404 | regulators { |
| 405 | compatible = "simple-bus"; |
| 406 | #address-cells = <1>; |
| 407 | #size-cells = <0>; |
| 408 | |
| 409 | hdmi_vdd_reg: regulator@0 { |
| 410 | compatible = "regulator-fixed"; |
| 411 | reg = <0>; |
| 412 | regulator-name = "avdd_hdmi"; |
| 413 | regulator-min-microvolt = <3300000>; |
| 414 | regulator-max-microvolt = <3300000>; |
| 415 | regulator-always-on; |
| 416 | }; |
| 417 | |
| 418 | hdmi_pll_reg: regulator@1 { |
| 419 | compatible = "regulator-fixed"; |
| 420 | reg = <1>; |
| 421 | regulator-name = "avdd_hdmi_pll"; |
| 422 | regulator-min-microvolt = <1800000>; |
| 423 | regulator-max-microvolt = <1800000>; |
| 424 | regulator-always-on; |
| 425 | }; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 426 | |
| 427 | vbus_reg: regulator@2 { |
| 428 | compatible = "regulator-fixed"; |
| 429 | reg = <2>; |
| 430 | regulator-name = "usb1_vbus"; |
| 431 | regulator-min-microvolt = <5000000>; |
| 432 | regulator-max-microvolt = <5000000>; |
Stephen Warren | 9f310de | 2013-07-01 15:07:05 -0600 | [diff] [blame] | 433 | enable-active-high; |
Stephen Warren | 23f95ef | 2013-08-01 12:26:01 -0600 | [diff] [blame] | 434 | gpio = <&gpio TEGRA_GPIO(V, 2) 0>; |
Stephen Warren | 30ca222 | 2013-08-20 14:00:13 -0600 | [diff] [blame] | 435 | regulator-always-on; |
| 436 | regulator-boot-on; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 437 | }; |
Thierry Reding | 1798efd | 2013-08-09 16:49:23 +0200 | [diff] [blame] | 438 | |
| 439 | pci_clk_reg: regulator@3 { |
| 440 | compatible = "regulator-fixed"; |
| 441 | reg = <3>; |
| 442 | regulator-name = "pci_clk"; |
| 443 | regulator-min-microvolt = <3300000>; |
| 444 | regulator-max-microvolt = <3300000>; |
| 445 | regulator-always-on; |
| 446 | }; |
| 447 | |
| 448 | pci_vdd_reg: regulator@4 { |
| 449 | compatible = "regulator-fixed"; |
| 450 | reg = <4>; |
| 451 | regulator-name = "pci_vdd"; |
| 452 | regulator-min-microvolt = <1050000>; |
| 453 | regulator-max-microvolt = <1050000>; |
| 454 | regulator-always-on; |
| 455 | }; |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 456 | }; |
| 457 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 458 | sound { |
| 459 | compatible = "nvidia,tegra-audio-trimslice"; |
| 460 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 461 | nvidia,audio-codec = <&codec>; |
Stephen Warren | f9cd2b3 | 2013-03-26 16:45:52 -0600 | [diff] [blame] | 462 | |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 463 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 464 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, |
| 465 | <&tegra_car TEGRA20_CLK_CDEV1>; |
Stephen Warren | f9cd2b3 | 2013-03-26 16:45:52 -0600 | [diff] [blame] | 466 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 467 | }; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 468 | }; |