Blame - drivers/scsi/qla2xxx/qla_dbg.c - kernel/msm-4.19

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Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	2	* QLogic Fibre Channel HBA Driver
Saurav Kashyap	1e63395	2013-02-08 01:57:54 -0500	[diff] [blame]	3	* Copyright (c) 2003-2013 QLogic Corporation
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	5	* See LICENSE.qla2xxx for copyright and licensing details.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	7
				8	/*
				9	* Table for showing the current message id in use for particular level
				10	* Change this table for addition of log/debug messages.
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	11	* ----------------------------------------------------------------------
				12	* \| Level \| Last Value Used \| Holes \|
				13	* ----------------------------------------------------------------------
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	14	* \| Module Init and Probe \| 0x017d \| 0x004b,0x0141 \|
				15	* \| \| \| 0x0144,0x0146 \|
				16	* \| \| \| 0x015b-0x0160 \|
				17	* \| \| \| 0x016e-0x0170 \|
Joe Carnuccio	e8887c5	2014-04-11 16:54:17 -0400	[diff] [blame]	18	* \| Mailbox commands \| 0x118d \| 0x1018-0x1019 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	19	* \| \| \| 0x10ca \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	20	* \| \| \| 0x1115-0x1116 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	21	* \| \| \| 0x111a-0x111b \|
				22	* \| \| \| 0x1155-0x1158 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	23	* \| Device Discovery \| 0x2095 \| 0x2020-0x2022, \|
Bart Van Assche	6593d5b	2013-06-25 11:27:24 -0400	[diff] [blame]	24	* \| \| \| 0x2011-0x2012, \|
Saurav Kashyap	2a8593f	2012-08-22 14:21:27 -0400	[diff] [blame]	25	* \| \| \| 0x2016 \|
Chad Dupuis	36008cf	2013-10-03 03:21:13 -0400	[diff] [blame]	26	* \| Queue Command and IO tracing \| 0x3059 \| 0x3006-0x300b \|
Arun Easi	9e522cd	2012-08-22 14:21:31 -0400	[diff] [blame]	27	* \| \| \| 0x3027-0x3028 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	28	* \| \| \| 0x303d-0x3041 \|
				29	* \| \| \| 0x302d,0x3033 \|
				30	* \| \| \| 0x3036,0x3038 \|
				31	* \| \| \| 0x303a \|
Armen Baloyan	e8f5e95	2013-10-30 03:38:17 -0400	[diff] [blame]	32	* \| DPC Thread \| 0x4023 \| 0x4002,0x4013 \|
Santosh Vernekar	454073c	2013-08-27 01:37:48 -0400	[diff] [blame]	33	* \| Async Events \| 0x5087 \| 0x502b-0x502f \|
Giridhar Malavali	9ba56b9	2012-02-09 11:15:36 -0800	[diff] [blame]	34	* \| \| \| 0x5047,0x5052 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	35	* \| \| \| 0x5084,0x5075 \|
Chad Dupuis	a78951b	2013-08-27 01:37:34 -0400	[diff] [blame]	36	* \| \| \| 0x503d,0x5044 \|
Armen Baloyan	faef62d	2014-02-26 04:15:17 -0500	[diff] [blame]	37	* \| \| \| 0x507b \|
Armen Baloyan	71e5600	2013-08-27 01:37:38 -0400	[diff] [blame]	38	* \| Timer Routines \| 0x6012 \| \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	39	* \| User Space Interactions \| 0x70e2 \| 0x7018,0x702e \|
				40	* \| \| \| 0x7020,0x7024 \|
				41	* \| \| \| 0x7039,0x7045 \|
				42	* \| \| \| 0x7073-0x7075 \|
				43	* \| \| \| 0x70a5-0x70a6 \|
				44	* \| \| \| 0x70a8,0x70ab \|
				45	* \| \| \| 0x70ad-0x70ae \|
				46	* \| \| \| 0x70d7-0x70db \|
				47	* \| \| \| 0x70de-0x70df \|
Armen Baloyan	5854771	2013-08-27 01:37:33 -0400	[diff] [blame]	48	* \| Task Management \| 0x803d \| 0x8025-0x8026 \|
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	49	* \| \| \| 0x800b,0x8039 \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	50	* \| AER/EEH \| 0x9011 \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	51	* \| Virtual Port \| 0xa007 \| \|
Pratik Mohanty	804df80	2014-04-11 16:54:15 -0400	[diff] [blame]	52	* \| ISP82XX Specific \| 0xb155 \| 0xb002,0xb024 \|
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	53	* \| \| \| 0xb09e,0xb0ae \|
				54	* \| \| \| 0xb0e0-0xb0ef \|
				55	* \| \| \| 0xb085,0xb0dc \|
				56	* \| \| \| 0xb107,0xb108 \|
				57	* \| \| \| 0xb111,0xb11e \|
				58	* \| \| \| 0xb12c,0xb12d \|
				59	* \| \| \| 0xb13a,0xb142 \|
				60	* \| \| \| 0xb13c-0xb140 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	61	* \| \| \| 0xb149 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	62	* \| MultiQ \| 0xc00c \| \|
Joe Carnuccio	0d90c34	2014-04-11 16:54:08 -0400	[diff] [blame]	63	* \| Misc \| 0xd300 \| 0xd017-0xd019 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	64	* \| \| \| 0xd020 \|
				65	* \| \| \| 0xd02e-0xd0ff \|
				66	* \| \| \| 0xd101-0xd1fe \|
				67	* \| \| \| 0xd212-0xd2fe \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	68	* \| Target Mode \| 0xe070 \| 0xe021 \|
				69	* \| Target Mode Management \| 0xf072 \| 0xf002-0xf003 \|
				70	* \| \| \| 0xf046-0xf049 \|
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	71	* \| Target Mode Task Management \| 0x1000b \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	72	* ----------------------------------------------------------------------
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	73	*/
				74
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	75	#include "qla_def.h"
				76
				77	#include <linux/delay.h>
				78
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	79	static uint32_t ql_dbg_offset = 0x800;
				80
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	81	static inline void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	82	qla2xxx_prep_dump(struct qla_hw_data ha, struct qla2xxx_fw_dump fw_dump)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	83	{
				84	fw_dump->fw_major_version = htonl(ha->fw_major_version);
				85	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
				86	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
				87	fw_dump->fw_attributes = htonl(ha->fw_attributes);
				88
				89	fw_dump->vendor = htonl(ha->pdev->vendor);
				90	fw_dump->device = htonl(ha->pdev->device);
				91	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
				92	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
				93	}
				94
				95	static inline void *
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	96	qla2xxx_copy_queues(struct qla_hw_data ha, void ptr)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	97	{
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	98	struct req_que *req = ha->req_q_map[0];
				99	struct rsp_que *rsp = ha->rsp_q_map[0];
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	100	/* Request queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	101	memcpy(ptr, req->ring, req->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	102	sizeof(request_t));
				103
				104	/* Response queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	105	ptr += req->length * sizeof(request_t);
				106	memcpy(ptr, rsp->ring, rsp->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	107	sizeof(response_t));
				108
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	109	return ptr + (rsp->length * sizeof(response_t));
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	110	}
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	111
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	112	int
				113	qla27xx_dump_mpi_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
				114	uint32_t ram_dwords, void **nxt)
				115	{
				116	int rval;
				117	uint32_t cnt, stat, timer, dwords, idx;
				118	uint16_t mb0, mb1;
				119	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				120	dma_addr_t dump_dma = ha->gid_list_dma;
				121	uint32_t dump = (uint32_t )ha->gid_list;
				122
				123	rval = QLA_SUCCESS;
				124	mb0 = 0;
				125
				126	WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
				127	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				128
				129	dwords = qla2x00_gid_list_size(ha) / 4;
				130	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				131	cnt += dwords, addr += dwords) {
				132	if (cnt + dwords > ram_dwords)
				133	dwords = ram_dwords - cnt;
				134
				135	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				136	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				137
				138	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				139	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				140	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				141	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				142
				143	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				144	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
				145
				146	WRT_REG_WORD(&reg->mailbox9, 0);
				147	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				148
				149	ha->flags.mbox_int = 0;
				150	for (timer = 6000000; timer; timer--) {
				151	/* Check for pending interrupts. */
				152	stat = RD_REG_DWORD(&reg->host_status);
				153	if (stat & HSRX_RISC_INT) {
				154	stat &= 0xff;
				155
				156	if (stat == 0x1 \|\| stat == 0x2 \|\|
				157	stat == 0x10 \|\| stat == 0x11) {
				158	set_bit(MBX_INTERRUPT,
				159	&ha->mbx_cmd_flags);
				160
				161	mb0 = RD_REG_WORD(&reg->mailbox0);
				162	mb1 = RD_REG_WORD(&reg->mailbox1);
				163
				164	WRT_REG_DWORD(&reg->hccr,
				165	HCCRX_CLR_RISC_INT);
				166	RD_REG_DWORD(&reg->hccr);
				167	break;
				168	}
				169
				170	/* Clear this intr; it wasn't a mailbox intr */
				171	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				172	RD_REG_DWORD(&reg->hccr);
				173	}
				174	udelay(5);
				175	}
				176	ha->flags.mbox_int = 1;
				177
				178	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				179	rval = mb0 & MBS_MASK;
				180	for (idx = 0; idx < dwords; idx++)
				181	ram[cnt + idx] = IS_QLA27XX(ha) ?
				182	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
				183	} else {
				184	rval = QLA_FUNCTION_FAILED;
				185	}
				186	}
				187
				188	*nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
				189	return rval;
				190	}
				191
				192	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	193	qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	194	uint32_t ram_dwords, void **nxt)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	195	{
				196	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	197	uint32_t cnt, stat, timer, dwords, idx;
				198	uint16_t mb0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	199	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	200	dma_addr_t dump_dma = ha->gid_list_dma;
				201	uint32_t dump = (uint32_t )ha->gid_list;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	202
				203	rval = QLA_SUCCESS;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	204	mb0 = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	205
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	206	WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	207	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				208
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	209	dwords = qla2x00_gid_list_size(ha) / 4;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	210	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				211	cnt += dwords, addr += dwords) {
				212	if (cnt + dwords > ram_dwords)
				213	dwords = ram_dwords - cnt;
				214
				215	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				216	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				217
				218	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				219	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				220	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				221	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				222
				223	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				224	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	225	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				226
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	227	ha->flags.mbox_int = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	228	for (timer = 6000000; timer; timer--) {
				229	/* Check for pending interrupts. */
				230	stat = RD_REG_DWORD(&reg->host_status);
				231	if (stat & HSRX_RISC_INT) {
				232	stat &= 0xff;
				233
				234	if (stat == 0x1 \|\| stat == 0x2 \|\|
				235	stat == 0x10 \|\| stat == 0x11) {
				236	set_bit(MBX_INTERRUPT,
				237	&ha->mbx_cmd_flags);
				238
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	239	mb0 = RD_REG_WORD(&reg->mailbox0);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	240
				241	WRT_REG_DWORD(&reg->hccr,
				242	HCCRX_CLR_RISC_INT);
				243	RD_REG_DWORD(&reg->hccr);
				244	break;
				245	}
				246
				247	/* Clear this intr; it wasn't a mailbox intr */
				248	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				249	RD_REG_DWORD(&reg->hccr);
				250	}
				251	udelay(5);
				252	}
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	253	ha->flags.mbox_int = 1;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	254
				255	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	256	rval = mb0 & MBS_MASK;
				257	for (idx = 0; idx < dwords; idx++)
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	258	ram[cnt + idx] = IS_QLA27XX(ha) ?
				259	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	260	} else {
				261	rval = QLA_FUNCTION_FAILED;
				262	}
				263	}
				264
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	265	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	266	return rval;
				267	}
				268
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	269	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	270	qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	271	uint32_t cram_size, void **nxt)
				272	{
				273	int rval;
				274
				275	/* Code RAM. */
				276	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
				277	if (rval != QLA_SUCCESS)
				278	return rval;
				279
				280	/* External Memory. */
				281	return qla24xx_dump_ram(ha, 0x100000, *nxt,
				282	ha->fw_memory_size - 0x100000 + 1, nxt);
				283	}
				284
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	285	static uint32_t *
				286	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
				287	uint32_t count, uint32_t *buf)
				288	{
				289	uint32_t __iomem *dmp_reg;
				290
				291	WRT_REG_DWORD(&reg->iobase_addr, iobase);
				292	dmp_reg = &reg->iobase_window;
				293	while (count--)
				294	*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
				295
				296	return buf;
				297	}
				298
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	299	void
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	300	qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
				301	{
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	302	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	303
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	304	/* 100 usec delay is sufficient enough for hardware to pause RISC */
				305	udelay(100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	306	}
				307
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	308	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	309	qla24xx_soft_reset(struct qla_hw_data *ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	310	{
				311	int rval = QLA_SUCCESS;
				312	uint32_t cnt;
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	313	uint16_t wd;
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	314	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				315
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	316	/*
				317	* Reset RISC. The delay is dependent on system architecture.
				318	* Driver can proceed with the reset sequence after waiting
				319	* for a timeout period.
				320	*/
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	321	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				322	for (cnt = 0; cnt < 30000; cnt++) {
				323	if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
				324	break;
				325
				326	udelay(10);
				327	}
				328
				329	WRT_REG_DWORD(&reg->ctrl_status,
				330	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				331	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
				332
				333	udelay(100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	334
				335	/* Wait for soft-reset to complete. */
				336	for (cnt = 0; cnt < 30000; cnt++) {
				337	if ((RD_REG_DWORD(&reg->ctrl_status) &
				338	CSRX_ISP_SOFT_RESET) == 0)
				339	break;
				340
				341	udelay(10);
				342	}
				343	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				344	RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
				345
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	346	for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	347	rval == QLA_SUCCESS; cnt--) {
				348	if (cnt)
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	349	udelay(10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	350	else
				351	rval = QLA_FUNCTION_TIMEOUT;
				352	}
				353
				354	return rval;
				355	}
				356
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	357	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	358	qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
Andrew Vasquez	e18e963	2009-06-17 10:30:31 -0700	[diff] [blame]	359	uint32_t ram_words, void **nxt)
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	360	{
				361	int rval;
				362	uint32_t cnt, stat, timer, words, idx;
				363	uint16_t mb0;
				364	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				365	dma_addr_t dump_dma = ha->gid_list_dma;
				366	uint16_t dump = (uint16_t )ha->gid_list;
				367
				368	rval = QLA_SUCCESS;
				369	mb0 = 0;
				370
				371	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
				372	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				373
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	374	words = qla2x00_gid_list_size(ha) / 2;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	375	for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
				376	cnt += words, addr += words) {
				377	if (cnt + words > ram_words)
				378	words = ram_words - cnt;
				379
				380	WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
				381	WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
				382
				383	WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
				384	WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
				385	WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
				386	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
				387
				388	WRT_MAILBOX_REG(ha, reg, 4, words);
				389	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				390
				391	for (timer = 6000000; timer; timer--) {
				392	/* Check for pending interrupts. */
				393	stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
				394	if (stat & HSR_RISC_INT) {
				395	stat &= 0xff;
				396
				397	if (stat == 0x1 \|\| stat == 0x2) {
				398	set_bit(MBX_INTERRUPT,
				399	&ha->mbx_cmd_flags);
				400
				401	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				402
				403	/* Release mailbox registers. */
				404	WRT_REG_WORD(&reg->semaphore, 0);
				405	WRT_REG_WORD(&reg->hccr,
				406	HCCR_CLR_RISC_INT);
				407	RD_REG_WORD(&reg->hccr);
				408	break;
				409	} else if (stat == 0x10 \|\| stat == 0x11) {
				410	set_bit(MBX_INTERRUPT,
				411	&ha->mbx_cmd_flags);
				412
				413	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				414
				415	WRT_REG_WORD(&reg->hccr,
				416	HCCR_CLR_RISC_INT);
				417	RD_REG_WORD(&reg->hccr);
				418	break;
				419	}
				420
				421	/* clear this intr; it wasn't a mailbox intr */
				422	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				423	RD_REG_WORD(&reg->hccr);
				424	}
				425	udelay(5);
				426	}
				427
				428	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				429	rval = mb0 & MBS_MASK;
				430	for (idx = 0; idx < words; idx++)
				431	ram[cnt + idx] = swab16(dump[idx]);
				432	} else {
				433	rval = QLA_FUNCTION_FAILED;
				434	}
				435	}
				436
				437	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
				438	return rval;
				439	}
				440
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	441	static inline void
				442	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
				443	uint16_t *buf)
				444	{
				445	uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
				446
				447	while (count--)
				448	*buf++ = htons(RD_REG_WORD(dmp_reg++));
				449	}
				450
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	451	static inline void *
				452	qla24xx_copy_eft(struct qla_hw_data ha, void ptr)
				453	{
				454	if (!ha->eft)
				455	return ptr;
				456
				457	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
				458	return ptr + ntohl(ha->fw_dump->eft_size);
				459	}
				460
				461	static inline void *
				462	qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				463	{
				464	uint32_t cnt;
				465	uint32_t *iter_reg;
				466	struct qla2xxx_fce_chain *fcec = ptr;
				467
				468	if (!ha->fce)
				469	return ptr;
				470
				471	*last_chain = &fcec->type;
				472	fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
				473	fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
				474	fce_calc_size(ha->fce_bufs));
				475	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
				476	fcec->addr_l = htonl(LSD(ha->fce_dma));
				477	fcec->addr_h = htonl(MSD(ha->fce_dma));
				478
				479	iter_reg = fcec->eregs;
				480	for (cnt = 0; cnt < 8; cnt++)
				481	*iter_reg++ = htonl(ha->fce_mb[cnt]);
				482
				483	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
				484
Giridhar Malavali	3cb0a67	2011-11-18 09:03:11 -0800	[diff] [blame]	485	return (char *)iter_reg + ntohl(fcec->size);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	486	}
				487
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	488	static inline void *
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	489	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
				490	uint32_t **last_chain)
				491	{
				492	struct qla2xxx_mqueue_chain *q;
				493	struct qla2xxx_mqueue_header *qh;
				494	uint32_t num_queues;
				495	int que;
				496	struct {
				497	int length;
				498	void *ring;
				499	} aq, *aqp;
				500
Arun Easi	00876ae	2013-03-25 02:21:37 -0400	[diff] [blame]	501	if (!ha->tgt.atio_ring)
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	502	return ptr;
				503
				504	num_queues = 1;
				505	aqp = &aq;
				506	aqp->length = ha->tgt.atio_q_length;
				507	aqp->ring = ha->tgt.atio_ring;
				508
				509	for (que = 0; que < num_queues; que++) {
				510	/* aqp = ha->atio_q_map[que]; */
				511	q = ptr;
				512	*last_chain = &q->type;
				513	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				514	q->chain_size = htonl(
				515	sizeof(struct qla2xxx_mqueue_chain) +
				516	sizeof(struct qla2xxx_mqueue_header) +
				517	(aqp->length * sizeof(request_t)));
				518	ptr += sizeof(struct qla2xxx_mqueue_chain);
				519
				520	/* Add header. */
				521	qh = ptr;
				522	qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
				523	qh->number = htonl(que);
				524	qh->size = htonl(aqp->length * sizeof(request_t));
				525	ptr += sizeof(struct qla2xxx_mqueue_header);
				526
				527	/* Add data. */
				528	memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
				529
				530	ptr += aqp->length * sizeof(request_t);
				531	}
				532
				533	return ptr;
				534	}
				535
				536	static inline void *
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	537	qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				538	{
				539	struct qla2xxx_mqueue_chain *q;
				540	struct qla2xxx_mqueue_header *qh;
				541	struct req_que *req;
				542	struct rsp_que *rsp;
				543	int que;
				544
				545	if (!ha->mqenable)
				546	return ptr;
				547
				548	/* Request queues */
				549	for (que = 1; que < ha->max_req_queues; que++) {
				550	req = ha->req_q_map[que];
				551	if (!req)
				552	break;
				553
				554	/* Add chain. */
				555	q = ptr;
				556	*last_chain = &q->type;
				557	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				558	q->chain_size = htonl(
				559	sizeof(struct qla2xxx_mqueue_chain) +
				560	sizeof(struct qla2xxx_mqueue_header) +
				561	(req->length * sizeof(request_t)));
				562	ptr += sizeof(struct qla2xxx_mqueue_chain);
				563
				564	/* Add header. */
				565	qh = ptr;
				566	qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
				567	qh->number = htonl(que);
				568	qh->size = htonl(req->length * sizeof(request_t));
				569	ptr += sizeof(struct qla2xxx_mqueue_header);
				570
				571	/* Add data. */
				572	memcpy(ptr, req->ring, req->length * sizeof(request_t));
				573	ptr += req->length * sizeof(request_t);
				574	}
				575
				576	/* Response queues */
				577	for (que = 1; que < ha->max_rsp_queues; que++) {
				578	rsp = ha->rsp_q_map[que];
				579	if (!rsp)
				580	break;
				581
				582	/* Add chain. */
				583	q = ptr;
				584	*last_chain = &q->type;
				585	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				586	q->chain_size = htonl(
				587	sizeof(struct qla2xxx_mqueue_chain) +
				588	sizeof(struct qla2xxx_mqueue_header) +
				589	(rsp->length * sizeof(response_t)));
				590	ptr += sizeof(struct qla2xxx_mqueue_chain);
				591
				592	/* Add header. */
				593	qh = ptr;
				594	qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
				595	qh->number = htonl(que);
				596	qh->size = htonl(rsp->length * sizeof(response_t));
				597	ptr += sizeof(struct qla2xxx_mqueue_header);
				598
				599	/* Add data. */
				600	memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
				601	ptr += rsp->length * sizeof(response_t);
				602	}
				603
				604	return ptr;
				605	}
				606
				607	static inline void *
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	608	qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				609	{
				610	uint32_t cnt, que_idx;
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	611	uint8_t que_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	612	struct qla2xxx_mq_chain *mq = ptr;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	613	device_reg_t __iomem *reg;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	614
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	615	if (!ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	616	return ptr;
				617
				618	mq = ptr;
				619	*last_chain = &mq->type;
				620	mq->type = __constant_htonl(DUMP_CHAIN_MQ);
				621	mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
				622
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	623	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
				624	ha->max_req_queues : ha->max_rsp_queues;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	625	mq->count = htonl(que_cnt);
				626	for (cnt = 0; cnt < que_cnt; cnt++) {
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	627	reg = ISP_QUE_REG(ha, cnt);
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	628	que_idx = cnt * 4;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	629	mq->qregs[que_idx] =
				630	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
				631	mq->qregs[que_idx+1] =
				632	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
				633	mq->qregs[que_idx+2] =
				634	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
				635	mq->qregs[que_idx+3] =
				636	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	637	}
				638
				639	return ptr + sizeof(struct qla2xxx_mq_chain);
				640	}
				641
Giridhar Malavali	08de284	2011-08-16 11:31:44 -0700	[diff] [blame]	642	void
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	643	qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
				644	{
				645	struct qla_hw_data *ha = vha->hw;
				646
				647	if (rval != QLA_SUCCESS) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	648	ql_log(ql_log_warn, vha, 0xd000,
				649	"Failed to dump firmware (%x).\n", rval);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	650	ha->fw_dumped = 0;
				651	} else {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	652	ql_log(ql_log_info, vha, 0xd001,
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	653	"Firmware dump saved to temp buffer (%ld/%p).\n",
				654	vha->host_no, ha->fw_dump);
				655	ha->fw_dumped = 1;
				656	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
				657	}
				658	}
				659
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	660	/**
				661	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
				662	* @ha: HA context
				663	* @hardware_locked: Called with the hardware_lock
				664	*/
				665	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	666	qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	667	{
				668	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	669	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	670	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	671	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	672	uint16_t __iomem *dmp_reg;
				673	unsigned long flags;
				674	struct qla2300_fw_dump *fw;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	675	void *nxt;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	676	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	677
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	678	flags = 0;
				679
				680	if (!hardware_locked)
				681	spin_lock_irqsave(&ha->hardware_lock, flags);
				682
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	683	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	684	ql_log(ql_log_warn, vha, 0xd002,
				685	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	686	goto qla2300_fw_dump_failed;
				687	}
				688
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	689	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	690	ql_log(ql_log_warn, vha, 0xd003,
				691	"Firmware has been previously dumped (%p) "
				692	"-- ignoring request.\n",
				693	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	694	goto qla2300_fw_dump_failed;
				695	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	696	fw = &ha->fw_dump->isp.isp23;
				697	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	698
				699	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	700	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	701
				702	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	703	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	704	if (IS_QLA2300(ha)) {
				705	for (cnt = 30000;
				706	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				707	rval == QLA_SUCCESS; cnt--) {
				708	if (cnt)
				709	udelay(100);
				710	else
				711	rval = QLA_FUNCTION_TIMEOUT;
				712	}
				713	} else {
				714	RD_REG_WORD(&reg->hccr); /* PCI Posting. */
				715	udelay(10);
				716	}
				717
				718	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	719	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	720	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	721	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	722
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	723	dmp_reg = &reg->u.isp2300.req_q_in;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	724	for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	725	fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	726
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	727	dmp_reg = &reg->u.isp2300.mailbox0;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	728	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	729	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	730
				731	WRT_REG_WORD(&reg->ctrl_status, 0x40);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	732	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	733
				734	WRT_REG_WORD(&reg->ctrl_status, 0x50);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	735	qla2xxx_read_window(reg, 48, fw->dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	736
				737	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	738	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	739	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	740	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	741
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	742	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	743	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	744
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	745	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	746	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	747
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	748	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	749	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	750
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	751	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	752	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	753
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	754	WRT_REG_WORD(&reg->pcr, 0x2800);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	755	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	756
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	757	WRT_REG_WORD(&reg->pcr, 0x2A00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	758	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	759
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	760	WRT_REG_WORD(&reg->pcr, 0x2C00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	761	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	762
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	763	WRT_REG_WORD(&reg->pcr, 0x2E00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	764	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	765
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	766	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	767	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	768
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	769	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	770	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	771
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	772	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	773	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	774
				775	/* Reset RISC. */
				776	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				777	for (cnt = 0; cnt < 30000; cnt++) {
				778	if ((RD_REG_WORD(&reg->ctrl_status) &
				779	CSR_ISP_SOFT_RESET) == 0)
				780	break;
				781
				782	udelay(10);
				783	}
				784	}
				785
				786	if (!IS_QLA2300(ha)) {
				787	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				788	rval == QLA_SUCCESS; cnt--) {
				789	if (cnt)
				790	udelay(100);
				791	else
				792	rval = QLA_FUNCTION_TIMEOUT;
				793	}
				794	}
				795
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	796	/* Get RISC SRAM. */
				797	if (rval == QLA_SUCCESS)
				798	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
				799	sizeof(fw->risc_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	800
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	801	/* Get stack SRAM. */
				802	if (rval == QLA_SUCCESS)
				803	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
				804	sizeof(fw->stack_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	805
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	806	/* Get data SRAM. */
				807	if (rval == QLA_SUCCESS)
				808	rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
				809	ha->fw_memory_size - 0x11000 + 1, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	810
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	811	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	812	qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	813
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	814	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	815
				816	qla2300_fw_dump_failed:
				817	if (!hardware_locked)
				818	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				819	}
				820
				821	/**
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	822	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
				823	* @ha: HA context
				824	* @hardware_locked: Called with the hardware_lock
				825	*/
				826	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	827	qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	828	{
				829	int rval;
				830	uint32_t cnt, timer;
				831	uint16_t risc_address;
				832	uint16_t mb0, mb2;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	833	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	834	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	835	uint16_t __iomem *dmp_reg;
				836	unsigned long flags;
				837	struct qla2100_fw_dump *fw;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	838	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	839
				840	risc_address = 0;
				841	mb0 = mb2 = 0;
				842	flags = 0;
				843
				844	if (!hardware_locked)
				845	spin_lock_irqsave(&ha->hardware_lock, flags);
				846
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	847	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	848	ql_log(ql_log_warn, vha, 0xd004,
				849	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	850	goto qla2100_fw_dump_failed;
				851	}
				852
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	853	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	854	ql_log(ql_log_warn, vha, 0xd005,
				855	"Firmware has been previously dumped (%p) "
				856	"-- ignoring request.\n",
				857	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	858	goto qla2100_fw_dump_failed;
				859	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	860	fw = &ha->fw_dump->isp.isp21;
				861	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	862
				863	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	864	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	865
				866	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	867	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	868	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				869	rval == QLA_SUCCESS; cnt--) {
				870	if (cnt)
				871	udelay(100);
				872	else
				873	rval = QLA_FUNCTION_TIMEOUT;
				874	}
				875	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	876	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	877	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	878	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	879
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	880	dmp_reg = &reg->u.isp2100.mailbox0;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	881	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	882	if (cnt == 8)
				883	dmp_reg = &reg->u_end.isp2200.mailbox8;
				884
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	885	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	886	}
				887
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	888	dmp_reg = &reg->u.isp2100.unused_2[0];
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	889	for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	890	fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	891
				892	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	893	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	894	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	895	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	896
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	897	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	898	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	899
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	900	WRT_REG_WORD(&reg->pcr, 0x2100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	901	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	902
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	903	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	904	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	905
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	906	WRT_REG_WORD(&reg->pcr, 0x2300);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	907	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	908
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	909	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	910	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	911
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	912	WRT_REG_WORD(&reg->pcr, 0x2500);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	913	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	914
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	915	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	916	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	917
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	918	WRT_REG_WORD(&reg->pcr, 0x2700);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	919	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	920
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	921	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	922	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	923
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	924	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	925	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	926
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	927	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	928	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	929
				930	/* Reset the ISP. */
				931	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				932	}
				933
				934	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				935	rval == QLA_SUCCESS; cnt--) {
				936	if (cnt)
				937	udelay(100);
				938	else
				939	rval = QLA_FUNCTION_TIMEOUT;
				940	}
				941
				942	/* Pause RISC. */
				943	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
				944	(RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
				945
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	946	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	947	for (cnt = 30000;
				948	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				949	rval == QLA_SUCCESS; cnt--) {
				950	if (cnt)
				951	udelay(100);
				952	else
				953	rval = QLA_FUNCTION_TIMEOUT;
				954	}
				955	if (rval == QLA_SUCCESS) {
				956	/* Set memory configuration and timing. */
				957	if (IS_QLA2100(ha))
				958	WRT_REG_WORD(&reg->mctr, 0xf1);
				959	else
				960	WRT_REG_WORD(&reg->mctr, 0xf2);
				961	RD_REG_WORD(&reg->mctr); /* PCI Posting. */
				962
				963	/* Release RISC. */
				964	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
				965	}
				966	}
				967
				968	if (rval == QLA_SUCCESS) {
				969	/* Get RISC SRAM. */
				970	risc_address = 0x1000;
				971	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
				972	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				973	}
				974	for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
				975	cnt++, risc_address++) {
				976	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
				977	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				978
				979	for (timer = 6000000; timer != 0; timer--) {
				980	/* Check for pending interrupts. */
				981	if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
				982	if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
				983	set_bit(MBX_INTERRUPT,
				984	&ha->mbx_cmd_flags);
				985
				986	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				987	mb2 = RD_MAILBOX_REG(ha, reg, 2);
				988
				989	WRT_REG_WORD(&reg->semaphore, 0);
				990	WRT_REG_WORD(&reg->hccr,
				991	HCCR_CLR_RISC_INT);
				992	RD_REG_WORD(&reg->hccr);
				993	break;
				994	}
				995	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				996	RD_REG_WORD(&reg->hccr);
				997	}
				998	udelay(5);
				999	}
				1000
				1001	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				1002	rval = mb0 & MBS_MASK;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1003	fw->risc_ram[cnt] = htons(mb2);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1004	} else {
				1005	rval = QLA_FUNCTION_FAILED;
				1006	}
				1007	}
				1008
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1009	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1010	qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1011
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1012	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1013
				1014	qla2100_fw_dump_failed:
				1015	if (!hardware_locked)
				1016	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1017	}
				1018
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1019	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1020	qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1021	{
				1022	int rval;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1023	uint32_t cnt;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1024	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1025	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1026	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1027	uint32_t __iomem *dmp_reg;
				1028	uint32_t *iter_reg;
				1029	uint16_t __iomem *mbx_reg;
				1030	unsigned long flags;
				1031	struct qla24xx_fw_dump *fw;
				1032	uint32_t ext_mem_cnt;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1033	void *nxt;
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1034	void *nxt_chain;
				1035	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1036	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1037
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	1038	if (IS_P3P_TYPE(ha))
Giridhar Malavali	a908301	2010-04-12 17:59:55 -0700	[diff] [blame]	1039	return;
				1040
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1041	risc_address = ext_mem_cnt = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1042	flags = 0;
				1043
				1044	if (!hardware_locked)
				1045	spin_lock_irqsave(&ha->hardware_lock, flags);
				1046
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	1047	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1048	ql_log(ql_log_warn, vha, 0xd006,
				1049	"No buffer available for dump.\n");
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1050	goto qla24xx_fw_dump_failed;
				1051	}
				1052
				1053	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1054	ql_log(ql_log_warn, vha, 0xd007,
				1055	"Firmware has been previously dumped (%p) "
				1056	"-- ignoring request.\n",
				1057	ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1058	goto qla24xx_fw_dump_failed;
				1059	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1060	fw = &ha->fw_dump->isp.isp24;
				1061	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1062
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1063	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1064
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	1065	/*
				1066	* Pause RISC. No need to track timeout, as resetting the chip
				1067	* is the right approach incase of pause timeout
				1068	*/
				1069	qla24xx_pause_risc(reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1070
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1071	/* Host interface registers. */
				1072	dmp_reg = &reg->flash_addr;
				1073	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1074	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1075
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1076	/* Disable interrupts. */
				1077	WRT_REG_DWORD(&reg->ictrl, 0);
				1078	RD_REG_DWORD(&reg->ictrl);
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1079
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1080	/* Shadow registers. */
				1081	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1082	RD_REG_DWORD(&reg->iobase_addr);
				1083	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1084	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1085
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1086	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1087	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1088
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1089	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1090	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1091
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1092	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1093	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1094
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1095	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1096	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1097
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1098	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1099	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1100
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1101	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1102	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1103
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1104	/* Mailbox registers. */
				1105	mbx_reg = &reg->mailbox0;
				1106	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1107	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1108
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1109	/* Transfer sequence registers. */
				1110	iter_reg = fw->xseq_gp_reg;
				1111	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1112	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1113	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1114	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1115	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1116	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1117	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1118	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1119
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1120	qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
				1121	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1122
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1123	/* Receive sequence registers. */
				1124	iter_reg = fw->rseq_gp_reg;
				1125	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1126	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1127	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1128	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1129	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1130	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1131	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1132	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1133
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1134	qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
				1135	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1136	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1137
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1138	/* Command DMA registers. */
				1139	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1140
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1141	/* Queues. */
				1142	iter_reg = fw->req0_dma_reg;
				1143	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1144	dmp_reg = &reg->iobase_q;
				1145	for (cnt = 0; cnt < 7; cnt++)
				1146	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1147
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1148	iter_reg = fw->resp0_dma_reg;
				1149	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1150	dmp_reg = &reg->iobase_q;
				1151	for (cnt = 0; cnt < 7; cnt++)
				1152	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1153
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1154	iter_reg = fw->req1_dma_reg;
				1155	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1156	dmp_reg = &reg->iobase_q;
				1157	for (cnt = 0; cnt < 7; cnt++)
				1158	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1159
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1160	/* Transmit DMA registers. */
				1161	iter_reg = fw->xmt0_dma_reg;
				1162	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1163	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1164
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1165	iter_reg = fw->xmt1_dma_reg;
				1166	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1167	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1168
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1169	iter_reg = fw->xmt2_dma_reg;
				1170	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1171	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1172
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1173	iter_reg = fw->xmt3_dma_reg;
				1174	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1175	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1176
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1177	iter_reg = fw->xmt4_dma_reg;
				1178	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1179	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1180
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1181	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1182
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1183	/* Receive DMA registers. */
				1184	iter_reg = fw->rcvt0_data_dma_reg;
				1185	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1186	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1187
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1188	iter_reg = fw->rcvt1_data_dma_reg;
				1189	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1190	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1191
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1192	/* RISC registers. */
				1193	iter_reg = fw->risc_gp_reg;
				1194	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1195	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1196	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1197	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1198	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1199	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1200	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1201	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1202
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1203	/* Local memory controller registers. */
				1204	iter_reg = fw->lmc_reg;
				1205	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1206	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1207	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1208	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1209	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1210	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1211	qla24xx_read_window(reg, 0x3060, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1212
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1213	/* Fibre Protocol Module registers. */
				1214	iter_reg = fw->fpm_hdw_reg;
				1215	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1216	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1217	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1218	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1219	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1220	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1221	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1222	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1223	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1224	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1225	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1226	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1227
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1228	/* Frame Buffer registers. */
				1229	iter_reg = fw->fb_hdw_reg;
				1230	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1231	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1232	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1233	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1234	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1235	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1236	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1237	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1238	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1239	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1240	qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1241
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1242	rval = qla24xx_soft_reset(ha);
				1243	if (rval != QLA_SUCCESS)
				1244	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1245
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1246	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1247	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1248	if (rval != QLA_SUCCESS)
				1249	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1250
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1251	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1252
				1253	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1254
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1255	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
				1256	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
				1257	if (last_chain) {
				1258	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1259	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1260	}
				1261
				1262	/* Adjust valid length. */
				1263	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1264
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1265	qla24xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1266	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1267
				1268	qla24xx_fw_dump_failed:
				1269	if (!hardware_locked)
				1270	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1271	}
				1272
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1273	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1274	qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1275	{
				1276	int rval;
				1277	uint32_t cnt;
				1278	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1279	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1280	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1281	uint32_t __iomem *dmp_reg;
				1282	uint32_t *iter_reg;
				1283	uint16_t __iomem *mbx_reg;
				1284	unsigned long flags;
				1285	struct qla25xx_fw_dump *fw;
				1286	uint32_t ext_mem_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1287	void nxt, nxt_chain;
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1288	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1289	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1290
				1291	risc_address = ext_mem_cnt = 0;
				1292	flags = 0;
				1293
				1294	if (!hardware_locked)
				1295	spin_lock_irqsave(&ha->hardware_lock, flags);
				1296
				1297	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1298	ql_log(ql_log_warn, vha, 0xd008,
				1299	"No buffer available for dump.\n");
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1300	goto qla25xx_fw_dump_failed;
				1301	}
				1302
				1303	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1304	ql_log(ql_log_warn, vha, 0xd009,
				1305	"Firmware has been previously dumped (%p) "
				1306	"-- ignoring request.\n",
				1307	ha->fw_dump);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1308	goto qla25xx_fw_dump_failed;
				1309	}
				1310	fw = &ha->fw_dump->isp.isp25;
				1311	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1312	ha->fw_dump->version = __constant_htonl(2);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1313
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1314	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1315
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	1316	/*
				1317	* Pause RISC. No need to track timeout, as resetting the chip
				1318	* is the right approach incase of pause timeout
				1319	*/
				1320	qla24xx_pause_risc(reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1321
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1322	/* Host/Risc registers. */
				1323	iter_reg = fw->host_risc_reg;
				1324	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1325	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1326
				1327	/* PCIe registers. */
				1328	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1329	RD_REG_DWORD(&reg->iobase_addr);
				1330	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1331	dmp_reg = &reg->iobase_c4;
				1332	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1333	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1334	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1335	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1336
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1337	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1338	RD_REG_DWORD(&reg->iobase_window);
				1339
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1340	/* Host interface registers. */
				1341	dmp_reg = &reg->flash_addr;
				1342	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1343	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1344
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1345	/* Disable interrupts. */
				1346	WRT_REG_DWORD(&reg->ictrl, 0);
				1347	RD_REG_DWORD(&reg->ictrl);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1348
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1349	/* Shadow registers. */
				1350	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1351	RD_REG_DWORD(&reg->iobase_addr);
				1352	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1353	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1354
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1355	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1356	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1357
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1358	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1359	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1360
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1361	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1362	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1363
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1364	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1365	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1366
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1367	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1368	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1369
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1370	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1371	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1372
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1373	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1374	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1375
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1376	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1377	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1378
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1379	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1380	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1381
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1382	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1383	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1384
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1385	/* RISC I/O register. */
				1386	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1387	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1388
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1389	/* Mailbox registers. */
				1390	mbx_reg = &reg->mailbox0;
				1391	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1392	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1393
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1394	/* Transfer sequence registers. */
				1395	iter_reg = fw->xseq_gp_reg;
				1396	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1397	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1398	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1399	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1400	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1401	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1402	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1403	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1404
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1405	iter_reg = fw->xseq_0_reg;
				1406	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1407	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1408	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1409
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1410	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1411
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1412	/* Receive sequence registers. */
				1413	iter_reg = fw->rseq_gp_reg;
				1414	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1415	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1416	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1417	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1418	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1419	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1420	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1421	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1422
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1423	iter_reg = fw->rseq_0_reg;
				1424	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1425	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1426
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1427	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1428	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1429
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1430	/* Auxiliary sequence registers. */
				1431	iter_reg = fw->aseq_gp_reg;
				1432	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1433	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1434	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1435	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1436	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1437	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1438	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1439	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1440
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1441	iter_reg = fw->aseq_0_reg;
				1442	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1443	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1444
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1445	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1446	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1447
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1448	/* Command DMA registers. */
				1449	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1450
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1451	/* Queues. */
				1452	iter_reg = fw->req0_dma_reg;
				1453	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1454	dmp_reg = &reg->iobase_q;
				1455	for (cnt = 0; cnt < 7; cnt++)
				1456	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1457
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1458	iter_reg = fw->resp0_dma_reg;
				1459	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1460	dmp_reg = &reg->iobase_q;
				1461	for (cnt = 0; cnt < 7; cnt++)
				1462	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1463
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1464	iter_reg = fw->req1_dma_reg;
				1465	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1466	dmp_reg = &reg->iobase_q;
				1467	for (cnt = 0; cnt < 7; cnt++)
				1468	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1469
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1470	/* Transmit DMA registers. */
				1471	iter_reg = fw->xmt0_dma_reg;
				1472	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1473	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1474
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1475	iter_reg = fw->xmt1_dma_reg;
				1476	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1477	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1478
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1479	iter_reg = fw->xmt2_dma_reg;
				1480	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1481	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1482
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1483	iter_reg = fw->xmt3_dma_reg;
				1484	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1485	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1486
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1487	iter_reg = fw->xmt4_dma_reg;
				1488	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1489	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1490
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1491	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1492
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1493	/* Receive DMA registers. */
				1494	iter_reg = fw->rcvt0_data_dma_reg;
				1495	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1496	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1497
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1498	iter_reg = fw->rcvt1_data_dma_reg;
				1499	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1500	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1501
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1502	/* RISC registers. */
				1503	iter_reg = fw->risc_gp_reg;
				1504	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1505	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1506	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1507	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1508	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1509	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1510	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1511	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1512
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1513	/* Local memory controller registers. */
				1514	iter_reg = fw->lmc_reg;
				1515	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1516	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1517	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1518	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1519	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1520	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1521	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1522	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1523
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1524	/* Fibre Protocol Module registers. */
				1525	iter_reg = fw->fpm_hdw_reg;
				1526	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1527	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1528	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1529	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1530	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1531	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1532	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1533	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1534	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1535	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1536	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1537	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1538
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1539	/* Frame Buffer registers. */
				1540	iter_reg = fw->fb_hdw_reg;
				1541	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1542	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1543	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1544	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1545	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1546	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1547	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1548	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1549	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1550	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1551	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1552	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1553
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1554	/* Multi queue registers */
				1555	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1556	&last_chain);
				1557
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1558	rval = qla24xx_soft_reset(ha);
				1559	if (rval != QLA_SUCCESS)
				1560	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1561
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1562	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1563	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1564	if (rval != QLA_SUCCESS)
				1565	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1566
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1567	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1568
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1569	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1570
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1571	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1572	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1573	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1574	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1575	if (last_chain) {
				1576	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1577	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1578	}
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1579
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1580	/* Adjust valid length. */
				1581	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1582
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1583	qla25xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1584	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1585
				1586	qla25xx_fw_dump_failed:
				1587	if (!hardware_locked)
				1588	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1589	}
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1590
				1591	void
				1592	qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1593	{
				1594	int rval;
				1595	uint32_t cnt;
				1596	uint32_t risc_address;
				1597	struct qla_hw_data *ha = vha->hw;
				1598	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1599	uint32_t __iomem *dmp_reg;
				1600	uint32_t *iter_reg;
				1601	uint16_t __iomem *mbx_reg;
				1602	unsigned long flags;
				1603	struct qla81xx_fw_dump *fw;
				1604	uint32_t ext_mem_cnt;
				1605	void nxt, nxt_chain;
				1606	uint32_t *last_chain = NULL;
				1607	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1608
				1609	risc_address = ext_mem_cnt = 0;
				1610	flags = 0;
				1611
				1612	if (!hardware_locked)
				1613	spin_lock_irqsave(&ha->hardware_lock, flags);
				1614
				1615	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1616	ql_log(ql_log_warn, vha, 0xd00a,
				1617	"No buffer available for dump.\n");
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1618	goto qla81xx_fw_dump_failed;
				1619	}
				1620
				1621	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1622	ql_log(ql_log_warn, vha, 0xd00b,
				1623	"Firmware has been previously dumped (%p) "
				1624	"-- ignoring request.\n",
				1625	ha->fw_dump);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1626	goto qla81xx_fw_dump_failed;
				1627	}
				1628	fw = &ha->fw_dump->isp.isp81;
				1629	qla2xxx_prep_dump(ha, ha->fw_dump);
				1630
				1631	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1632
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	1633	/*
				1634	* Pause RISC. No need to track timeout, as resetting the chip
				1635	* is the right approach incase of pause timeout
				1636	*/
				1637	qla24xx_pause_risc(reg);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1638
				1639	/* Host/Risc registers. */
				1640	iter_reg = fw->host_risc_reg;
				1641	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1642	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1643
				1644	/* PCIe registers. */
				1645	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1646	RD_REG_DWORD(&reg->iobase_addr);
				1647	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1648	dmp_reg = &reg->iobase_c4;
				1649	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1650	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1651	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1652	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1653
				1654	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1655	RD_REG_DWORD(&reg->iobase_window);
				1656
				1657	/* Host interface registers. */
				1658	dmp_reg = &reg->flash_addr;
				1659	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1660	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1661
				1662	/* Disable interrupts. */
				1663	WRT_REG_DWORD(&reg->ictrl, 0);
				1664	RD_REG_DWORD(&reg->ictrl);
				1665
				1666	/* Shadow registers. */
				1667	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1668	RD_REG_DWORD(&reg->iobase_addr);
				1669	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1670	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1671
				1672	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1673	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1674
				1675	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1676	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1677
				1678	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1679	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1680
				1681	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1682	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1683
				1684	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1685	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1686
				1687	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1688	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1689
				1690	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1691	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1692
				1693	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1694	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1695
				1696	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1697	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1698
				1699	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1700	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1701
				1702	/* RISC I/O register. */
				1703	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1704	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1705
				1706	/* Mailbox registers. */
				1707	mbx_reg = &reg->mailbox0;
				1708	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1709	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1710
				1711	/* Transfer sequence registers. */
				1712	iter_reg = fw->xseq_gp_reg;
				1713	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1714	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1715	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1716	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1717	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1718	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1719	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1720	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1721
				1722	iter_reg = fw->xseq_0_reg;
				1723	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1724	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1725	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1726
				1727	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1728
				1729	/* Receive sequence registers. */
				1730	iter_reg = fw->rseq_gp_reg;
				1731	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1732	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1733	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1734	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1735	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1736	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1737	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1738	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1739
				1740	iter_reg = fw->rseq_0_reg;
				1741	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1742	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1743
				1744	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1745	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				1746
				1747	/* Auxiliary sequence registers. */
				1748	iter_reg = fw->aseq_gp_reg;
				1749	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1750	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1751	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1752	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1753	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1754	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1755	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1756	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				1757
				1758	iter_reg = fw->aseq_0_reg;
				1759	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1760	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				1761
				1762	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1763	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				1764
				1765	/* Command DMA registers. */
				1766	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
				1767
				1768	/* Queues. */
				1769	iter_reg = fw->req0_dma_reg;
				1770	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1771	dmp_reg = &reg->iobase_q;
				1772	for (cnt = 0; cnt < 7; cnt++)
				1773	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1774
				1775	iter_reg = fw->resp0_dma_reg;
				1776	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1777	dmp_reg = &reg->iobase_q;
				1778	for (cnt = 0; cnt < 7; cnt++)
				1779	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1780
				1781	iter_reg = fw->req1_dma_reg;
				1782	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1783	dmp_reg = &reg->iobase_q;
				1784	for (cnt = 0; cnt < 7; cnt++)
				1785	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1786
				1787	/* Transmit DMA registers. */
				1788	iter_reg = fw->xmt0_dma_reg;
				1789	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1790	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				1791
				1792	iter_reg = fw->xmt1_dma_reg;
				1793	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1794	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				1795
				1796	iter_reg = fw->xmt2_dma_reg;
				1797	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1798	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				1799
				1800	iter_reg = fw->xmt3_dma_reg;
				1801	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1802	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				1803
				1804	iter_reg = fw->xmt4_dma_reg;
				1805	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1806	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				1807
				1808	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				1809
				1810	/* Receive DMA registers. */
				1811	iter_reg = fw->rcvt0_data_dma_reg;
				1812	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1813	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				1814
				1815	iter_reg = fw->rcvt1_data_dma_reg;
				1816	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1817	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				1818
				1819	/* RISC registers. */
				1820	iter_reg = fw->risc_gp_reg;
				1821	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1822	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1823	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1824	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1825	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1826	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1827	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1828	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				1829
				1830	/* Local memory controller registers. */
				1831	iter_reg = fw->lmc_reg;
				1832	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1833	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1834	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1835	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1836	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1837	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1838	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1839	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				1840
				1841	/* Fibre Protocol Module registers. */
				1842	iter_reg = fw->fpm_hdw_reg;
				1843	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1844	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1845	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1846	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1847	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1848	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1849	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1850	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1851	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1852	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1853	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1854	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				1855	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				1856	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				1857
				1858	/* Frame Buffer registers. */
				1859	iter_reg = fw->fb_hdw_reg;
				1860	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1861	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1862	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1863	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1864	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1865	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1866	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1867	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1868	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1869	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1870	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1871	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				1872	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				1873
				1874	/* Multi queue registers */
				1875	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1876	&last_chain);
				1877
				1878	rval = qla24xx_soft_reset(ha);
				1879	if (rval != QLA_SUCCESS)
				1880	goto qla81xx_fw_dump_failed_0;
				1881
				1882	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				1883	&nxt);
				1884	if (rval != QLA_SUCCESS)
				1885	goto qla81xx_fw_dump_failed_0;
				1886
				1887	nxt = qla2xxx_copy_queues(ha, nxt);
				1888
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1889	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1890
				1891	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1892	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1893	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1894	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1895	if (last_chain) {
				1896	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1897	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1898	}
				1899
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1900	/* Adjust valid length. */
				1901	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1902
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1903	qla81xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1904	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1905
				1906	qla81xx_fw_dump_failed:
				1907	if (!hardware_locked)
				1908	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1909	}
				1910
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1911	void
				1912	qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1913	{
				1914	int rval;
				1915	uint32_t cnt, reg_data;
				1916	uint32_t risc_address;
				1917	struct qla_hw_data *ha = vha->hw;
				1918	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1919	uint32_t __iomem *dmp_reg;
				1920	uint32_t *iter_reg;
				1921	uint16_t __iomem *mbx_reg;
				1922	unsigned long flags;
				1923	struct qla83xx_fw_dump *fw;
				1924	uint32_t ext_mem_cnt;
				1925	void nxt, nxt_chain;
				1926	uint32_t *last_chain = NULL;
				1927	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1928
				1929	risc_address = ext_mem_cnt = 0;
				1930	flags = 0;
				1931
				1932	if (!hardware_locked)
				1933	spin_lock_irqsave(&ha->hardware_lock, flags);
				1934
				1935	if (!ha->fw_dump) {
				1936	ql_log(ql_log_warn, vha, 0xd00c,
				1937	"No buffer available for dump!!!\n");
				1938	goto qla83xx_fw_dump_failed;
				1939	}
				1940
				1941	if (ha->fw_dumped) {
				1942	ql_log(ql_log_warn, vha, 0xd00d,
				1943	"Firmware has been previously dumped (%p) -- ignoring "
				1944	"request...\n", ha->fw_dump);
				1945	goto qla83xx_fw_dump_failed;
				1946	}
				1947	fw = &ha->fw_dump->isp.isp83;
				1948	qla2xxx_prep_dump(ha, ha->fw_dump);
				1949
				1950	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1951
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame^]	1952	/*
				1953	* Pause RISC. No need to track timeout, as resetting the chip
				1954	* is the right approach incase of pause timeout
				1955	*/
				1956	qla24xx_pause_risc(reg);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1957
				1958	WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
				1959	dmp_reg = &reg->iobase_window;
				1960	reg_data = RD_REG_DWORD(dmp_reg);
				1961	WRT_REG_DWORD(dmp_reg, 0);
				1962
				1963	dmp_reg = &reg->unused_4_1[0];
				1964	reg_data = RD_REG_DWORD(dmp_reg);
				1965	WRT_REG_DWORD(dmp_reg, 0);
				1966
				1967	WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
				1968	dmp_reg = &reg->unused_4_1[2];
				1969	reg_data = RD_REG_DWORD(dmp_reg);
				1970	WRT_REG_DWORD(dmp_reg, 0);
				1971
				1972	/* select PCR and disable ecc checking and correction */
				1973	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1974	RD_REG_DWORD(&reg->iobase_addr);
				1975	WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
				1976
				1977	/* Host/Risc registers. */
				1978	iter_reg = fw->host_risc_reg;
				1979	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1980	iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1981	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
				1982
				1983	/* PCIe registers. */
				1984	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1985	RD_REG_DWORD(&reg->iobase_addr);
				1986	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1987	dmp_reg = &reg->iobase_c4;
				1988	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1989	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1990	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1991	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1992
				1993	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1994	RD_REG_DWORD(&reg->iobase_window);
				1995
				1996	/* Host interface registers. */
				1997	dmp_reg = &reg->flash_addr;
				1998	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1999	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				2000
				2001	/* Disable interrupts. */
				2002	WRT_REG_DWORD(&reg->ictrl, 0);
				2003	RD_REG_DWORD(&reg->ictrl);
				2004
				2005	/* Shadow registers. */
				2006	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				2007	RD_REG_DWORD(&reg->iobase_addr);
				2008	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				2009	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2010
				2011	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				2012	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2013
				2014	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				2015	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2016
				2017	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				2018	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2019
				2020	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				2021	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2022
				2023	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				2024	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2025
				2026	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				2027	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2028
				2029	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				2030	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2031
				2032	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				2033	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2034
				2035	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				2036	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2037
				2038	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				2039	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2040
				2041	/* RISC I/O register. */
				2042	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				2043	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				2044
				2045	/* Mailbox registers. */
				2046	mbx_reg = &reg->mailbox0;
				2047	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				2048	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				2049
				2050	/* Transfer sequence registers. */
				2051	iter_reg = fw->xseq_gp_reg;
				2052	iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
				2053	iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
				2054	iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
				2055	iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
				2056	iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
				2057	iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
				2058	iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
				2059	iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
				2060	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				2061	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				2062	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				2063	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				2064	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				2065	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				2066	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				2067	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				2068
				2069	iter_reg = fw->xseq_0_reg;
				2070	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				2071	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				2072	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				2073
				2074	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				2075
				2076	qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
				2077
				2078	/* Receive sequence registers. */
				2079	iter_reg = fw->rseq_gp_reg;
				2080	iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
				2081	iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
				2082	iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
				2083	iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
				2084	iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
				2085	iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
				2086	iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
				2087	iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
				2088	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				2089	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				2090	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				2091	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				2092	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				2093	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				2094	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				2095	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				2096
				2097	iter_reg = fw->rseq_0_reg;
				2098	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				2099	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				2100
				2101	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				2102	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				2103	qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
				2104
				2105	/* Auxiliary sequence registers. */
				2106	iter_reg = fw->aseq_gp_reg;
				2107	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				2108	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				2109	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				2110	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				2111	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				2112	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				2113	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				2114	iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				2115	iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
				2116	iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
				2117	iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
				2118	iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
				2119	iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
				2120	iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
				2121	iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
				2122	qla24xx_read_window(reg, 0xB170, 16, iter_reg);
				2123
				2124	iter_reg = fw->aseq_0_reg;
				2125	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				2126	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				2127
				2128	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				2129	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				2130	qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
				2131
				2132	/* Command DMA registers. */
				2133	iter_reg = fw->cmd_dma_reg;
				2134	iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
				2135	iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
				2136	iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
				2137	qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
				2138
				2139	/* Queues. */
				2140	iter_reg = fw->req0_dma_reg;
				2141	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				2142	dmp_reg = &reg->iobase_q;
				2143	for (cnt = 0; cnt < 7; cnt++)
				2144	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2145
				2146	iter_reg = fw->resp0_dma_reg;
				2147	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				2148	dmp_reg = &reg->iobase_q;
				2149	for (cnt = 0; cnt < 7; cnt++)
				2150	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2151
				2152	iter_reg = fw->req1_dma_reg;
				2153	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				2154	dmp_reg = &reg->iobase_q;
				2155	for (cnt = 0; cnt < 7; cnt++)
				2156	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2157
				2158	/* Transmit DMA registers. */
				2159	iter_reg = fw->xmt0_dma_reg;
				2160	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				2161	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				2162
				2163	iter_reg = fw->xmt1_dma_reg;
				2164	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				2165	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				2166
				2167	iter_reg = fw->xmt2_dma_reg;
				2168	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				2169	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				2170
				2171	iter_reg = fw->xmt3_dma_reg;
				2172	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				2173	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				2174
				2175	iter_reg = fw->xmt4_dma_reg;
				2176	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				2177	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				2178
				2179	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				2180
				2181	/* Receive DMA registers. */
				2182	iter_reg = fw->rcvt0_data_dma_reg;
				2183	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				2184	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				2185
				2186	iter_reg = fw->rcvt1_data_dma_reg;
				2187	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				2188	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				2189
				2190	/* RISC registers. */
				2191	iter_reg = fw->risc_gp_reg;
				2192	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				2193	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				2194	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				2195	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				2196	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				2197	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				2198	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				2199	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				2200
				2201	/* Local memory controller registers. */
				2202	iter_reg = fw->lmc_reg;
				2203	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				2204	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				2205	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				2206	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				2207	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				2208	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				2209	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				2210	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				2211
				2212	/* Fibre Protocol Module registers. */
				2213	iter_reg = fw->fpm_hdw_reg;
				2214	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				2215	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				2216	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				2217	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				2218	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				2219	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				2220	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				2221	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				2222	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				2223	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				2224	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				2225	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				2226	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				2227	iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				2228	iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
				2229	qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
				2230
				2231	/* RQ0 Array registers. */
				2232	iter_reg = fw->rq0_array_reg;
				2233	iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
				2234	iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
				2235	iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
				2236	iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
				2237	iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
				2238	iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
				2239	iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
				2240	iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
				2241	iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
				2242	iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
				2243	iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
				2244	iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
				2245	iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
				2246	iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
				2247	iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
				2248	qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
				2249
				2250	/* RQ1 Array registers. */
				2251	iter_reg = fw->rq1_array_reg;
				2252	iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
				2253	iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
				2254	iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
				2255	iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
				2256	iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
				2257	iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
				2258	iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
				2259	iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
				2260	iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
				2261	iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
				2262	iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
				2263	iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
				2264	iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
				2265	iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
				2266	iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
				2267	qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
				2268
				2269	/* RP0 Array registers. */
				2270	iter_reg = fw->rp0_array_reg;
				2271	iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
				2272	iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
				2273	iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
				2274	iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
				2275	iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
				2276	iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
				2277	iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
				2278	iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
				2279	iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
				2280	iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
				2281	iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
				2282	iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
				2283	iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
				2284	iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
				2285	iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
				2286	qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
				2287
				2288	/* RP1 Array registers. */
				2289	iter_reg = fw->rp1_array_reg;
				2290	iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
				2291	iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
				2292	iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
				2293	iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
				2294	iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
				2295	iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
				2296	iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
				2297	iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
				2298	iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
				2299	iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
				2300	iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
				2301	iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
				2302	iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
				2303	iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
				2304	iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
				2305	qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
				2306
				2307	iter_reg = fw->at0_array_reg;
				2308	iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
				2309	iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
				2310	iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
				2311	iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
				2312	iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
				2313	iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
				2314	iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
				2315	qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
				2316
				2317	/* I/O Queue Control registers. */
				2318	qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
				2319
				2320	/* Frame Buffer registers. */
				2321	iter_reg = fw->fb_hdw_reg;
				2322	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				2323	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				2324	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				2325	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				2326	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				2327	iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
				2328	iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
				2329	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				2330	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				2331	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				2332	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				2333	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				2334	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				2335	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				2336	iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
				2337	iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
				2338	iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
				2339	iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
				2340	iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
				2341	iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
				2342	iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
				2343	iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
				2344	iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
				2345	iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
				2346	iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
				2347	iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
				2348	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				2349
				2350	/* Multi queue registers */
				2351	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				2352	&last_chain);
				2353
				2354	rval = qla24xx_soft_reset(ha);
				2355	if (rval != QLA_SUCCESS) {
				2356	ql_log(ql_log_warn, vha, 0xd00e,
				2357	"SOFT RESET FAILED, forcing continuation of dump!!!\n");
				2358	rval = QLA_SUCCESS;
				2359
				2360	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
				2361
				2362	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
				2363	RD_REG_DWORD(&reg->hccr);
				2364
				2365	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
				2366	RD_REG_DWORD(&reg->hccr);
				2367
				2368	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				2369	RD_REG_DWORD(&reg->hccr);
				2370
				2371	for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
				2372	udelay(5);
				2373
				2374	if (!cnt) {
				2375	nxt = fw->code_ram;
Saurav Kashyap	8c0bc70	2012-11-21 02:40:35 -0500	[diff] [blame]	2376	nxt += sizeof(fw->code_ram);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2377	nxt += (ha->fw_memory_size - 0x100000 + 1);
				2378	goto copy_queue;
				2379	} else
				2380	ql_log(ql_log_warn, vha, 0xd010,
				2381	"bigger hammer success?\n");
				2382	}
				2383
				2384	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				2385	&nxt);
				2386	if (rval != QLA_SUCCESS)
				2387	goto qla83xx_fw_dump_failed_0;
				2388
				2389	copy_queue:
				2390	nxt = qla2xxx_copy_queues(ha, nxt);
				2391
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	2392	qla24xx_copy_eft(ha, nxt);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2393
				2394	/* Chain entries -- started with MQ. */
				2395	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				2396	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	2397	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2398	if (last_chain) {
				2399	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				2400	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				2401	}
				2402
				2403	/* Adjust valid length. */
				2404	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				2405
				2406	qla83xx_fw_dump_failed_0:
				2407	qla2xxx_dump_post_process(base_vha, rval);
				2408
				2409	qla83xx_fw_dump_failed:
				2410	if (!hardware_locked)
				2411	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				2412	}
				2413
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2414	/****************************************************************************/
				2415	/* Driver Debug Functions. */
				2416	/****************************************************************************/
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2417
				2418	static inline int
				2419	ql_mask_match(uint32_t level)
				2420	{
				2421	if (ql2xextended_error_logging == 1)
				2422	ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
				2423	return (level & ql2xextended_error_logging) == level;
				2424	}
				2425
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2426	/*
				2427	* This function is for formatting and logging debug information.
				2428	* It is to be used when vha is available. It formats the message
				2429	* and logs it to the messages file.
				2430	* parameters:
				2431	* level: The level of the debug messages to be printed.
				2432	* If ql2xextended_error_logging value is correctly set,
				2433	* this message will appear in the messages file.
				2434	* vha: Pointer to the scsi_qla_host_t.
				2435	* id: This is a unique identifier for the level. It identifies the
				2436	* part of the code from where the message originated.
				2437	* msg: The message to be displayed.
				2438	*/
				2439	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2440	ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2441	{
				2442	va_list va;
				2443	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2444
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2445	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2446	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2447
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2448	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2449
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2450	vaf.fmt = fmt;
				2451	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2452
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2453	if (vha != NULL) {
				2454	const struct pci_dev *pdev = vha->hw->pdev;
				2455	/* <module-name> <pci-name> <msg-id>:<host> Message */
				2456	pr_warn("%s [%s]-%04x:%ld: %pV",
				2457	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
				2458	vha->host_no, &vaf);
				2459	} else {
				2460	pr_warn("%s [%s]-%04x: : %pV",
				2461	QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2462	}
				2463
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2464	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2465
				2466	}
				2467
				2468	/*
				2469	* This function is for formatting and logging debug information.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2470	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2471	* i.e., before host allocation. It formats the message and logs it
				2472	* to the messages file.
				2473	* parameters:
				2474	* level: The level of the debug messages to be printed.
				2475	* If ql2xextended_error_logging value is correctly set,
				2476	* this message will appear in the messages file.
				2477	* pdev: Pointer to the struct pci_dev.
				2478	* id: This is a unique id for the level. It identifies the part
				2479	* of the code from where the message originated.
				2480	* msg: The message to be displayed.
				2481	*/
				2482	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2483	ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2484	const char *fmt, ...)
				2485	{
				2486	va_list va;
				2487	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2488
				2489	if (pdev == NULL)
				2490	return;
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2491	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2492	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2493
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2494	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2495
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2496	vaf.fmt = fmt;
				2497	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2498
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2499	/* <module-name> <dev-name>:<msg-id> Message */
				2500	pr_warn("%s [%s]-%04x: : %pV",
				2501	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2502
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2503	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2504	}
				2505
				2506	/*
				2507	* This function is for formatting and logging log messages.
				2508	* It is to be used when vha is available. It formats the message
				2509	* and logs it to the messages file. All the messages will be logged
				2510	* irrespective of value of ql2xextended_error_logging.
				2511	* parameters:
				2512	* level: The level of the log messages to be printed in the
				2513	* messages file.
				2514	* vha: Pointer to the scsi_qla_host_t
				2515	* id: This is a unique id for the level. It identifies the
				2516	* part of the code from where the message originated.
				2517	* msg: The message to be displayed.
				2518	*/
				2519	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2520	ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2521	{
				2522	va_list va;
				2523	struct va_format vaf;
				2524	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2525
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2526	if (level > ql_errlev)
				2527	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2528
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2529	if (vha != NULL) {
				2530	const struct pci_dev *pdev = vha->hw->pdev;
				2531	/* <module-name> <msg-id>:<host> Message */
				2532	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
				2533	QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
				2534	} else {
				2535	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2536	QL_MSGHDR, "0000:00:00.0", id);
				2537	}
				2538	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2539
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2540	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2541
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2542	vaf.fmt = fmt;
				2543	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2544
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2545	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2546	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2547	pr_crit("%s%pV", pbuf, &vaf);
				2548	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2549	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2550	pr_err("%s%pV", pbuf, &vaf);
				2551	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2552	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2553	pr_warn("%s%pV", pbuf, &vaf);
				2554	break;
				2555	default:
				2556	pr_info("%s%pV", pbuf, &vaf);
				2557	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2558	}
				2559
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2560	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2561	}
				2562
				2563	/*
				2564	* This function is for formatting and logging log messages.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2565	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2566	* i.e., before host allocation. It formats the message and logs
				2567	* it to the messages file. All the messages are logged irrespective
				2568	* of the value of ql2xextended_error_logging.
				2569	* parameters:
				2570	* level: The level of the log messages to be printed in the
				2571	* messages file.
				2572	* pdev: Pointer to the struct pci_dev.
				2573	* id: This is a unique id for the level. It identifies the
				2574	* part of the code from where the message originated.
				2575	* msg: The message to be displayed.
				2576	*/
				2577	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2578	ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2579	const char *fmt, ...)
				2580	{
				2581	va_list va;
				2582	struct va_format vaf;
				2583	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2584
				2585	if (pdev == NULL)
				2586	return;
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2587	if (level > ql_errlev)
				2588	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2589
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2590	/* <module-name> <dev-name>:<msg-id> Message */
				2591	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2592	QL_MSGHDR, dev_name(&(pdev->dev)), id);
				2593	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2594
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2595	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2596
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2597	vaf.fmt = fmt;
				2598	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2599
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2600	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2601	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2602	pr_crit("%s%pV", pbuf, &vaf);
				2603	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2604	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2605	pr_err("%s%pV", pbuf, &vaf);
				2606	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2607	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2608	pr_warn("%s%pV", pbuf, &vaf);
				2609	break;
				2610	default:
				2611	pr_info("%s%pV", pbuf, &vaf);
				2612	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2613	}
				2614
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2615	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2616	}
				2617
				2618	void
				2619	ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
				2620	{
				2621	int i;
				2622	struct qla_hw_data *ha = vha->hw;
				2623	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				2624	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
				2625	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
				2626	uint16_t __iomem *mbx_reg;
				2627
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2628	if (!ql_mask_match(level))
				2629	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2630
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	2631	if (IS_P3P_TYPE(ha))
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2632	mbx_reg = &reg82->mailbox_in[0];
				2633	else if (IS_FWI2_CAPABLE(ha))
				2634	mbx_reg = &reg24->mailbox0;
				2635	else
				2636	mbx_reg = MAILBOX_REG(ha, reg, 0);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2637
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2638	ql_dbg(level, vha, id, "Mailbox registers:\n");
				2639	for (i = 0; i < 6; i++)
				2640	ql_dbg(level, vha, id,
				2641	"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2642	}
				2643
				2644
				2645	void
				2646	ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
				2647	uint8_t *b, uint32_t size)
				2648	{
				2649	uint32_t cnt;
				2650	uint8_t c;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2651
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2652	if (!ql_mask_match(level))
				2653	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2654
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2655	ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
				2656	"9 Ah Bh Ch Dh Eh Fh\n");
				2657	ql_dbg(level, vha, id, "----------------------------------"
				2658	"----------------------------\n");
				2659
				2660	ql_dbg(level, vha, id, " ");
				2661	for (cnt = 0; cnt < size;) {
				2662	c = *b++;
				2663	printk("%02x", (uint32_t) c);
				2664	cnt++;
				2665	if (!(cnt % 16))
				2666	printk("\n");
				2667	else
				2668	printk(" ");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2669	}
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2670	if (cnt % 16)
				2671	ql_dbg(level, vha, id, "\n");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2672	}