Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "i915_drv.h" |
| 29 | #include "intel_drv.h" |
| 30 | |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 31 | struct ddi_buf_trans { |
| 32 | u32 trans1; /* balance leg enable, de-emph level */ |
| 33 | u32 trans2; /* vref sel, vswing */ |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 34 | u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 35 | }; |
| 36 | |
Ville Syrjälä | 97eeb87 | 2017-02-23 19:35:06 +0200 | [diff] [blame] | 37 | static const u8 index_to_dp_signal_levels[] = { |
| 38 | [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, |
| 39 | [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, |
| 40 | [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, |
| 41 | [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, |
| 42 | [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, |
| 43 | [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, |
| 44 | [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, |
| 45 | [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, |
| 46 | [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, |
| 47 | [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, |
| 48 | }; |
| 49 | |
Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 50 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
| 51 | * them for both DP and FDI transports, allowing those ports to |
| 52 | * automatically adapt to HDMI connections as well |
| 53 | */ |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 54 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 55 | { 0x00FFFFFF, 0x0006000E, 0x0 }, |
| 56 | { 0x00D75FFF, 0x0005000A, 0x0 }, |
| 57 | { 0x00C30FFF, 0x00040006, 0x0 }, |
| 58 | { 0x80AAAFFF, 0x000B0000, 0x0 }, |
| 59 | { 0x00FFFFFF, 0x0005000A, 0x0 }, |
| 60 | { 0x00D75FFF, 0x000C0004, 0x0 }, |
| 61 | { 0x80C30FFF, 0x000B0000, 0x0 }, |
| 62 | { 0x00FFFFFF, 0x00040006, 0x0 }, |
| 63 | { 0x80D75FFF, 0x000B0000, 0x0 }, |
Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 64 | }; |
| 65 | |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 66 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 67 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
| 68 | { 0x00D75FFF, 0x000F000A, 0x0 }, |
| 69 | { 0x00C30FFF, 0x00060006, 0x0 }, |
| 70 | { 0x00AAAFFF, 0x001E0000, 0x0 }, |
| 71 | { 0x00FFFFFF, 0x000F000A, 0x0 }, |
| 72 | { 0x00D75FFF, 0x00160004, 0x0 }, |
| 73 | { 0x00C30FFF, 0x001E0000, 0x0 }, |
| 74 | { 0x00FFFFFF, 0x00060006, 0x0 }, |
| 75 | { 0x00D75FFF, 0x001E0000, 0x0 }, |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 76 | }; |
| 77 | |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 78 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
| 79 | /* Idx NT mV d T mV d db */ |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 80 | { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ |
| 81 | { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ |
| 82 | { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ |
| 83 | { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ |
| 84 | { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ |
| 85 | { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ |
| 86 | { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ |
| 87 | { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ |
| 88 | { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ |
| 89 | { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ |
| 90 | { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ |
| 91 | { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ |
Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 92 | }; |
| 93 | |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 94 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 95 | { 0x00FFFFFF, 0x00000012, 0x0 }, |
| 96 | { 0x00EBAFFF, 0x00020011, 0x0 }, |
| 97 | { 0x00C71FFF, 0x0006000F, 0x0 }, |
| 98 | { 0x00AAAFFF, 0x000E000A, 0x0 }, |
| 99 | { 0x00FFFFFF, 0x00020011, 0x0 }, |
| 100 | { 0x00DB6FFF, 0x0005000F, 0x0 }, |
| 101 | { 0x00BEEFFF, 0x000A000C, 0x0 }, |
| 102 | { 0x00FFFFFF, 0x0005000F, 0x0 }, |
| 103 | { 0x00DB6FFF, 0x000A000C, 0x0 }, |
Paulo Zanoni | 300644c | 2013-11-02 21:07:42 -0700 | [diff] [blame] | 104 | }; |
| 105 | |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 106 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 107 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
| 108 | { 0x00D75FFF, 0x000E000A, 0x0 }, |
| 109 | { 0x00BEFFFF, 0x00140006, 0x0 }, |
| 110 | { 0x80B2CFFF, 0x001B0002, 0x0 }, |
| 111 | { 0x00FFFFFF, 0x000E000A, 0x0 }, |
| 112 | { 0x00DB6FFF, 0x00160005, 0x0 }, |
| 113 | { 0x80C71FFF, 0x001A0002, 0x0 }, |
| 114 | { 0x00F7DFFF, 0x00180004, 0x0 }, |
| 115 | { 0x80D75FFF, 0x001B0002, 0x0 }, |
Art Runyan | e58623c | 2013-11-02 21:07:41 -0700 | [diff] [blame] | 116 | }; |
| 117 | |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 118 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 119 | { 0x00FFFFFF, 0x0001000E, 0x0 }, |
| 120 | { 0x00D75FFF, 0x0004000A, 0x0 }, |
| 121 | { 0x00C30FFF, 0x00070006, 0x0 }, |
| 122 | { 0x00AAAFFF, 0x000C0000, 0x0 }, |
| 123 | { 0x00FFFFFF, 0x0004000A, 0x0 }, |
| 124 | { 0x00D75FFF, 0x00090004, 0x0 }, |
| 125 | { 0x00C30FFF, 0x000C0000, 0x0 }, |
| 126 | { 0x00FFFFFF, 0x00070006, 0x0 }, |
| 127 | { 0x00D75FFF, 0x000C0000, 0x0 }, |
Art Runyan | e58623c | 2013-11-02 21:07:41 -0700 | [diff] [blame] | 128 | }; |
| 129 | |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 130 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
| 131 | /* Idx NT mV d T mV df db */ |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 132 | { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ |
| 133 | { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ |
| 134 | { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ |
| 135 | { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ |
| 136 | { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ |
| 137 | { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ |
| 138 | { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ |
| 139 | { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ |
| 140 | { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ |
| 141 | { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ |
Damien Lespiau | a26aa8b | 2014-08-01 11:07:55 +0100 | [diff] [blame] | 142 | }; |
| 143 | |
Rodrigo Vivi | 5f8b253 | 2015-08-24 16:48:44 -0700 | [diff] [blame] | 144 | /* Skylake H and S */ |
Damien Lespiau | 7f88e3a | 2013-12-03 13:56:25 +0000 | [diff] [blame] | 145 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 146 | { 0x00002016, 0x000000A0, 0x0 }, |
| 147 | { 0x00005012, 0x0000009B, 0x0 }, |
| 148 | { 0x00007011, 0x00000088, 0x0 }, |
Rodrigo Vivi | d7097cf | 2016-01-05 11:18:55 -0800 | [diff] [blame] | 149 | { 0x80009010, 0x000000C0, 0x1 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 150 | { 0x00002016, 0x0000009B, 0x0 }, |
| 151 | { 0x00005012, 0x00000088, 0x0 }, |
Rodrigo Vivi | d7097cf | 2016-01-05 11:18:55 -0800 | [diff] [blame] | 152 | { 0x80007011, 0x000000C0, 0x1 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 153 | { 0x00002016, 0x000000DF, 0x0 }, |
Rodrigo Vivi | d7097cf | 2016-01-05 11:18:55 -0800 | [diff] [blame] | 154 | { 0x80005012, 0x000000C0, 0x1 }, |
Damien Lespiau | 7f88e3a | 2013-12-03 13:56:25 +0000 | [diff] [blame] | 155 | }; |
| 156 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 157 | /* Skylake U */ |
| 158 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { |
Rodrigo Vivi | 5f8b253 | 2015-08-24 16:48:44 -0700 | [diff] [blame] | 159 | { 0x0000201B, 0x000000A2, 0x0 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 160 | { 0x00005012, 0x00000088, 0x0 }, |
Ville Syrjälä | 5ac9056 | 2016-08-02 15:21:57 +0300 | [diff] [blame] | 161 | { 0x80007011, 0x000000CD, 0x1 }, |
Rodrigo Vivi | d7097cf | 2016-01-05 11:18:55 -0800 | [diff] [blame] | 162 | { 0x80009010, 0x000000C0, 0x1 }, |
Rodrigo Vivi | 5f8b253 | 2015-08-24 16:48:44 -0700 | [diff] [blame] | 163 | { 0x0000201B, 0x0000009D, 0x0 }, |
Rodrigo Vivi | d7097cf | 2016-01-05 11:18:55 -0800 | [diff] [blame] | 164 | { 0x80005012, 0x000000C0, 0x1 }, |
| 165 | { 0x80007011, 0x000000C0, 0x1 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 166 | { 0x00002016, 0x00000088, 0x0 }, |
Rodrigo Vivi | d7097cf | 2016-01-05 11:18:55 -0800 | [diff] [blame] | 167 | { 0x80005012, 0x000000C0, 0x1 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 168 | }; |
| 169 | |
Rodrigo Vivi | 5f8b253 | 2015-08-24 16:48:44 -0700 | [diff] [blame] | 170 | /* Skylake Y */ |
| 171 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 172 | { 0x00000018, 0x000000A2, 0x0 }, |
| 173 | { 0x00005012, 0x00000088, 0x0 }, |
Ville Syrjälä | 5ac9056 | 2016-08-02 15:21:57 +0300 | [diff] [blame] | 174 | { 0x80007011, 0x000000CD, 0x3 }, |
Rodrigo Vivi | d7097cf | 2016-01-05 11:18:55 -0800 | [diff] [blame] | 175 | { 0x80009010, 0x000000C0, 0x3 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 176 | { 0x00000018, 0x0000009D, 0x0 }, |
Rodrigo Vivi | d7097cf | 2016-01-05 11:18:55 -0800 | [diff] [blame] | 177 | { 0x80005012, 0x000000C0, 0x3 }, |
| 178 | { 0x80007011, 0x000000C0, 0x3 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 179 | { 0x00000018, 0x00000088, 0x0 }, |
Rodrigo Vivi | d7097cf | 2016-01-05 11:18:55 -0800 | [diff] [blame] | 180 | { 0x80005012, 0x000000C0, 0x3 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 181 | }; |
| 182 | |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 183 | /* Kabylake H and S */ |
| 184 | static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { |
| 185 | { 0x00002016, 0x000000A0, 0x0 }, |
| 186 | { 0x00005012, 0x0000009B, 0x0 }, |
| 187 | { 0x00007011, 0x00000088, 0x0 }, |
| 188 | { 0x80009010, 0x000000C0, 0x1 }, |
| 189 | { 0x00002016, 0x0000009B, 0x0 }, |
| 190 | { 0x00005012, 0x00000088, 0x0 }, |
| 191 | { 0x80007011, 0x000000C0, 0x1 }, |
| 192 | { 0x00002016, 0x00000097, 0x0 }, |
| 193 | { 0x80005012, 0x000000C0, 0x1 }, |
| 194 | }; |
| 195 | |
| 196 | /* Kabylake U */ |
| 197 | static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { |
| 198 | { 0x0000201B, 0x000000A1, 0x0 }, |
| 199 | { 0x00005012, 0x00000088, 0x0 }, |
| 200 | { 0x80007011, 0x000000CD, 0x3 }, |
| 201 | { 0x80009010, 0x000000C0, 0x3 }, |
| 202 | { 0x0000201B, 0x0000009D, 0x0 }, |
| 203 | { 0x80005012, 0x000000C0, 0x3 }, |
| 204 | { 0x80007011, 0x000000C0, 0x3 }, |
| 205 | { 0x00002016, 0x0000004F, 0x0 }, |
| 206 | { 0x80005012, 0x000000C0, 0x3 }, |
| 207 | }; |
| 208 | |
| 209 | /* Kabylake Y */ |
| 210 | static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { |
| 211 | { 0x00001017, 0x000000A1, 0x0 }, |
| 212 | { 0x00005012, 0x00000088, 0x0 }, |
| 213 | { 0x80007011, 0x000000CD, 0x3 }, |
| 214 | { 0x8000800F, 0x000000C0, 0x3 }, |
| 215 | { 0x00001017, 0x0000009D, 0x0 }, |
| 216 | { 0x80005012, 0x000000C0, 0x3 }, |
| 217 | { 0x80007011, 0x000000C0, 0x3 }, |
| 218 | { 0x00001017, 0x0000004C, 0x0 }, |
| 219 | { 0x80005012, 0x000000C0, 0x3 }, |
| 220 | }; |
| 221 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 222 | /* |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 223 | * Skylake/Kabylake H and S |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 224 | * eDP 1.4 low vswing translation parameters |
| 225 | */ |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 226 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 227 | { 0x00000018, 0x000000A8, 0x0 }, |
| 228 | { 0x00004013, 0x000000A9, 0x0 }, |
| 229 | { 0x00007011, 0x000000A2, 0x0 }, |
| 230 | { 0x00009010, 0x0000009C, 0x0 }, |
| 231 | { 0x00000018, 0x000000A9, 0x0 }, |
| 232 | { 0x00006013, 0x000000A2, 0x0 }, |
| 233 | { 0x00007011, 0x000000A6, 0x0 }, |
| 234 | { 0x00000018, 0x000000AB, 0x0 }, |
| 235 | { 0x00007013, 0x0000009F, 0x0 }, |
| 236 | { 0x00000018, 0x000000DF, 0x0 }, |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 237 | }; |
| 238 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 239 | /* |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 240 | * Skylake/Kabylake U |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 241 | * eDP 1.4 low vswing translation parameters |
| 242 | */ |
| 243 | static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { |
| 244 | { 0x00000018, 0x000000A8, 0x0 }, |
| 245 | { 0x00004013, 0x000000A9, 0x0 }, |
| 246 | { 0x00007011, 0x000000A2, 0x0 }, |
| 247 | { 0x00009010, 0x0000009C, 0x0 }, |
| 248 | { 0x00000018, 0x000000A9, 0x0 }, |
| 249 | { 0x00006013, 0x000000A2, 0x0 }, |
| 250 | { 0x00007011, 0x000000A6, 0x0 }, |
| 251 | { 0x00002016, 0x000000AB, 0x0 }, |
| 252 | { 0x00005013, 0x0000009F, 0x0 }, |
| 253 | { 0x00000018, 0x000000DF, 0x0 }, |
| 254 | }; |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 255 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 256 | /* |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 257 | * Skylake/Kabylake Y |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 258 | * eDP 1.4 low vswing translation parameters |
| 259 | */ |
Rodrigo Vivi | 5f8b253 | 2015-08-24 16:48:44 -0700 | [diff] [blame] | 260 | static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 261 | { 0x00000018, 0x000000A8, 0x0 }, |
| 262 | { 0x00004013, 0x000000AB, 0x0 }, |
| 263 | { 0x00007011, 0x000000A4, 0x0 }, |
| 264 | { 0x00009010, 0x000000DF, 0x0 }, |
| 265 | { 0x00000018, 0x000000AA, 0x0 }, |
| 266 | { 0x00006013, 0x000000A4, 0x0 }, |
| 267 | { 0x00007011, 0x0000009D, 0x0 }, |
| 268 | { 0x00000018, 0x000000A0, 0x0 }, |
| 269 | { 0x00006012, 0x000000DF, 0x0 }, |
| 270 | { 0x00000018, 0x0000008A, 0x0 }, |
| 271 | }; |
| 272 | |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 273 | /* Skylake/Kabylake U, H and S */ |
Damien Lespiau | 7f88e3a | 2013-12-03 13:56:25 +0000 | [diff] [blame] | 274 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 275 | { 0x00000018, 0x000000AC, 0x0 }, |
| 276 | { 0x00005012, 0x0000009D, 0x0 }, |
| 277 | { 0x00007011, 0x00000088, 0x0 }, |
| 278 | { 0x00000018, 0x000000A1, 0x0 }, |
| 279 | { 0x00000018, 0x00000098, 0x0 }, |
| 280 | { 0x00004013, 0x00000088, 0x0 }, |
Rodrigo Vivi | 2e78416 | 2016-01-05 11:11:27 -0800 | [diff] [blame] | 281 | { 0x80006012, 0x000000CD, 0x1 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 282 | { 0x00000018, 0x000000DF, 0x0 }, |
Rodrigo Vivi | 2e78416 | 2016-01-05 11:11:27 -0800 | [diff] [blame] | 283 | { 0x80003015, 0x000000CD, 0x1 }, /* Default */ |
| 284 | { 0x80003015, 0x000000C0, 0x1 }, |
| 285 | { 0x80000018, 0x000000C0, 0x1 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 286 | }; |
| 287 | |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 288 | /* Skylake/Kabylake Y */ |
Rodrigo Vivi | 5f8b253 | 2015-08-24 16:48:44 -0700 | [diff] [blame] | 289 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 290 | { 0x00000018, 0x000000A1, 0x0 }, |
| 291 | { 0x00005012, 0x000000DF, 0x0 }, |
Rodrigo Vivi | 2e78416 | 2016-01-05 11:11:27 -0800 | [diff] [blame] | 292 | { 0x80007011, 0x000000CB, 0x3 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 293 | { 0x00000018, 0x000000A4, 0x0 }, |
| 294 | { 0x00000018, 0x0000009D, 0x0 }, |
| 295 | { 0x00004013, 0x00000080, 0x0 }, |
Rodrigo Vivi | 2e78416 | 2016-01-05 11:11:27 -0800 | [diff] [blame] | 296 | { 0x80006013, 0x000000C0, 0x3 }, |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 297 | { 0x00000018, 0x0000008A, 0x0 }, |
Rodrigo Vivi | 2e78416 | 2016-01-05 11:11:27 -0800 | [diff] [blame] | 298 | { 0x80003015, 0x000000C0, 0x3 }, /* Default */ |
| 299 | { 0x80003015, 0x000000C0, 0x3 }, |
| 300 | { 0x80000018, 0x000000C0, 0x3 }, |
Damien Lespiau | 7f88e3a | 2013-12-03 13:56:25 +0000 | [diff] [blame] | 301 | }; |
| 302 | |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 303 | struct bxt_ddi_buf_trans { |
| 304 | u32 margin; /* swing value */ |
| 305 | u32 scale; /* scale value */ |
| 306 | u32 enable; /* scale enable */ |
| 307 | u32 deemphasis; |
| 308 | bool default_index; /* true if the entry represents default value */ |
| 309 | }; |
| 310 | |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 311 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { |
| 312 | /* Idx NT mV diff db */ |
Imre Deak | fe4c63c | 2015-06-04 18:01:35 +0300 | [diff] [blame] | 313 | { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ |
| 314 | { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ |
| 315 | { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ |
| 316 | { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ |
| 317 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ |
| 318 | { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ |
| 319 | { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ |
| 320 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ |
| 321 | { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 322 | { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 323 | }; |
| 324 | |
Sonika Jindal | d9d7000 | 2015-09-24 10:24:56 +0530 | [diff] [blame] | 325 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { |
| 326 | /* Idx NT mV diff db */ |
| 327 | { 26, 0, 0, 128, false }, /* 0: 200 0 */ |
| 328 | { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ |
| 329 | { 48, 0, 0, 96, false }, /* 2: 200 4 */ |
| 330 | { 54, 0, 0, 69, false }, /* 3: 200 6 */ |
| 331 | { 32, 0, 0, 128, false }, /* 4: 250 0 */ |
| 332 | { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ |
| 333 | { 54, 0, 0, 85, false }, /* 6: 250 4 */ |
| 334 | { 43, 0, 0, 128, false }, /* 7: 300 0 */ |
| 335 | { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ |
| 336 | { 48, 0, 0, 128, false }, /* 9: 300 0 */ |
| 337 | }; |
| 338 | |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 339 | /* BSpec has 2 recommended values - entries 0 and 8. |
| 340 | * Using the entry with higher vswing. |
| 341 | */ |
| 342 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { |
| 343 | /* Idx NT mV diff db */ |
Imre Deak | fe4c63c | 2015-06-04 18:01:35 +0300 | [diff] [blame] | 344 | { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ |
| 345 | { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ |
| 346 | { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ |
| 347 | { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ |
| 348 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ |
| 349 | { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ |
| 350 | { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ |
| 351 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ |
| 352 | { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 353 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ |
| 354 | }; |
| 355 | |
Rodrigo Vivi | 83fb7ab | 2017-06-09 15:26:07 -0700 | [diff] [blame] | 356 | struct cnl_ddi_buf_trans { |
| 357 | u32 dw2_swing_sel; |
| 358 | u32 dw7_n_scalar; |
| 359 | u32 dw4_cursor_coeff; |
| 360 | u32 dw4_post_cursor_2; |
| 361 | u32 dw4_post_cursor_1; |
| 362 | }; |
| 363 | |
| 364 | /* Voltage Swing Programming for VccIO 0.85V for DP */ |
| 365 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { |
| 366 | /* NT mV Trans mV db */ |
| 367 | { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ |
| 368 | { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ |
| 369 | { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ |
| 370 | { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ |
| 371 | { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ |
| 372 | { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ |
| 373 | { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ |
| 374 | { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ |
| 375 | { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ |
| 376 | { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ |
| 377 | }; |
| 378 | |
| 379 | /* Voltage Swing Programming for VccIO 0.85V for HDMI */ |
| 380 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { |
| 381 | /* NT mV Trans mV db */ |
| 382 | { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ |
| 383 | { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ |
| 384 | { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ |
| 385 | { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ |
| 386 | { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ |
| 387 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ |
| 388 | { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ |
| 389 | }; |
| 390 | |
| 391 | /* Voltage Swing Programming for VccIO 0.85V for eDP */ |
| 392 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { |
| 393 | /* NT mV Trans mV db */ |
| 394 | { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ |
| 395 | { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ |
| 396 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ |
| 397 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ |
| 398 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ |
| 399 | { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ |
| 400 | { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ |
| 401 | { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ |
| 402 | { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ |
| 403 | }; |
| 404 | |
| 405 | /* Voltage Swing Programming for VccIO 0.95V for DP */ |
| 406 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { |
| 407 | /* NT mV Trans mV db */ |
| 408 | { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ |
| 409 | { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ |
| 410 | { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ |
| 411 | { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ |
| 412 | { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ |
| 413 | { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ |
| 414 | { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ |
| 415 | { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ |
| 416 | { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ |
| 417 | { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ |
| 418 | }; |
| 419 | |
| 420 | /* Voltage Swing Programming for VccIO 0.95V for HDMI */ |
| 421 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { |
| 422 | /* NT mV Trans mV db */ |
| 423 | { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ |
| 424 | { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ |
| 425 | { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ |
| 426 | { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ |
| 427 | { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ |
| 428 | { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ |
| 429 | { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ |
| 430 | { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ |
| 431 | { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ |
| 432 | { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ |
| 433 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ |
| 434 | }; |
| 435 | |
| 436 | /* Voltage Swing Programming for VccIO 0.95V for eDP */ |
| 437 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { |
| 438 | /* NT mV Trans mV db */ |
| 439 | { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ |
| 440 | { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ |
| 441 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ |
| 442 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ |
| 443 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ |
| 444 | { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ |
| 445 | { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ |
| 446 | { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ |
| 447 | { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ |
| 448 | { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ |
| 449 | }; |
| 450 | |
| 451 | /* Voltage Swing Programming for VccIO 1.05V for DP */ |
| 452 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { |
| 453 | /* NT mV Trans mV db */ |
| 454 | { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ |
| 455 | { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ |
| 456 | { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ |
| 457 | { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ |
| 458 | { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ |
| 459 | { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ |
| 460 | { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ |
| 461 | { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ |
| 462 | { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ |
| 463 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ |
| 464 | }; |
| 465 | |
| 466 | /* Voltage Swing Programming for VccIO 1.05V for HDMI */ |
| 467 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { |
| 468 | /* NT mV Trans mV db */ |
| 469 | { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ |
| 470 | { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ |
| 471 | { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ |
| 472 | { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ |
| 473 | { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ |
| 474 | { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ |
| 475 | { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ |
| 476 | { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ |
| 477 | { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ |
| 478 | { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ |
| 479 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ |
| 480 | }; |
| 481 | |
| 482 | /* Voltage Swing Programming for VccIO 1.05V for eDP */ |
| 483 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { |
| 484 | /* NT mV Trans mV db */ |
| 485 | { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ |
| 486 | { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ |
| 487 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ |
| 488 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ |
| 489 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ |
| 490 | { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ |
| 491 | { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ |
| 492 | { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ |
| 493 | { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ |
| 494 | }; |
| 495 | |
Ville Syrjälä | 5a5d24d | 2016-07-12 15:59:35 +0300 | [diff] [blame] | 496 | enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder) |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 497 | { |
Ville Syrjälä | 5a5d24d | 2016-07-12 15:59:35 +0300 | [diff] [blame] | 498 | switch (encoder->type) { |
Jani Nikula | 8cd21b7 | 2015-09-29 10:24:26 +0300 | [diff] [blame] | 499 | case INTEL_OUTPUT_DP_MST: |
Ville Syrjälä | 5a5d24d | 2016-07-12 15:59:35 +0300 | [diff] [blame] | 500 | return enc_to_mst(&encoder->base)->primary->port; |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 501 | case INTEL_OUTPUT_DP: |
Jani Nikula | 8cd21b7 | 2015-09-29 10:24:26 +0300 | [diff] [blame] | 502 | case INTEL_OUTPUT_EDP: |
| 503 | case INTEL_OUTPUT_HDMI: |
| 504 | case INTEL_OUTPUT_UNKNOWN: |
Ville Syrjälä | 5a5d24d | 2016-07-12 15:59:35 +0300 | [diff] [blame] | 505 | return enc_to_dig_port(&encoder->base)->port; |
Jani Nikula | 8cd21b7 | 2015-09-29 10:24:26 +0300 | [diff] [blame] | 506 | case INTEL_OUTPUT_ANALOG: |
Ville Syrjälä | 5a5d24d | 2016-07-12 15:59:35 +0300 | [diff] [blame] | 507 | return PORT_E; |
| 508 | default: |
| 509 | MISSING_CASE(encoder->type); |
| 510 | return PORT_A; |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 511 | } |
| 512 | } |
| 513 | |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 514 | static const struct ddi_buf_trans * |
Ville Syrjälä | a930acd | 2016-07-12 15:59:36 +0300 | [diff] [blame] | 515 | bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
| 516 | { |
| 517 | if (dev_priv->vbt.edp.low_vswing) { |
| 518 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
| 519 | return bdw_ddi_translations_edp; |
| 520 | } else { |
| 521 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
| 522 | return bdw_ddi_translations_dp; |
| 523 | } |
| 524 | } |
| 525 | |
| 526 | static const struct ddi_buf_trans * |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 527 | skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 528 | { |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 529 | if (IS_SKL_ULX(dev_priv)) { |
Rodrigo Vivi | 5f8b253 | 2015-08-24 16:48:44 -0700 | [diff] [blame] | 530 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 531 | return skl_y_ddi_translations_dp; |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 532 | } else if (IS_SKL_ULT(dev_priv)) { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 533 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 534 | return skl_u_ddi_translations_dp; |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 535 | } else { |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 536 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 537 | return skl_ddi_translations_dp; |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 538 | } |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 539 | } |
| 540 | |
| 541 | static const struct ddi_buf_trans * |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 542 | kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
| 543 | { |
| 544 | if (IS_KBL_ULX(dev_priv)) { |
| 545 | *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); |
| 546 | return kbl_y_ddi_translations_dp; |
Rodrigo Vivi | da411a4 | 2017-06-09 15:02:50 -0700 | [diff] [blame] | 547 | } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 548 | *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); |
| 549 | return kbl_u_ddi_translations_dp; |
| 550 | } else { |
| 551 | *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); |
| 552 | return kbl_ddi_translations_dp; |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | static const struct ddi_buf_trans * |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 557 | skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 558 | { |
Jani Nikula | 06411f0 | 2016-03-24 17:50:21 +0200 | [diff] [blame] | 559 | if (dev_priv->vbt.edp.low_vswing) { |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 560 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 561 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
| 562 | return skl_y_ddi_translations_edp; |
Rodrigo Vivi | da411a4 | 2017-06-09 15:02:50 -0700 | [diff] [blame] | 563 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || |
| 564 | IS_CFL_ULT(dev_priv)) { |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 565 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
| 566 | return skl_u_ddi_translations_edp; |
| 567 | } else { |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 568 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
| 569 | return skl_ddi_translations_edp; |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 570 | } |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 571 | } |
Ville Syrjälä | cd1101c | 2015-12-08 19:59:40 +0200 | [diff] [blame] | 572 | |
Rodrigo Vivi | da411a4 | 2017-06-09 15:02:50 -0700 | [diff] [blame] | 573 | if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 574 | return kbl_get_buf_trans_dp(dev_priv, n_entries); |
| 575 | else |
| 576 | return skl_get_buf_trans_dp(dev_priv, n_entries); |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 577 | } |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 578 | |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 579 | static const struct ddi_buf_trans * |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 580 | skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 581 | { |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 582 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
Ville Syrjälä | acee299 | 2015-12-08 19:59:39 +0200 | [diff] [blame] | 583 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
| 584 | return skl_y_ddi_translations_hdmi; |
| 585 | } else { |
| 586 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
| 587 | return skl_ddi_translations_hdmi; |
| 588 | } |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 589 | } |
| 590 | |
Ville Syrjälä | 8d8bb85 | 2016-07-12 15:59:30 +0300 | [diff] [blame] | 591 | static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) |
| 592 | { |
| 593 | int n_hdmi_entries; |
| 594 | int hdmi_level; |
| 595 | int hdmi_default_entry; |
| 596 | |
| 597 | hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
| 598 | |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 599 | if (IS_GEN9_LP(dev_priv)) |
Ville Syrjälä | 8d8bb85 | 2016-07-12 15:59:30 +0300 | [diff] [blame] | 600 | return hdmi_level; |
| 601 | |
Rodrigo Vivi | b976dc5 | 2017-01-23 10:32:37 -0800 | [diff] [blame] | 602 | if (IS_GEN9_BC(dev_priv)) { |
Ville Syrjälä | 8d8bb85 | 2016-07-12 15:59:30 +0300 | [diff] [blame] | 603 | skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); |
| 604 | hdmi_default_entry = 8; |
| 605 | } else if (IS_BROADWELL(dev_priv)) { |
| 606 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
| 607 | hdmi_default_entry = 7; |
| 608 | } else if (IS_HASWELL(dev_priv)) { |
| 609 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); |
| 610 | hdmi_default_entry = 6; |
| 611 | } else { |
| 612 | WARN(1, "ddi translation table missing\n"); |
| 613 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
| 614 | hdmi_default_entry = 7; |
| 615 | } |
| 616 | |
| 617 | /* Choose a good default if VBT is badly populated */ |
| 618 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || |
| 619 | hdmi_level >= n_hdmi_entries) |
| 620 | hdmi_level = hdmi_default_entry; |
| 621 | |
| 622 | return hdmi_level; |
| 623 | } |
| 624 | |
Ville Syrjälä | 7d1c42e | 2017-02-23 19:35:05 +0200 | [diff] [blame] | 625 | static const struct ddi_buf_trans * |
| 626 | intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, |
| 627 | int *n_entries) |
| 628 | { |
Rodrigo Vivi | da411a4 | 2017-06-09 15:02:50 -0700 | [diff] [blame] | 629 | if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { |
Ville Syrjälä | 7d1c42e | 2017-02-23 19:35:05 +0200 | [diff] [blame] | 630 | return kbl_get_buf_trans_dp(dev_priv, n_entries); |
| 631 | } else if (IS_SKYLAKE(dev_priv)) { |
| 632 | return skl_get_buf_trans_dp(dev_priv, n_entries); |
| 633 | } else if (IS_BROADWELL(dev_priv)) { |
| 634 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
| 635 | return bdw_ddi_translations_dp; |
| 636 | } else if (IS_HASWELL(dev_priv)) { |
| 637 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
| 638 | return hsw_ddi_translations_dp; |
| 639 | } |
| 640 | |
| 641 | *n_entries = 0; |
| 642 | return NULL; |
| 643 | } |
| 644 | |
| 645 | static const struct ddi_buf_trans * |
| 646 | intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, |
| 647 | int *n_entries) |
| 648 | { |
Rodrigo Vivi | da411a4 | 2017-06-09 15:02:50 -0700 | [diff] [blame] | 649 | if (IS_GEN9_BC(dev_priv)) { |
Ville Syrjälä | 7d1c42e | 2017-02-23 19:35:05 +0200 | [diff] [blame] | 650 | return skl_get_buf_trans_edp(dev_priv, n_entries); |
| 651 | } else if (IS_BROADWELL(dev_priv)) { |
| 652 | return bdw_get_buf_trans_edp(dev_priv, n_entries); |
| 653 | } else if (IS_HASWELL(dev_priv)) { |
| 654 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
| 655 | return hsw_ddi_translations_dp; |
| 656 | } |
| 657 | |
| 658 | *n_entries = 0; |
| 659 | return NULL; |
| 660 | } |
| 661 | |
| 662 | static const struct ddi_buf_trans * |
| 663 | intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, |
| 664 | int *n_entries) |
| 665 | { |
| 666 | if (IS_BROADWELL(dev_priv)) { |
| 667 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); |
| 668 | return hsw_ddi_translations_fdi; |
| 669 | } else if (IS_HASWELL(dev_priv)) { |
| 670 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); |
| 671 | return hsw_ddi_translations_fdi; |
| 672 | } |
| 673 | |
| 674 | *n_entries = 0; |
| 675 | return NULL; |
| 676 | } |
| 677 | |
Art Runyan | e58623c | 2013-11-02 21:07:41 -0700 | [diff] [blame] | 678 | /* |
| 679 | * Starting with Haswell, DDI port buffers must be programmed with correct |
Ville Syrjälä | 32bdc40 | 2016-07-12 15:59:33 +0300 | [diff] [blame] | 680 | * values in advance. This function programs the correct values for |
| 681 | * DP/eDP/FDI use cases. |
Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 682 | */ |
Paulo Zanoni | d7c530b | 2017-03-30 17:57:52 -0300 | [diff] [blame] | 683 | static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder) |
Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 684 | { |
Ville Syrjälä | 6a7e4f9 | 2015-12-08 19:59:44 +0200 | [diff] [blame] | 685 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Antti Koskipaa | 75067dd | 2015-07-10 14:10:55 +0300 | [diff] [blame] | 686 | u32 iboost_bit = 0; |
Ville Syrjälä | 7d1c42e | 2017-02-23 19:35:05 +0200 | [diff] [blame] | 687 | int i, n_entries; |
Ville Syrjälä | 32bdc40 | 2016-07-12 15:59:33 +0300 | [diff] [blame] | 688 | enum port port = intel_ddi_get_encoder_port(encoder); |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 689 | const struct ddi_buf_trans *ddi_translations; |
Art Runyan | e58623c | 2013-11-02 21:07:41 -0700 | [diff] [blame] | 690 | |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 691 | if (IS_GEN9_LP(dev_priv)) |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 692 | return; |
Ville Syrjälä | 6a7e4f9 | 2015-12-08 19:59:44 +0200 | [diff] [blame] | 693 | |
Ville Syrjälä | 7d1c42e | 2017-02-23 19:35:05 +0200 | [diff] [blame] | 694 | switch (encoder->type) { |
| 695 | case INTEL_OUTPUT_EDP: |
| 696 | ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, |
| 697 | &n_entries); |
| 698 | break; |
| 699 | case INTEL_OUTPUT_DP: |
| 700 | ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, |
| 701 | &n_entries); |
| 702 | break; |
| 703 | case INTEL_OUTPUT_ANALOG: |
| 704 | ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, |
| 705 | &n_entries); |
| 706 | break; |
| 707 | default: |
| 708 | MISSING_CASE(encoder->type); |
| 709 | return; |
Art Runyan | e58623c | 2013-11-02 21:07:41 -0700 | [diff] [blame] | 710 | } |
| 711 | |
Rodrigo Vivi | b976dc5 | 2017-01-23 10:32:37 -0800 | [diff] [blame] | 712 | if (IS_GEN9_BC(dev_priv)) { |
Rodrigo Vivi | 0a91877 | 2016-09-30 11:05:56 -0700 | [diff] [blame] | 713 | /* If we're boosting the current, set bit 31 of trans1 */ |
| 714 | if (dev_priv->vbt.ddi_port_info[port].dp_boost_level) |
| 715 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; |
| 716 | |
| 717 | if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && |
| 718 | port != PORT_A && port != PORT_E && |
Ville Syrjälä | 7d1c42e | 2017-02-23 19:35:05 +0200 | [diff] [blame] | 719 | n_entries > 9)) |
| 720 | n_entries = 9; |
Rodrigo Vivi | 0a91877 | 2016-09-30 11:05:56 -0700 | [diff] [blame] | 721 | } |
| 722 | |
Ville Syrjälä | 7d1c42e | 2017-02-23 19:35:05 +0200 | [diff] [blame] | 723 | for (i = 0; i < n_entries; i++) { |
Ville Syrjälä | 9712e68 | 2015-09-18 20:03:22 +0300 | [diff] [blame] | 724 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), |
| 725 | ddi_translations[i].trans1 | iboost_bit); |
| 726 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), |
| 727 | ddi_translations[i].trans2); |
Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 728 | } |
Ville Syrjälä | 32bdc40 | 2016-07-12 15:59:33 +0300 | [diff] [blame] | 729 | } |
Damien Lespiau | ce4dd49 | 2014-08-01 11:07:54 +0100 | [diff] [blame] | 730 | |
Ville Syrjälä | 32bdc40 | 2016-07-12 15:59:33 +0300 | [diff] [blame] | 731 | /* |
| 732 | * Starting with Haswell, DDI port buffers must be programmed with correct |
| 733 | * values in advance. This function programs the correct values for |
| 734 | * HDMI/DVI use cases. |
| 735 | */ |
| 736 | static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder) |
| 737 | { |
| 738 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 739 | u32 iboost_bit = 0; |
| 740 | int n_hdmi_entries, hdmi_level; |
| 741 | enum port port = intel_ddi_get_encoder_port(encoder); |
| 742 | const struct ddi_buf_trans *ddi_translations_hdmi; |
| 743 | |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 744 | if (IS_GEN9_LP(dev_priv)) |
Damien Lespiau | ce3b7e9 | 2014-08-04 15:04:43 +0100 | [diff] [blame] | 745 | return; |
| 746 | |
Ville Syrjälä | 32bdc40 | 2016-07-12 15:59:33 +0300 | [diff] [blame] | 747 | hdmi_level = intel_ddi_hdmi_level(dev_priv, port); |
| 748 | |
Rodrigo Vivi | b976dc5 | 2017-01-23 10:32:37 -0800 | [diff] [blame] | 749 | if (IS_GEN9_BC(dev_priv)) { |
Ville Syrjälä | 32bdc40 | 2016-07-12 15:59:33 +0300 | [diff] [blame] | 750 | ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); |
Ville Syrjälä | 1edaaa2 | 2016-07-12 15:59:34 +0300 | [diff] [blame] | 751 | |
Ville Syrjälä | 32bdc40 | 2016-07-12 15:59:33 +0300 | [diff] [blame] | 752 | /* If we're boosting the current, set bit 31 of trans1 */ |
Ville Syrjälä | 1edaaa2 | 2016-07-12 15:59:34 +0300 | [diff] [blame] | 753 | if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) |
Ville Syrjälä | 32bdc40 | 2016-07-12 15:59:33 +0300 | [diff] [blame] | 754 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; |
| 755 | } else if (IS_BROADWELL(dev_priv)) { |
| 756 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
| 757 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
| 758 | } else if (IS_HASWELL(dev_priv)) { |
| 759 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
| 760 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); |
| 761 | } else { |
| 762 | WARN(1, "ddi translation table missing\n"); |
| 763 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
| 764 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
| 765 | } |
| 766 | |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 767 | /* Entry 9 is for HDMI: */ |
Ville Syrjälä | ed9c77d | 2016-07-12 15:59:32 +0300 | [diff] [blame] | 768 | I915_WRITE(DDI_BUF_TRANS_LO(port, 9), |
Ville Syrjälä | 9712e68 | 2015-09-18 20:03:22 +0300 | [diff] [blame] | 769 | ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); |
Ville Syrjälä | ed9c77d | 2016-07-12 15:59:32 +0300 | [diff] [blame] | 770 | I915_WRITE(DDI_BUF_TRANS_HI(port, 9), |
Ville Syrjälä | 9712e68 | 2015-09-18 20:03:22 +0300 | [diff] [blame] | 771 | ddi_translations_hdmi[hdmi_level].trans2); |
Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 772 | } |
| 773 | |
Paulo Zanoni | 248138b | 2012-11-29 11:29:31 -0200 | [diff] [blame] | 774 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
| 775 | enum port port) |
| 776 | { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 777 | i915_reg_t reg = DDI_BUF_CTL(port); |
Paulo Zanoni | 248138b | 2012-11-29 11:29:31 -0200 | [diff] [blame] | 778 | int i; |
| 779 | |
Vandana Kannan | 3449ca8 | 2015-03-27 14:19:09 +0200 | [diff] [blame] | 780 | for (i = 0; i < 16; i++) { |
Paulo Zanoni | 248138b | 2012-11-29 11:29:31 -0200 | [diff] [blame] | 781 | udelay(1); |
| 782 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) |
| 783 | return; |
| 784 | } |
| 785 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); |
| 786 | } |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 787 | |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 788 | static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll) |
| 789 | { |
| 790 | switch (pll->id) { |
| 791 | case DPLL_ID_WRPLL1: |
| 792 | return PORT_CLK_SEL_WRPLL1; |
| 793 | case DPLL_ID_WRPLL2: |
| 794 | return PORT_CLK_SEL_WRPLL2; |
| 795 | case DPLL_ID_SPLL: |
| 796 | return PORT_CLK_SEL_SPLL; |
| 797 | case DPLL_ID_LCPLL_810: |
| 798 | return PORT_CLK_SEL_LCPLL_810; |
| 799 | case DPLL_ID_LCPLL_1350: |
| 800 | return PORT_CLK_SEL_LCPLL_1350; |
| 801 | case DPLL_ID_LCPLL_2700: |
| 802 | return PORT_CLK_SEL_LCPLL_2700; |
| 803 | default: |
| 804 | MISSING_CASE(pll->id); |
| 805 | return PORT_CLK_SEL_NONE; |
| 806 | } |
| 807 | } |
| 808 | |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 809 | /* Starting with Haswell, different DDI ports can work in FDI mode for |
| 810 | * connection to the PCH-located connectors. For this, it is necessary to train |
| 811 | * both the DDI port and PCH receiver for the desired DDI buffer settings. |
| 812 | * |
| 813 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, |
| 814 | * please note that when FDI mode is active on DDI E, it shares 2 lines with |
| 815 | * DDI A (which is used for eDP) |
| 816 | */ |
| 817 | |
Ander Conselvan de Oliveira | dc4a109 | 2017-03-02 14:58:54 +0200 | [diff] [blame] | 818 | void hsw_fdi_link_train(struct intel_crtc *crtc, |
| 819 | const struct intel_crtc_state *crtc_state) |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 820 | { |
Ander Conselvan de Oliveira | 4cbe4b2 | 2017-03-02 14:58:51 +0200 | [diff] [blame] | 821 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 822 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 6a7e4f9 | 2015-12-08 19:59:44 +0200 | [diff] [blame] | 823 | struct intel_encoder *encoder; |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 824 | u32 temp, i, rx_ctl_val, ddi_pll_sel; |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 825 | |
Ander Conselvan de Oliveira | 4cbe4b2 | 2017-03-02 14:58:51 +0200 | [diff] [blame] | 826 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
Ville Syrjälä | 6a7e4f9 | 2015-12-08 19:59:44 +0200 | [diff] [blame] | 827 | WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); |
Ville Syrjälä | 32bdc40 | 2016-07-12 15:59:33 +0300 | [diff] [blame] | 828 | intel_prepare_dp_ddi_buffers(encoder); |
Ville Syrjälä | 6a7e4f9 | 2015-12-08 19:59:44 +0200 | [diff] [blame] | 829 | } |
| 830 | |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 831 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
| 832 | * mode set "sequence for CRT port" document: |
| 833 | * - TP1 to TP2 time with the default value |
| 834 | * - FDI delay to 90h |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 835 | * |
| 836 | * WaFDIAutoLinkSetTimingOverrride:hsw |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 837 | */ |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 838 | I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 839 | FDI_RX_PWRDN_LANE0_VAL(2) | |
| 840 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 841 | |
| 842 | /* Enable the PCH Receiver FDI PLL */ |
Damien Lespiau | 3e68320 | 2012-12-11 18:48:29 +0000 | [diff] [blame] | 843 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
Daniel Vetter | 33d29b1 | 2013-02-13 18:04:45 +0100 | [diff] [blame] | 844 | FDI_RX_PLL_ENABLE | |
Ander Conselvan de Oliveira | dc4a109 | 2017-03-02 14:58:54 +0200 | [diff] [blame] | 845 | FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 846 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
| 847 | POSTING_READ(FDI_RX_CTL(PIPE_A)); |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 848 | udelay(220); |
| 849 | |
| 850 | /* Switch from Rawclk to PCDclk */ |
| 851 | rx_ctl_val |= FDI_PCDCLK; |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 852 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 853 | |
| 854 | /* Configure Port Clock Select */ |
Ander Conselvan de Oliveira | dc4a109 | 2017-03-02 14:58:54 +0200 | [diff] [blame] | 855 | ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 856 | I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); |
| 857 | WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 858 | |
| 859 | /* Start the training iterating through available voltages and emphasis, |
| 860 | * testing each value twice. */ |
Jani Nikula | 1012205 | 2014-08-27 16:27:30 +0300 | [diff] [blame] | 861 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 862 | /* Configure DP_TP_CTL with auto-training */ |
| 863 | I915_WRITE(DP_TP_CTL(PORT_E), |
| 864 | DP_TP_CTL_FDI_AUTOTRAIN | |
| 865 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
| 866 | DP_TP_CTL_LINK_TRAIN_PAT1 | |
| 867 | DP_TP_CTL_ENABLE); |
| 868 | |
Damien Lespiau | 876a8cd | 2012-12-11 18:48:30 +0000 | [diff] [blame] | 869 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
| 870 | * DDI E does not support port reversal, the functionality is |
| 871 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the |
| 872 | * port reversal bit */ |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 873 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 874 | DDI_BUF_CTL_ENABLE | |
Ander Conselvan de Oliveira | dc4a109 | 2017-03-02 14:58:54 +0200 | [diff] [blame] | 875 | ((crtc_state->fdi_lanes - 1) << 1) | |
Sonika Jindal | c5fe6a0 | 2014-08-11 08:57:36 +0530 | [diff] [blame] | 876 | DDI_BUF_TRANS_SELECT(i / 2)); |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 877 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 878 | |
| 879 | udelay(600); |
| 880 | |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 881 | /* Program PCH FDI Receiver TU */ |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 882 | I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); |
Eugeni Dodonov | 4acf518 | 2012-07-04 20:15:16 -0300 | [diff] [blame] | 883 | |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 884 | /* Enable PCH FDI Receiver with auto-training */ |
| 885 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 886 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
| 887 | POSTING_READ(FDI_RX_CTL(PIPE_A)); |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 888 | |
| 889 | /* Wait for FDI receiver lane calibration */ |
| 890 | udelay(30); |
| 891 | |
| 892 | /* Unset FDI_RX_MISC pwrdn lanes */ |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 893 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 894 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 895 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
| 896 | POSTING_READ(FDI_RX_MISC(PIPE_A)); |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 897 | |
| 898 | /* Wait for FDI auto training time */ |
| 899 | udelay(5); |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 900 | |
| 901 | temp = I915_READ(DP_TP_STATUS(PORT_E)); |
| 902 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 903 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
Ville Syrjälä | a308ccb | 2015-12-04 22:22:50 +0200 | [diff] [blame] | 904 | break; |
| 905 | } |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 906 | |
Ville Syrjälä | a308ccb | 2015-12-04 22:22:50 +0200 | [diff] [blame] | 907 | /* |
| 908 | * Leave things enabled even if we failed to train FDI. |
| 909 | * Results in less fireworks from the state checker. |
| 910 | */ |
| 911 | if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { |
| 912 | DRM_ERROR("FDI link training failed!\n"); |
| 913 | break; |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 914 | } |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 915 | |
Ville Syrjälä | 5b421c5 | 2016-03-01 16:16:23 +0200 | [diff] [blame] | 916 | rx_ctl_val &= ~FDI_RX_ENABLE; |
| 917 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
| 918 | POSTING_READ(FDI_RX_CTL(PIPE_A)); |
| 919 | |
Paulo Zanoni | 248138b | 2012-11-29 11:29:31 -0200 | [diff] [blame] | 920 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
| 921 | temp &= ~DDI_BUF_CTL_ENABLE; |
| 922 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); |
| 923 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
| 924 | |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 925 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
Paulo Zanoni | 248138b | 2012-11-29 11:29:31 -0200 | [diff] [blame] | 926 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
| 927 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
| 928 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 929 | I915_WRITE(DP_TP_CTL(PORT_E), temp); |
| 930 | POSTING_READ(DP_TP_CTL(PORT_E)); |
| 931 | |
| 932 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 933 | |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 934 | /* Reset FDI_RX_MISC pwrdn lanes */ |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 935 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 936 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
| 937 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 938 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
| 939 | POSTING_READ(FDI_RX_MISC(PIPE_A)); |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 940 | } |
| 941 | |
Ville Syrjälä | a308ccb | 2015-12-04 22:22:50 +0200 | [diff] [blame] | 942 | /* Enable normal pixel sending for FDI */ |
| 943 | I915_WRITE(DP_TP_CTL(PORT_E), |
| 944 | DP_TP_CTL_FDI_AUTOTRAIN | |
| 945 | DP_TP_CTL_LINK_TRAIN_NORMAL | |
| 946 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
| 947 | DP_TP_CTL_ENABLE); |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 948 | } |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 949 | |
Paulo Zanoni | d7c530b | 2017-03-30 17:57:52 -0300 | [diff] [blame] | 950 | static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
Dave Airlie | 44905a27 | 2014-05-02 13:36:43 +1000 | [diff] [blame] | 951 | { |
| 952 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 953 | struct intel_digital_port *intel_dig_port = |
| 954 | enc_to_dig_port(&encoder->base); |
| 955 | |
| 956 | intel_dp->DP = intel_dig_port->saved_port_bits | |
Sonika Jindal | c5fe6a0 | 2014-08-11 08:57:36 +0530 | [diff] [blame] | 957 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 958 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
Dave Airlie | 44905a27 | 2014-05-02 13:36:43 +1000 | [diff] [blame] | 959 | } |
| 960 | |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 961 | static struct intel_encoder * |
Ander Conselvan de Oliveira | e9ce1a6 | 2017-03-02 14:58:55 +0200 | [diff] [blame] | 962 | intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 963 | { |
Ander Conselvan de Oliveira | e9ce1a6 | 2017-03-02 14:58:55 +0200 | [diff] [blame] | 964 | struct drm_device *dev = crtc->base.dev; |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 965 | struct intel_encoder *encoder, *ret = NULL; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 966 | int num_encoders = 0; |
| 967 | |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 968 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
| 969 | ret = encoder; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 970 | num_encoders++; |
| 971 | } |
| 972 | |
| 973 | if (num_encoders != 1) |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 974 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
Ander Conselvan de Oliveira | e9ce1a6 | 2017-03-02 14:58:55 +0200 | [diff] [blame] | 975 | pipe_name(crtc->pipe)); |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 976 | |
| 977 | BUG_ON(ret == NULL); |
| 978 | return ret; |
| 979 | } |
| 980 | |
Paulo Zanoni | 44a126b | 2017-03-22 15:58:45 -0300 | [diff] [blame] | 981 | /* Finds the only possible encoder associated with the given CRTC. */ |
| 982 | struct intel_encoder * |
Ander Conselvan de Oliveira | 3165c07 | 2015-03-20 16:18:12 +0200 | [diff] [blame] | 983 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 984 | { |
Ander Conselvan de Oliveira | 3165c07 | 2015-03-20 16:18:12 +0200 | [diff] [blame] | 985 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
| 986 | struct intel_encoder *ret = NULL; |
| 987 | struct drm_atomic_state *state; |
Ander Conselvan de Oliveira | da3ced2 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 988 | struct drm_connector *connector; |
| 989 | struct drm_connector_state *connector_state; |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 990 | int num_encoders = 0; |
Ander Conselvan de Oliveira | 3165c07 | 2015-03-20 16:18:12 +0200 | [diff] [blame] | 991 | int i; |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 992 | |
Ander Conselvan de Oliveira | 3165c07 | 2015-03-20 16:18:12 +0200 | [diff] [blame] | 993 | state = crtc_state->base.state; |
| 994 | |
Maarten Lankhorst | b77c7a9 | 2017-03-09 15:52:01 +0100 | [diff] [blame] | 995 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
Ander Conselvan de Oliveira | da3ced2 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 996 | if (connector_state->crtc != crtc_state->base.crtc) |
Ander Conselvan de Oliveira | 3165c07 | 2015-03-20 16:18:12 +0200 | [diff] [blame] | 997 | continue; |
| 998 | |
Ander Conselvan de Oliveira | da3ced2 | 2015-04-21 17:12:59 +0300 | [diff] [blame] | 999 | ret = to_intel_encoder(connector_state->best_encoder); |
Ander Conselvan de Oliveira | 3165c07 | 2015-03-20 16:18:12 +0200 | [diff] [blame] | 1000 | num_encoders++; |
Ander Conselvan de Oliveira | d0737e1 | 2014-10-29 11:32:30 +0200 | [diff] [blame] | 1001 | } |
| 1002 | |
| 1003 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, |
| 1004 | pipe_name(crtc->pipe)); |
| 1005 | |
| 1006 | BUG_ON(ret == NULL); |
| 1007 | return ret; |
| 1008 | } |
| 1009 | |
Damien Lespiau | 1c0b85c | 2013-05-10 14:01:51 +0100 | [diff] [blame] | 1010 | #define LC_FREQ 2700 |
Damien Lespiau | 1c0b85c | 2013-05-10 14:01:51 +0100 | [diff] [blame] | 1011 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1012 | static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
| 1013 | i915_reg_t reg) |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1014 | { |
| 1015 | int refclk = LC_FREQ; |
| 1016 | int n, p, r; |
| 1017 | u32 wrpll; |
| 1018 | |
| 1019 | wrpll = I915_READ(reg); |
Daniel Vetter | 114fe48 | 2014-06-25 22:01:48 +0300 | [diff] [blame] | 1020 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
| 1021 | case WRPLL_PLL_SSC: |
| 1022 | case WRPLL_PLL_NON_SSC: |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1023 | /* |
| 1024 | * We could calculate spread here, but our checking |
| 1025 | * code only cares about 5% accuracy, and spread is a max of |
| 1026 | * 0.5% downspread. |
| 1027 | */ |
| 1028 | refclk = 135; |
| 1029 | break; |
Daniel Vetter | 114fe48 | 2014-06-25 22:01:48 +0300 | [diff] [blame] | 1030 | case WRPLL_PLL_LCPLL: |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1031 | refclk = LC_FREQ; |
| 1032 | break; |
| 1033 | default: |
| 1034 | WARN(1, "bad wrpll refclk\n"); |
| 1035 | return 0; |
| 1036 | } |
| 1037 | |
| 1038 | r = wrpll & WRPLL_DIVIDER_REF_MASK; |
| 1039 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; |
| 1040 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; |
| 1041 | |
Jesse Barnes | 20f0ec1 | 2014-01-22 12:58:04 -0800 | [diff] [blame] | 1042 | /* Convert to KHz, p & r have a fixed point portion */ |
| 1043 | return (refclk * n * 100) / (p * r); |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1044 | } |
| 1045 | |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1046 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
| 1047 | uint32_t dpll) |
| 1048 | { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1049 | i915_reg_t cfgcr1_reg, cfgcr2_reg; |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1050 | uint32_t cfgcr1_val, cfgcr2_val; |
| 1051 | uint32_t p0, p1, p2, dco_freq; |
| 1052 | |
Ville Syrjälä | 923c1241 | 2015-09-30 17:06:43 +0300 | [diff] [blame] | 1053 | cfgcr1_reg = DPLL_CFGCR1(dpll); |
| 1054 | cfgcr2_reg = DPLL_CFGCR2(dpll); |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1055 | |
| 1056 | cfgcr1_val = I915_READ(cfgcr1_reg); |
| 1057 | cfgcr2_val = I915_READ(cfgcr2_reg); |
| 1058 | |
| 1059 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; |
| 1060 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; |
| 1061 | |
| 1062 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) |
| 1063 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; |
| 1064 | else |
| 1065 | p1 = 1; |
| 1066 | |
| 1067 | |
| 1068 | switch (p0) { |
| 1069 | case DPLL_CFGCR2_PDIV_1: |
| 1070 | p0 = 1; |
| 1071 | break; |
| 1072 | case DPLL_CFGCR2_PDIV_2: |
| 1073 | p0 = 2; |
| 1074 | break; |
| 1075 | case DPLL_CFGCR2_PDIV_3: |
| 1076 | p0 = 3; |
| 1077 | break; |
| 1078 | case DPLL_CFGCR2_PDIV_7: |
| 1079 | p0 = 7; |
| 1080 | break; |
| 1081 | } |
| 1082 | |
| 1083 | switch (p2) { |
| 1084 | case DPLL_CFGCR2_KDIV_5: |
| 1085 | p2 = 5; |
| 1086 | break; |
| 1087 | case DPLL_CFGCR2_KDIV_2: |
| 1088 | p2 = 2; |
| 1089 | break; |
| 1090 | case DPLL_CFGCR2_KDIV_3: |
| 1091 | p2 = 3; |
| 1092 | break; |
| 1093 | case DPLL_CFGCR2_KDIV_1: |
| 1094 | p2 = 1; |
| 1095 | break; |
| 1096 | } |
| 1097 | |
| 1098 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; |
| 1099 | |
| 1100 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * |
| 1101 | 1000) / 0x8000; |
| 1102 | |
| 1103 | return dco_freq / (p0 * p1 * p2 * 5); |
| 1104 | } |
| 1105 | |
Rodrigo Vivi | a9701a8 | 2017-07-06 13:52:01 -0700 | [diff] [blame] | 1106 | static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
| 1107 | uint32_t pll_id) |
| 1108 | { |
| 1109 | uint32_t cfgcr0, cfgcr1; |
| 1110 | uint32_t p0, p1, p2, dco_freq, ref_clock; |
| 1111 | |
| 1112 | cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); |
| 1113 | cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); |
| 1114 | |
| 1115 | p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK; |
| 1116 | p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK; |
| 1117 | |
| 1118 | if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) |
| 1119 | p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> |
| 1120 | DPLL_CFGCR1_QDIV_RATIO_SHIFT; |
| 1121 | else |
| 1122 | p1 = 1; |
| 1123 | |
| 1124 | |
| 1125 | switch (p0) { |
| 1126 | case DPLL_CFGCR1_PDIV_2: |
| 1127 | p0 = 2; |
| 1128 | break; |
| 1129 | case DPLL_CFGCR1_PDIV_3: |
| 1130 | p0 = 3; |
| 1131 | break; |
| 1132 | case DPLL_CFGCR1_PDIV_5: |
| 1133 | p0 = 5; |
| 1134 | break; |
| 1135 | case DPLL_CFGCR1_PDIV_7: |
| 1136 | p0 = 7; |
| 1137 | break; |
| 1138 | } |
| 1139 | |
| 1140 | switch (p2) { |
| 1141 | case DPLL_CFGCR1_KDIV_1: |
| 1142 | p2 = 1; |
| 1143 | break; |
| 1144 | case DPLL_CFGCR1_KDIV_2: |
| 1145 | p2 = 2; |
| 1146 | break; |
| 1147 | case DPLL_CFGCR1_KDIV_4: |
| 1148 | p2 = 4; |
| 1149 | break; |
| 1150 | } |
| 1151 | |
| 1152 | ref_clock = dev_priv->cdclk.hw.ref; |
| 1153 | |
| 1154 | dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock; |
| 1155 | |
| 1156 | dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> |
| 1157 | DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000; |
| 1158 | |
| 1159 | return dco_freq / (p0 * p1 * p2 * 5); |
| 1160 | } |
| 1161 | |
Ville Syrjälä | 398a017 | 2015-06-30 15:33:51 +0300 | [diff] [blame] | 1162 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
| 1163 | { |
| 1164 | int dotclock; |
| 1165 | |
| 1166 | if (pipe_config->has_pch_encoder) |
| 1167 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
| 1168 | &pipe_config->fdi_m_n); |
Ville Syrjälä | 37a5650 | 2016-06-22 21:57:04 +0300 | [diff] [blame] | 1169 | else if (intel_crtc_has_dp_encoder(pipe_config)) |
Ville Syrjälä | 398a017 | 2015-06-30 15:33:51 +0300 | [diff] [blame] | 1170 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
| 1171 | &pipe_config->dp_m_n); |
| 1172 | else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) |
| 1173 | dotclock = pipe_config->port_clock * 2 / 3; |
| 1174 | else |
| 1175 | dotclock = pipe_config->port_clock; |
| 1176 | |
Shashank Sharma | b22ca99 | 2017-07-24 19:19:32 +0530 | [diff] [blame] | 1177 | if (pipe_config->ycbcr420) |
| 1178 | dotclock *= 2; |
| 1179 | |
Ville Syrjälä | 398a017 | 2015-06-30 15:33:51 +0300 | [diff] [blame] | 1180 | if (pipe_config->pixel_multiplier) |
| 1181 | dotclock /= pipe_config->pixel_multiplier; |
| 1182 | |
| 1183 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
| 1184 | } |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1185 | |
Rodrigo Vivi | a9701a8 | 2017-07-06 13:52:01 -0700 | [diff] [blame] | 1186 | static void cnl_ddi_clock_get(struct intel_encoder *encoder, |
| 1187 | struct intel_crtc_state *pipe_config) |
| 1188 | { |
| 1189 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 1190 | int link_clock = 0; |
| 1191 | uint32_t cfgcr0, pll_id; |
| 1192 | |
| 1193 | pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); |
| 1194 | |
| 1195 | cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); |
| 1196 | |
| 1197 | if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { |
| 1198 | link_clock = cnl_calc_wrpll_link(dev_priv, pll_id); |
| 1199 | } else { |
| 1200 | link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; |
| 1201 | |
| 1202 | switch (link_clock) { |
| 1203 | case DPLL_CFGCR0_LINK_RATE_810: |
| 1204 | link_clock = 81000; |
| 1205 | break; |
| 1206 | case DPLL_CFGCR0_LINK_RATE_1080: |
| 1207 | link_clock = 108000; |
| 1208 | break; |
| 1209 | case DPLL_CFGCR0_LINK_RATE_1350: |
| 1210 | link_clock = 135000; |
| 1211 | break; |
| 1212 | case DPLL_CFGCR0_LINK_RATE_1620: |
| 1213 | link_clock = 162000; |
| 1214 | break; |
| 1215 | case DPLL_CFGCR0_LINK_RATE_2160: |
| 1216 | link_clock = 216000; |
| 1217 | break; |
| 1218 | case DPLL_CFGCR0_LINK_RATE_2700: |
| 1219 | link_clock = 270000; |
| 1220 | break; |
| 1221 | case DPLL_CFGCR0_LINK_RATE_3240: |
| 1222 | link_clock = 324000; |
| 1223 | break; |
| 1224 | case DPLL_CFGCR0_LINK_RATE_4050: |
| 1225 | link_clock = 405000; |
| 1226 | break; |
| 1227 | default: |
| 1228 | WARN(1, "Unsupported link rate\n"); |
| 1229 | break; |
| 1230 | } |
| 1231 | link_clock *= 2; |
| 1232 | } |
| 1233 | |
| 1234 | pipe_config->port_clock = link_clock; |
| 1235 | |
| 1236 | ddi_dotclock_get(pipe_config); |
| 1237 | } |
| 1238 | |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1239 | static void skl_ddi_clock_get(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1240 | struct intel_crtc_state *pipe_config) |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1241 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1242 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1243 | int link_clock = 0; |
| 1244 | uint32_t dpll_ctl1, dpll; |
| 1245 | |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 1246 | dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1247 | |
| 1248 | dpll_ctl1 = I915_READ(DPLL_CTRL1); |
| 1249 | |
| 1250 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { |
| 1251 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); |
| 1252 | } else { |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1253 | link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); |
| 1254 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1255 | |
| 1256 | switch (link_clock) { |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1257 | case DPLL_CTRL1_LINK_RATE_810: |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1258 | link_clock = 81000; |
| 1259 | break; |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1260 | case DPLL_CTRL1_LINK_RATE_1080: |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1261 | link_clock = 108000; |
| 1262 | break; |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1263 | case DPLL_CTRL1_LINK_RATE_1350: |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1264 | link_clock = 135000; |
| 1265 | break; |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1266 | case DPLL_CTRL1_LINK_RATE_1620: |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1267 | link_clock = 162000; |
| 1268 | break; |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1269 | case DPLL_CTRL1_LINK_RATE_2160: |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1270 | link_clock = 216000; |
| 1271 | break; |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1272 | case DPLL_CTRL1_LINK_RATE_2700: |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1273 | link_clock = 270000; |
| 1274 | break; |
| 1275 | default: |
| 1276 | WARN(1, "Unsupported link rate\n"); |
| 1277 | break; |
| 1278 | } |
| 1279 | link_clock *= 2; |
| 1280 | } |
| 1281 | |
| 1282 | pipe_config->port_clock = link_clock; |
| 1283 | |
Ville Syrjälä | 398a017 | 2015-06-30 15:33:51 +0300 | [diff] [blame] | 1284 | ddi_dotclock_get(pipe_config); |
Satheeshakrishna M | 540e732 | 2014-11-13 14:55:16 +0000 | [diff] [blame] | 1285 | } |
| 1286 | |
Daniel Vetter | 3d51278a | 2014-07-29 20:57:08 +0200 | [diff] [blame] | 1287 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1288 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1289 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1290 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1291 | int link_clock = 0; |
| 1292 | u32 val, pll; |
| 1293 | |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 1294 | val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1295 | switch (val & PORT_CLK_SEL_MASK) { |
| 1296 | case PORT_CLK_SEL_LCPLL_810: |
| 1297 | link_clock = 81000; |
| 1298 | break; |
| 1299 | case PORT_CLK_SEL_LCPLL_1350: |
| 1300 | link_clock = 135000; |
| 1301 | break; |
| 1302 | case PORT_CLK_SEL_LCPLL_2700: |
| 1303 | link_clock = 270000; |
| 1304 | break; |
| 1305 | case PORT_CLK_SEL_WRPLL1: |
Ville Syrjälä | 01403de | 2015-09-18 20:03:33 +0300 | [diff] [blame] | 1306 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1307 | break; |
| 1308 | case PORT_CLK_SEL_WRPLL2: |
Ville Syrjälä | 01403de | 2015-09-18 20:03:33 +0300 | [diff] [blame] | 1309 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1310 | break; |
| 1311 | case PORT_CLK_SEL_SPLL: |
| 1312 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; |
| 1313 | if (pll == SPLL_PLL_FREQ_810MHz) |
| 1314 | link_clock = 81000; |
| 1315 | else if (pll == SPLL_PLL_FREQ_1350MHz) |
| 1316 | link_clock = 135000; |
| 1317 | else if (pll == SPLL_PLL_FREQ_2700MHz) |
| 1318 | link_clock = 270000; |
| 1319 | else { |
| 1320 | WARN(1, "bad spll freq\n"); |
| 1321 | return; |
| 1322 | } |
| 1323 | break; |
| 1324 | default: |
| 1325 | WARN(1, "bad port clock sel\n"); |
| 1326 | return; |
| 1327 | } |
| 1328 | |
| 1329 | pipe_config->port_clock = link_clock * 2; |
| 1330 | |
Ville Syrjälä | 398a017 | 2015-06-30 15:33:51 +0300 | [diff] [blame] | 1331 | ddi_dotclock_get(pipe_config); |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 1332 | } |
| 1333 | |
Satheeshakrishna M | 977bb38 | 2014-08-22 09:49:12 +0530 | [diff] [blame] | 1334 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
| 1335 | enum intel_dpll_id dpll) |
| 1336 | { |
Imre Deak | aa610dc | 2015-06-22 23:35:52 +0300 | [diff] [blame] | 1337 | struct intel_shared_dpll *pll; |
| 1338 | struct intel_dpll_hw_state *state; |
Ander Conselvan de Oliveira | 9e2c847 | 2016-05-04 12:11:57 +0300 | [diff] [blame] | 1339 | struct dpll clock; |
Imre Deak | aa610dc | 2015-06-22 23:35:52 +0300 | [diff] [blame] | 1340 | |
| 1341 | /* For DDI ports we always use a shared PLL. */ |
| 1342 | if (WARN_ON(dpll == DPLL_ID_PRIVATE)) |
| 1343 | return 0; |
| 1344 | |
| 1345 | pll = &dev_priv->shared_dplls[dpll]; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1346 | state = &pll->state.hw_state; |
Imre Deak | aa610dc | 2015-06-22 23:35:52 +0300 | [diff] [blame] | 1347 | |
| 1348 | clock.m1 = 2; |
| 1349 | clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; |
| 1350 | if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) |
| 1351 | clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; |
| 1352 | clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; |
| 1353 | clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; |
| 1354 | clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; |
| 1355 | |
| 1356 | return chv_calc_dpll_params(100000, &clock); |
Satheeshakrishna M | 977bb38 | 2014-08-22 09:49:12 +0530 | [diff] [blame] | 1357 | } |
| 1358 | |
| 1359 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, |
| 1360 | struct intel_crtc_state *pipe_config) |
| 1361 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1362 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Satheeshakrishna M | 977bb38 | 2014-08-22 09:49:12 +0530 | [diff] [blame] | 1363 | enum port port = intel_ddi_get_encoder_port(encoder); |
| 1364 | uint32_t dpll = port; |
| 1365 | |
Ville Syrjälä | 398a017 | 2015-06-30 15:33:51 +0300 | [diff] [blame] | 1366 | pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); |
Satheeshakrishna M | 977bb38 | 2014-08-22 09:49:12 +0530 | [diff] [blame] | 1367 | |
Ville Syrjälä | 398a017 | 2015-06-30 15:33:51 +0300 | [diff] [blame] | 1368 | ddi_dotclock_get(pipe_config); |
Satheeshakrishna M | 977bb38 | 2014-08-22 09:49:12 +0530 | [diff] [blame] | 1369 | } |
| 1370 | |
Daniel Vetter | 3d51278a | 2014-07-29 20:57:08 +0200 | [diff] [blame] | 1371 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1372 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | 3d51278a | 2014-07-29 20:57:08 +0200 | [diff] [blame] | 1373 | { |
Tvrtko Ursulin | 0853723 | 2016-10-13 11:03:02 +0100 | [diff] [blame] | 1374 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Damien Lespiau | 22606a1 | 2014-12-12 14:26:57 +0000 | [diff] [blame] | 1375 | |
Tvrtko Ursulin | 0853723 | 2016-10-13 11:03:02 +0100 | [diff] [blame] | 1376 | if (INTEL_GEN(dev_priv) <= 8) |
Damien Lespiau | 22606a1 | 2014-12-12 14:26:57 +0000 | [diff] [blame] | 1377 | hsw_ddi_clock_get(encoder, pipe_config); |
Rodrigo Vivi | b976dc5 | 2017-01-23 10:32:37 -0800 | [diff] [blame] | 1378 | else if (IS_GEN9_BC(dev_priv)) |
Damien Lespiau | 22606a1 | 2014-12-12 14:26:57 +0000 | [diff] [blame] | 1379 | skl_ddi_clock_get(encoder, pipe_config); |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 1380 | else if (IS_GEN9_LP(dev_priv)) |
Satheeshakrishna M | 977bb38 | 2014-08-22 09:49:12 +0530 | [diff] [blame] | 1381 | bxt_ddi_clock_get(encoder, pipe_config); |
Rodrigo Vivi | a9701a8 | 2017-07-06 13:52:01 -0700 | [diff] [blame] | 1382 | else if (IS_CANNONLAKE(dev_priv)) |
| 1383 | cnl_ddi_clock_get(encoder, pipe_config); |
Daniel Vetter | 3d51278a | 2014-07-29 20:57:08 +0200 | [diff] [blame] | 1384 | } |
| 1385 | |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1386 | void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state) |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 1387 | { |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1388 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
Ander Conselvan de Oliveira | e9ce1a6 | 2017-03-02 14:58:55 +0200 | [diff] [blame] | 1389 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1390 | struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1391 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1392 | int type = encoder->type; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 1393 | uint32_t temp; |
| 1394 | |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 1395 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 1396 | WARN_ON(transcoder_is_dsi(cpu_transcoder)); |
| 1397 | |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 1398 | temp = TRANS_MSA_SYNC_CLK; |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1399 | switch (crtc_state->pipe_bpp) { |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 1400 | case 18: |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 1401 | temp |= TRANS_MSA_6_BPC; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 1402 | break; |
| 1403 | case 24: |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 1404 | temp |= TRANS_MSA_8_BPC; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 1405 | break; |
| 1406 | case 30: |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 1407 | temp |= TRANS_MSA_10_BPC; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 1408 | break; |
| 1409 | case 36: |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 1410 | temp |= TRANS_MSA_12_BPC; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 1411 | break; |
| 1412 | default: |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 1413 | BUG(); |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 1414 | } |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 1415 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 1416 | } |
| 1417 | } |
| 1418 | |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1419 | void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, |
| 1420 | bool state) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1421 | { |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1422 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
Ander Conselvan de Oliveira | e9ce1a6 | 2017-03-02 14:58:55 +0200 | [diff] [blame] | 1423 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1424 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1425 | uint32_t temp; |
| 1426 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
| 1427 | if (state == true) |
| 1428 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; |
| 1429 | else |
| 1430 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; |
| 1431 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
| 1432 | } |
| 1433 | |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1434 | void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1435 | { |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1436 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1437 | struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); |
Ander Conselvan de Oliveira | e9ce1a6 | 2017-03-02 14:58:55 +0200 | [diff] [blame] | 1438 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 1439 | enum pipe pipe = crtc->pipe; |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1440 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1441 | enum port port = intel_ddi_get_encoder_port(encoder); |
| 1442 | int type = encoder->type; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1443 | uint32_t temp; |
| 1444 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1445 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
| 1446 | temp = TRANS_DDI_FUNC_ENABLE; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 1447 | temp |= TRANS_DDI_SELECT_PORT(port); |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 1448 | |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1449 | switch (crtc_state->pipe_bpp) { |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 1450 | case 18: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1451 | temp |= TRANS_DDI_BPC_6; |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 1452 | break; |
| 1453 | case 24: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1454 | temp |= TRANS_DDI_BPC_8; |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 1455 | break; |
| 1456 | case 30: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1457 | temp |= TRANS_DDI_BPC_10; |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 1458 | break; |
| 1459 | case 36: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1460 | temp |= TRANS_DDI_BPC_12; |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 1461 | break; |
| 1462 | default: |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 1463 | BUG(); |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 1464 | } |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 1465 | |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1466 | if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1467 | temp |= TRANS_DDI_PVSYNC; |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1468 | if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1469 | temp |= TRANS_DDI_PHSYNC; |
Paulo Zanoni | f63eb7c4 | 2012-08-08 14:15:28 -0300 | [diff] [blame] | 1470 | |
Paulo Zanoni | e6f0bfc | 2012-10-23 18:30:04 -0200 | [diff] [blame] | 1471 | if (cpu_transcoder == TRANSCODER_EDP) { |
| 1472 | switch (pipe) { |
| 1473 | case PIPE_A: |
Paulo Zanoni | c7670b1 | 2013-11-02 21:07:37 -0700 | [diff] [blame] | 1474 | /* On Haswell, can only use the always-on power well for |
| 1475 | * eDP when not using the panel fitter, and when not |
| 1476 | * using motion blur mitigation (which we don't |
| 1477 | * support). */ |
Tvrtko Ursulin | 772c2a5 | 2016-10-13 11:03:01 +0100 | [diff] [blame] | 1478 | if (IS_HASWELL(dev_priv) && |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1479 | (crtc_state->pch_pfit.enabled || |
| 1480 | crtc_state->pch_pfit.force_thru)) |
Daniel Vetter | d6dd9eb | 2013-01-29 16:35:20 -0200 | [diff] [blame] | 1481 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
| 1482 | else |
| 1483 | temp |= TRANS_DDI_EDP_INPUT_A_ON; |
Paulo Zanoni | e6f0bfc | 2012-10-23 18:30:04 -0200 | [diff] [blame] | 1484 | break; |
| 1485 | case PIPE_B: |
| 1486 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; |
| 1487 | break; |
| 1488 | case PIPE_C: |
| 1489 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; |
| 1490 | break; |
| 1491 | default: |
| 1492 | BUG(); |
| 1493 | break; |
| 1494 | } |
| 1495 | } |
| 1496 | |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 1497 | if (type == INTEL_OUTPUT_HDMI) { |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1498 | if (crtc_state->has_hdmi_sink) |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1499 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1500 | else |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1501 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
Shashank Sharma | 1595363 | 2017-03-13 16:54:03 +0530 | [diff] [blame] | 1502 | |
| 1503 | if (crtc_state->hdmi_scrambling) |
| 1504 | temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK; |
| 1505 | if (crtc_state->hdmi_high_tmds_clock_ratio) |
| 1506 | temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 1507 | } else if (type == INTEL_OUTPUT_ANALOG) { |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1508 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1509 | temp |= (crtc_state->fdi_lanes - 1) << 1; |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 1510 | } else if (type == INTEL_OUTPUT_DP || |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 1511 | type == INTEL_OUTPUT_EDP) { |
Ville Syrjälä | 64ee2fd | 2016-07-28 17:50:39 +0300 | [diff] [blame] | 1512 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1513 | temp |= DDI_PORT_WIDTH(crtc_state->lane_count); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1514 | } else if (type == INTEL_OUTPUT_DP_MST) { |
Ville Syrjälä | 64ee2fd | 2016-07-28 17:50:39 +0300 | [diff] [blame] | 1515 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1516 | temp |= DDI_PORT_WIDTH(crtc_state->lane_count); |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1517 | } else { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 1518 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1519 | encoder->type, pipe_name(pipe)); |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1520 | } |
| 1521 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1522 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1523 | } |
| 1524 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1525 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| 1526 | enum transcoder cpu_transcoder) |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1527 | { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1528 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1529 | uint32_t val = I915_READ(reg); |
| 1530 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1531 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1532 | val |= TRANS_DDI_PORT_NONE; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1533 | I915_WRITE(reg, val); |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 1534 | } |
| 1535 | |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1536 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
| 1537 | { |
| 1538 | struct drm_device *dev = intel_connector->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1539 | struct drm_i915_private *dev_priv = to_i915(dev); |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1540 | struct intel_encoder *encoder = intel_connector->encoder; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1541 | int type = intel_connector->base.connector_type; |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1542 | enum port port = intel_ddi_get_encoder_port(encoder); |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1543 | enum pipe pipe = 0; |
| 1544 | enum transcoder cpu_transcoder; |
| 1545 | uint32_t tmp; |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1546 | bool ret; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1547 | |
Ander Conselvan de Oliveira | 79f255a | 2017-02-22 08:34:27 +0200 | [diff] [blame] | 1548 | if (!intel_display_power_get_if_enabled(dev_priv, |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1549 | encoder->power_domain)) |
Paulo Zanoni | 882244a | 2014-04-01 14:55:12 -0300 | [diff] [blame] | 1550 | return false; |
| 1551 | |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1552 | if (!encoder->get_hw_state(encoder, &pipe)) { |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1553 | ret = false; |
| 1554 | goto out; |
| 1555 | } |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1556 | |
| 1557 | if (port == PORT_A) |
| 1558 | cpu_transcoder = TRANSCODER_EDP; |
| 1559 | else |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1560 | cpu_transcoder = (enum transcoder) pipe; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1561 | |
| 1562 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
| 1563 | |
| 1564 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { |
| 1565 | case TRANS_DDI_MODE_SELECT_HDMI: |
| 1566 | case TRANS_DDI_MODE_SELECT_DVI: |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1567 | ret = type == DRM_MODE_CONNECTOR_HDMIA; |
| 1568 | break; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1569 | |
| 1570 | case TRANS_DDI_MODE_SELECT_DP_SST: |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1571 | ret = type == DRM_MODE_CONNECTOR_eDP || |
| 1572 | type == DRM_MODE_CONNECTOR_DisplayPort; |
| 1573 | break; |
| 1574 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1575 | case TRANS_DDI_MODE_SELECT_DP_MST: |
| 1576 | /* if the transcoder is in MST state then |
| 1577 | * connector isn't connected */ |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1578 | ret = false; |
| 1579 | break; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1580 | |
| 1581 | case TRANS_DDI_MODE_SELECT_FDI: |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1582 | ret = type == DRM_MODE_CONNECTOR_VGA; |
| 1583 | break; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1584 | |
| 1585 | default: |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1586 | ret = false; |
| 1587 | break; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1588 | } |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1589 | |
| 1590 | out: |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1591 | intel_display_power_put(dev_priv, encoder->power_domain); |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1592 | |
| 1593 | return ret; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 1594 | } |
| 1595 | |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1596 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
| 1597 | enum pipe *pipe) |
| 1598 | { |
| 1599 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1600 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | fe43d3f | 2012-10-15 15:51:39 -0300 | [diff] [blame] | 1601 | enum port port = intel_ddi_get_encoder_port(encoder); |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1602 | u32 tmp; |
| 1603 | int i; |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1604 | bool ret; |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1605 | |
Ander Conselvan de Oliveira | 79f255a | 2017-02-22 08:34:27 +0200 | [diff] [blame] | 1606 | if (!intel_display_power_get_if_enabled(dev_priv, |
| 1607 | encoder->power_domain)) |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 1608 | return false; |
| 1609 | |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1610 | ret = false; |
| 1611 | |
Paulo Zanoni | fe43d3f | 2012-10-15 15:51:39 -0300 | [diff] [blame] | 1612 | tmp = I915_READ(DDI_BUF_CTL(port)); |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1613 | |
| 1614 | if (!(tmp & DDI_BUF_CTL_ENABLE)) |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1615 | goto out; |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1616 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1617 | if (port == PORT_A) { |
| 1618 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1619 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1620 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
| 1621 | case TRANS_DDI_EDP_INPUT_A_ON: |
| 1622 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
| 1623 | *pipe = PIPE_A; |
| 1624 | break; |
| 1625 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
| 1626 | *pipe = PIPE_B; |
| 1627 | break; |
| 1628 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
| 1629 | *pipe = PIPE_C; |
| 1630 | break; |
| 1631 | } |
| 1632 | |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1633 | ret = true; |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1634 | |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1635 | goto out; |
| 1636 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1637 | |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1638 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
| 1639 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); |
| 1640 | |
| 1641 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { |
| 1642 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == |
| 1643 | TRANS_DDI_MODE_SELECT_DP_MST) |
| 1644 | goto out; |
| 1645 | |
| 1646 | *pipe = i; |
| 1647 | ret = true; |
| 1648 | |
| 1649 | goto out; |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1650 | } |
| 1651 | } |
| 1652 | |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 1653 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1654 | |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1655 | out: |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 1656 | if (ret && IS_GEN9_LP(dev_priv)) { |
Imre Deak | e93da0a | 2016-06-13 16:44:37 +0300 | [diff] [blame] | 1657 | tmp = I915_READ(BXT_PHY_CTL(port)); |
| 1658 | if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK | |
| 1659 | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) |
| 1660 | DRM_ERROR("Port %c enabled but PHY powered down? " |
| 1661 | "(PHY_CTL %08x)\n", port_name(port), tmp); |
| 1662 | } |
| 1663 | |
Ander Conselvan de Oliveira | 79f255a | 2017-02-22 08:34:27 +0200 | [diff] [blame] | 1664 | intel_display_power_put(dev_priv, encoder->power_domain); |
Imre Deak | e27daab | 2016-02-12 18:55:16 +0200 | [diff] [blame] | 1665 | |
| 1666 | return ret; |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1667 | } |
| 1668 | |
Ander Conselvan de Oliveira | 62b6956 | 2017-02-24 16:19:59 +0200 | [diff] [blame] | 1669 | static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder) |
| 1670 | { |
| 1671 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); |
| 1672 | enum pipe pipe; |
| 1673 | |
| 1674 | if (intel_ddi_get_hw_state(encoder, &pipe)) |
| 1675 | return BIT_ULL(dig_port->ddi_io_power_domain); |
| 1676 | |
| 1677 | return 0; |
| 1678 | } |
| 1679 | |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1680 | void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1681 | { |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1682 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
Ander Conselvan de Oliveira | e9ce1a6 | 2017-03-02 14:58:55 +0200 | [diff] [blame] | 1683 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 1684 | struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); |
| 1685 | enum port port = intel_ddi_get_encoder_port(encoder); |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1686 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1687 | |
Paulo Zanoni | bb523fc | 2012-10-23 18:29:56 -0200 | [diff] [blame] | 1688 | if (cpu_transcoder != TRANSCODER_EDP) |
| 1689 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
| 1690 | TRANS_CLK_SEL_PORT(port)); |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1691 | } |
| 1692 | |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1693 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1694 | { |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 1695 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
| 1696 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1697 | |
Paulo Zanoni | bb523fc | 2012-10-23 18:29:56 -0200 | [diff] [blame] | 1698 | if (cpu_transcoder != TRANSCODER_EDP) |
| 1699 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
| 1700 | TRANS_CLK_SEL_DISABLED); |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1701 | } |
| 1702 | |
Ville Syrjälä | a7d8dbc | 2016-07-12 15:59:28 +0300 | [diff] [blame] | 1703 | static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, |
| 1704 | enum port port, uint8_t iboost) |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 1705 | { |
Ville Syrjälä | a7d8dbc | 2016-07-12 15:59:28 +0300 | [diff] [blame] | 1706 | u32 tmp; |
| 1707 | |
| 1708 | tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); |
| 1709 | tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); |
| 1710 | if (iboost) |
| 1711 | tmp |= iboost << BALANCE_LEG_SHIFT(port); |
| 1712 | else |
| 1713 | tmp |= BALANCE_LEG_DISABLE(port); |
| 1714 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); |
| 1715 | } |
| 1716 | |
| 1717 | static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level) |
| 1718 | { |
| 1719 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
| 1720 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
| 1721 | enum port port = intel_dig_port->port; |
| 1722 | int type = encoder->type; |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 1723 | const struct ddi_buf_trans *ddi_translations; |
| 1724 | uint8_t iboost; |
Antti Koskipaa | 75067dd | 2015-07-10 14:10:55 +0300 | [diff] [blame] | 1725 | uint8_t dp_iboost, hdmi_iboost; |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 1726 | int n_entries; |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 1727 | |
Antti Koskipaa | 75067dd | 2015-07-10 14:10:55 +0300 | [diff] [blame] | 1728 | /* VBT may override standard boost values */ |
| 1729 | dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; |
| 1730 | hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; |
| 1731 | |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 1732 | if (type == INTEL_OUTPUT_DP) { |
Antti Koskipaa | 75067dd | 2015-07-10 14:10:55 +0300 | [diff] [blame] | 1733 | if (dp_iboost) { |
| 1734 | iboost = dp_iboost; |
| 1735 | } else { |
Rodrigo Vivi | da411a4 | 2017-06-09 15:02:50 -0700 | [diff] [blame] | 1736 | if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) |
Rodrigo Vivi | 0fdd491 | 2016-10-18 08:57:36 -0700 | [diff] [blame] | 1737 | ddi_translations = kbl_get_buf_trans_dp(dev_priv, |
| 1738 | &n_entries); |
| 1739 | else |
| 1740 | ddi_translations = skl_get_buf_trans_dp(dev_priv, |
| 1741 | &n_entries); |
Ander Conselvan de Oliveira | e4d4c05 | 2015-11-11 15:15:54 +0200 | [diff] [blame] | 1742 | iboost = ddi_translations[level].i_boost; |
Antti Koskipaa | 75067dd | 2015-07-10 14:10:55 +0300 | [diff] [blame] | 1743 | } |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 1744 | } else if (type == INTEL_OUTPUT_EDP) { |
Antti Koskipaa | 75067dd | 2015-07-10 14:10:55 +0300 | [diff] [blame] | 1745 | if (dp_iboost) { |
| 1746 | iboost = dp_iboost; |
| 1747 | } else { |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 1748 | ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); |
Ville Syrjälä | 10afa0b | 2015-12-08 19:59:43 +0200 | [diff] [blame] | 1749 | |
| 1750 | if (WARN_ON(port != PORT_A && |
| 1751 | port != PORT_E && n_entries > 9)) |
| 1752 | n_entries = 9; |
| 1753 | |
Ander Conselvan de Oliveira | e4d4c05 | 2015-11-11 15:15:54 +0200 | [diff] [blame] | 1754 | iboost = ddi_translations[level].i_boost; |
Antti Koskipaa | 75067dd | 2015-07-10 14:10:55 +0300 | [diff] [blame] | 1755 | } |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 1756 | } else if (type == INTEL_OUTPUT_HDMI) { |
Antti Koskipaa | 75067dd | 2015-07-10 14:10:55 +0300 | [diff] [blame] | 1757 | if (hdmi_iboost) { |
| 1758 | iboost = hdmi_iboost; |
| 1759 | } else { |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 1760 | ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); |
Ander Conselvan de Oliveira | e4d4c05 | 2015-11-11 15:15:54 +0200 | [diff] [blame] | 1761 | iboost = ddi_translations[level].i_boost; |
Antti Koskipaa | 75067dd | 2015-07-10 14:10:55 +0300 | [diff] [blame] | 1762 | } |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 1763 | } else { |
| 1764 | return; |
| 1765 | } |
| 1766 | |
| 1767 | /* Make sure that the requested I_boost is valid */ |
| 1768 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { |
| 1769 | DRM_ERROR("Invalid I_boost value %u\n", iboost); |
| 1770 | return; |
| 1771 | } |
| 1772 | |
Ville Syrjälä | a7d8dbc | 2016-07-12 15:59:28 +0300 | [diff] [blame] | 1773 | _skl_ddi_set_iboost(dev_priv, port, iboost); |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 1774 | |
Ville Syrjälä | a7d8dbc | 2016-07-12 15:59:28 +0300 | [diff] [blame] | 1775 | if (port == PORT_A && intel_dig_port->max_lanes == 4) |
| 1776 | _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 1777 | } |
| 1778 | |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 1779 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
| 1780 | u32 level, enum port port, int type) |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 1781 | { |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 1782 | const struct bxt_ddi_buf_trans *ddi_translations; |
| 1783 | u32 n_entries, i; |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 1784 | |
Jani Nikula | 06411f0 | 2016-03-24 17:50:21 +0200 | [diff] [blame] | 1785 | if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { |
Sonika Jindal | d9d7000 | 2015-09-24 10:24:56 +0530 | [diff] [blame] | 1786 | n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); |
| 1787 | ddi_translations = bxt_ddi_translations_edp; |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 1788 | } else if (type == INTEL_OUTPUT_DP |
Sonika Jindal | d9d7000 | 2015-09-24 10:24:56 +0530 | [diff] [blame] | 1789 | || type == INTEL_OUTPUT_EDP) { |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 1790 | n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); |
| 1791 | ddi_translations = bxt_ddi_translations_dp; |
| 1792 | } else if (type == INTEL_OUTPUT_HDMI) { |
| 1793 | n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); |
| 1794 | ddi_translations = bxt_ddi_translations_hdmi; |
| 1795 | } else { |
| 1796 | DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", |
| 1797 | type); |
| 1798 | return; |
| 1799 | } |
| 1800 | |
| 1801 | /* Check if default value has to be used */ |
| 1802 | if (level >= n_entries || |
| 1803 | (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { |
| 1804 | for (i = 0; i < n_entries; i++) { |
| 1805 | if (ddi_translations[i].default_index) { |
| 1806 | level = i; |
| 1807 | break; |
| 1808 | } |
| 1809 | } |
| 1810 | } |
| 1811 | |
Ander Conselvan de Oliveira | b6e0820 | 2016-10-06 19:22:19 +0300 | [diff] [blame] | 1812 | bxt_ddi_phy_set_signal_level(dev_priv, port, |
| 1813 | ddi_translations[level].margin, |
| 1814 | ddi_translations[level].scale, |
| 1815 | ddi_translations[level].enable, |
| 1816 | ddi_translations[level].deemphasis); |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 1817 | } |
| 1818 | |
Ville Syrjälä | ffe5111 | 2017-02-23 19:49:01 +0200 | [diff] [blame] | 1819 | u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) |
| 1820 | { |
| 1821 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 1822 | int n_entries; |
| 1823 | |
| 1824 | if (encoder->type == INTEL_OUTPUT_EDP) |
| 1825 | intel_ddi_get_buf_trans_edp(dev_priv, &n_entries); |
| 1826 | else |
| 1827 | intel_ddi_get_buf_trans_dp(dev_priv, &n_entries); |
| 1828 | |
| 1829 | if (WARN_ON(n_entries < 1)) |
| 1830 | n_entries = 1; |
| 1831 | if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) |
| 1832 | n_entries = ARRAY_SIZE(index_to_dp_signal_levels); |
| 1833 | |
| 1834 | return index_to_dp_signal_levels[n_entries - 1] & |
| 1835 | DP_TRAIN_VOLTAGE_SWING_MASK; |
| 1836 | } |
| 1837 | |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1838 | static const struct cnl_ddi_buf_trans * |
| 1839 | cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, |
| 1840 | u32 voltage, int *n_entries) |
| 1841 | { |
| 1842 | if (voltage == VOLTAGE_INFO_0_85V) { |
| 1843 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); |
| 1844 | return cnl_ddi_translations_hdmi_0_85V; |
| 1845 | } else if (voltage == VOLTAGE_INFO_0_95V) { |
| 1846 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); |
| 1847 | return cnl_ddi_translations_hdmi_0_95V; |
| 1848 | } else if (voltage == VOLTAGE_INFO_1_05V) { |
| 1849 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); |
| 1850 | return cnl_ddi_translations_hdmi_1_05V; |
| 1851 | } |
| 1852 | return NULL; |
| 1853 | } |
| 1854 | |
| 1855 | static const struct cnl_ddi_buf_trans * |
| 1856 | cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, |
| 1857 | u32 voltage, int *n_entries) |
| 1858 | { |
| 1859 | if (voltage == VOLTAGE_INFO_0_85V) { |
| 1860 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); |
| 1861 | return cnl_ddi_translations_dp_0_85V; |
| 1862 | } else if (voltage == VOLTAGE_INFO_0_95V) { |
| 1863 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); |
| 1864 | return cnl_ddi_translations_dp_0_95V; |
| 1865 | } else if (voltage == VOLTAGE_INFO_1_05V) { |
| 1866 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); |
| 1867 | return cnl_ddi_translations_dp_1_05V; |
| 1868 | } |
| 1869 | return NULL; |
| 1870 | } |
| 1871 | |
| 1872 | static const struct cnl_ddi_buf_trans * |
| 1873 | cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, |
| 1874 | u32 voltage, int *n_entries) |
| 1875 | { |
| 1876 | if (dev_priv->vbt.edp.low_vswing) { |
| 1877 | if (voltage == VOLTAGE_INFO_0_85V) { |
| 1878 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); |
Matthias Kaehlcke | 50946c89 | 2017-07-17 12:58:54 -0700 | [diff] [blame] | 1879 | return cnl_ddi_translations_edp_0_85V; |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1880 | } else if (voltage == VOLTAGE_INFO_0_95V) { |
| 1881 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); |
| 1882 | return cnl_ddi_translations_edp_0_95V; |
| 1883 | } else if (voltage == VOLTAGE_INFO_1_05V) { |
| 1884 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); |
| 1885 | return cnl_ddi_translations_edp_1_05V; |
| 1886 | } |
| 1887 | return NULL; |
| 1888 | } else { |
| 1889 | return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries); |
| 1890 | } |
| 1891 | } |
| 1892 | |
| 1893 | static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, |
| 1894 | u32 level, enum port port, int type) |
| 1895 | { |
| 1896 | const struct cnl_ddi_buf_trans *ddi_translations = NULL; |
| 1897 | u32 n_entries, val, voltage; |
| 1898 | int ln; |
| 1899 | |
| 1900 | /* |
| 1901 | * Values for each port type are listed in |
| 1902 | * voltage swing programming tables. |
| 1903 | * Vccio voltage found in PORT_COMP_DW3. |
| 1904 | */ |
| 1905 | voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; |
| 1906 | |
| 1907 | if (type == INTEL_OUTPUT_HDMI) { |
| 1908 | ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, |
| 1909 | voltage, &n_entries); |
| 1910 | } else if (type == INTEL_OUTPUT_DP) { |
| 1911 | ddi_translations = cnl_get_buf_trans_dp(dev_priv, |
| 1912 | voltage, &n_entries); |
| 1913 | } else if (type == INTEL_OUTPUT_EDP) { |
| 1914 | ddi_translations = cnl_get_buf_trans_edp(dev_priv, |
| 1915 | voltage, &n_entries); |
| 1916 | } |
| 1917 | |
| 1918 | if (ddi_translations == NULL) { |
| 1919 | MISSING_CASE(voltage); |
| 1920 | return; |
| 1921 | } |
| 1922 | |
| 1923 | if (level >= n_entries) { |
| 1924 | DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); |
| 1925 | level = n_entries - 1; |
| 1926 | } |
| 1927 | |
| 1928 | /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ |
| 1929 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); |
Rodrigo Vivi | 1f588ae | 2017-06-19 11:39:32 -0700 | [diff] [blame] | 1930 | val &= ~SCALING_MODE_SEL_MASK; |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1931 | val |= SCALING_MODE_SEL(2); |
| 1932 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); |
| 1933 | |
| 1934 | /* Program PORT_TX_DW2 */ |
| 1935 | val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); |
Rodrigo Vivi | 1f588ae | 2017-06-19 11:39:32 -0700 | [diff] [blame] | 1936 | val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | |
| 1937 | RCOMP_SCALAR_MASK); |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1938 | val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); |
| 1939 | val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); |
| 1940 | /* Rcomp scalar is fixed as 0x98 for every table entry */ |
| 1941 | val |= RCOMP_SCALAR(0x98); |
| 1942 | I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); |
| 1943 | |
| 1944 | /* Program PORT_TX_DW4 */ |
| 1945 | /* We cannot write to GRP. It would overrite individual loadgen */ |
| 1946 | for (ln = 0; ln < 4; ln++) { |
| 1947 | val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); |
Rodrigo Vivi | 1f588ae | 2017-06-19 11:39:32 -0700 | [diff] [blame] | 1948 | val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | |
| 1949 | CURSOR_COEFF_MASK); |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1950 | val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); |
| 1951 | val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); |
| 1952 | val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); |
| 1953 | I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); |
| 1954 | } |
| 1955 | |
| 1956 | /* Program PORT_TX_DW5 */ |
| 1957 | /* All DW5 values are fixed for every table entry */ |
| 1958 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); |
Rodrigo Vivi | 1f588ae | 2017-06-19 11:39:32 -0700 | [diff] [blame] | 1959 | val &= ~RTERM_SELECT_MASK; |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1960 | val |= RTERM_SELECT(6); |
| 1961 | val |= TAP3_DISABLE; |
| 1962 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); |
| 1963 | |
| 1964 | /* Program PORT_TX_DW7 */ |
| 1965 | val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); |
Rodrigo Vivi | 1f588ae | 2017-06-19 11:39:32 -0700 | [diff] [blame] | 1966 | val &= ~N_SCALAR_MASK; |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1967 | val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); |
| 1968 | I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); |
| 1969 | } |
| 1970 | |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 1971 | static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level) |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1972 | { |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 1973 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 1974 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1975 | enum port port = intel_ddi_get_encoder_port(encoder); |
| 1976 | int type = encoder->type; |
| 1977 | int width = 0; |
| 1978 | int rate = 0; |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1979 | u32 val; |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 1980 | int ln = 0; |
| 1981 | |
| 1982 | if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) { |
| 1983 | width = intel_dp->lane_count; |
| 1984 | rate = intel_dp->link_rate; |
Rodrigo Vivi | 61f3e77 | 2017-07-10 13:58:52 -0700 | [diff] [blame] | 1985 | } else if (type == INTEL_OUTPUT_HDMI) { |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 1986 | width = 4; |
| 1987 | /* Rate is always < than 6GHz for HDMI */ |
Rodrigo Vivi | 61f3e77 | 2017-07-10 13:58:52 -0700 | [diff] [blame] | 1988 | } else { |
| 1989 | MISSING_CASE(type); |
| 1990 | return; |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 1991 | } |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 1992 | |
| 1993 | /* |
| 1994 | * 1. If port type is eDP or DP, |
| 1995 | * set PORT_PCS_DW1 cmnkeeper_enable to 1b, |
| 1996 | * else clear to 0b. |
| 1997 | */ |
| 1998 | val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); |
| 1999 | if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP) |
| 2000 | val |= COMMON_KEEPER_EN; |
| 2001 | else |
| 2002 | val &= ~COMMON_KEEPER_EN; |
| 2003 | I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val); |
| 2004 | |
| 2005 | /* 2. Program loadgen select */ |
| 2006 | /* |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 2007 | * Program PORT_TX_DW4_LN depending on Bit rate and used lanes |
| 2008 | * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) |
| 2009 | * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) |
| 2010 | * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 2011 | */ |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 2012 | for (ln = 0; ln <= 3; ln++) { |
| 2013 | val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); |
| 2014 | val &= ~LOADGEN_SELECT; |
| 2015 | |
Navare, Manasi D | a8e45a1 | 2017-07-17 15:05:22 -0700 | [diff] [blame] | 2016 | if ((rate <= 600000 && width == 4 && ln >= 1) || |
| 2017 | (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 2018 | val |= LOADGEN_SELECT; |
| 2019 | } |
| 2020 | I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); |
| 2021 | } |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 2022 | |
| 2023 | /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ |
| 2024 | val = I915_READ(CNL_PORT_CL1CM_DW5); |
| 2025 | val |= SUS_CLOCK_CONFIG; |
| 2026 | I915_WRITE(CNL_PORT_CL1CM_DW5, val); |
| 2027 | |
| 2028 | /* 4. Clear training enable to change swing values */ |
| 2029 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); |
| 2030 | val &= ~TX_TRAINING_EN; |
| 2031 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); |
| 2032 | |
| 2033 | /* 5. Program swing and de-emphasis */ |
| 2034 | cnl_ddi_vswing_program(dev_priv, level, port, type); |
| 2035 | |
| 2036 | /* 6. Set training enable to trigger update */ |
| 2037 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); |
| 2038 | val |= TX_TRAINING_EN; |
| 2039 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); |
| 2040 | } |
| 2041 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 2042 | static uint32_t translate_signal_level(int signal_levels) |
| 2043 | { |
Ville Syrjälä | 97eeb87 | 2017-02-23 19:35:06 +0200 | [diff] [blame] | 2044 | int i; |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 2045 | |
Ville Syrjälä | 97eeb87 | 2017-02-23 19:35:06 +0200 | [diff] [blame] | 2046 | for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { |
| 2047 | if (index_to_dp_signal_levels[i] == signal_levels) |
| 2048 | return i; |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 2049 | } |
| 2050 | |
Ville Syrjälä | 97eeb87 | 2017-02-23 19:35:06 +0200 | [diff] [blame] | 2051 | WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", |
| 2052 | signal_levels); |
| 2053 | |
| 2054 | return 0; |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 2055 | } |
| 2056 | |
| 2057 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) |
| 2058 | { |
| 2059 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 2060 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 2061 | struct intel_encoder *encoder = &dport->base; |
| 2062 | uint8_t train_set = intel_dp->train_set[0]; |
| 2063 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 2064 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 2065 | enum port port = dport->port; |
| 2066 | uint32_t level; |
| 2067 | |
| 2068 | level = translate_signal_level(signal_levels); |
| 2069 | |
Rodrigo Vivi | b976dc5 | 2017-01-23 10:32:37 -0800 | [diff] [blame] | 2070 | if (IS_GEN9_BC(dev_priv)) |
Ville Syrjälä | a7d8dbc | 2016-07-12 15:59:28 +0300 | [diff] [blame] | 2071 | skl_ddi_set_iboost(encoder, level); |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 2072 | else if (IS_GEN9_LP(dev_priv)) |
Ville Syrjälä | 78ab0ba | 2015-12-08 19:59:41 +0200 | [diff] [blame] | 2073 | bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 2074 | else if (IS_CANNONLAKE(dev_priv)) { |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 2075 | cnl_ddi_vswing_sequence(encoder, level); |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 2076 | /* DDI_BUF_CTL bits 27:24 are reserved on CNL */ |
| 2077 | return 0; |
| 2078 | } |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 2079 | return DDI_BUF_TRANS_SELECT(level); |
| 2080 | } |
| 2081 | |
Paulo Zanoni | d7c530b | 2017-03-30 17:57:52 -0300 | [diff] [blame] | 2082 | static void intel_ddi_clk_select(struct intel_encoder *encoder, |
| 2083 | struct intel_shared_dpll *pll) |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 2084 | { |
Ville Syrjälä | e404ba8d | 2015-08-17 18:46:20 +0300 | [diff] [blame] | 2085 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 2086 | enum port port = intel_ddi_get_encoder_port(encoder); |
Rodrigo Vivi | 555e38d | 2017-06-09 15:26:02 -0700 | [diff] [blame] | 2087 | uint32_t val; |
Paulo Zanoni | 82a4d9c | 2012-10-23 18:30:07 -0200 | [diff] [blame] | 2088 | |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 2089 | if (WARN_ON(!pll)) |
| 2090 | return; |
| 2091 | |
Rodrigo Vivi | 555e38d | 2017-06-09 15:26:02 -0700 | [diff] [blame] | 2092 | if (IS_CANNONLAKE(dev_priv)) { |
| 2093 | /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ |
| 2094 | val = I915_READ(DPCLKA_CFGCR0); |
| 2095 | val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port); |
| 2096 | I915_WRITE(DPCLKA_CFGCR0, val); |
Satheeshakrishna M | efa80ad | 2014-11-13 14:55:19 +0000 | [diff] [blame] | 2097 | |
Rodrigo Vivi | 555e38d | 2017-06-09 15:26:02 -0700 | [diff] [blame] | 2098 | /* |
| 2099 | * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. |
| 2100 | * This step and the step before must be done with separate |
| 2101 | * register writes. |
| 2102 | */ |
| 2103 | val = I915_READ(DPCLKA_CFGCR0); |
| 2104 | val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) | |
| 2105 | DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)); |
| 2106 | I915_WRITE(DPCLKA_CFGCR0, val); |
| 2107 | } else if (IS_GEN9_BC(dev_priv)) { |
Damien Lespiau | 5416d87 | 2014-11-14 17:24:33 +0000 | [diff] [blame] | 2108 | /* DDI -> PLL mapping */ |
Satheeshakrishna M | efa80ad | 2014-11-13 14:55:19 +0000 | [diff] [blame] | 2109 | val = I915_READ(DPLL_CTRL2); |
| 2110 | |
| 2111 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | |
| 2112 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 2113 | val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) | |
Satheeshakrishna M | efa80ad | 2014-11-13 14:55:19 +0000 | [diff] [blame] | 2114 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); |
| 2115 | |
| 2116 | I915_WRITE(DPLL_CTRL2, val); |
Damien Lespiau | 5416d87 | 2014-11-14 17:24:33 +0000 | [diff] [blame] | 2117 | |
Ville Syrjälä | e404ba8d | 2015-08-17 18:46:20 +0300 | [diff] [blame] | 2118 | } else if (INTEL_INFO(dev_priv)->gen < 9) { |
Ander Conselvan de Oliveira | c856052 | 2016-09-01 15:08:07 -0700 | [diff] [blame] | 2119 | I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); |
Satheeshakrishna M | efa80ad | 2014-11-13 14:55:19 +0000 | [diff] [blame] | 2120 | } |
Ville Syrjälä | e404ba8d | 2015-08-17 18:46:20 +0300 | [diff] [blame] | 2121 | } |
| 2122 | |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2123 | static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, |
| 2124 | int link_rate, uint32_t lane_count, |
| 2125 | struct intel_shared_dpll *pll, |
| 2126 | bool link_mst) |
| 2127 | { |
| 2128 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2129 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 2130 | enum port port = intel_ddi_get_encoder_port(encoder); |
Ander Conselvan de Oliveira | 62b6956 | 2017-02-24 16:19:59 +0200 | [diff] [blame] | 2131 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2132 | |
Ander Conselvan de Oliveira | e081c84 | 2017-03-02 14:58:57 +0200 | [diff] [blame] | 2133 | WARN_ON(link_mst && (port == PORT_A || port == PORT_E)); |
| 2134 | |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2135 | intel_dp_set_link_params(intel_dp, link_rate, lane_count, |
| 2136 | link_mst); |
| 2137 | if (encoder->type == INTEL_OUTPUT_EDP) |
| 2138 | intel_edp_panel_on(intel_dp); |
| 2139 | |
| 2140 | intel_ddi_clk_select(encoder, pll); |
Ander Conselvan de Oliveira | 62b6956 | 2017-02-24 16:19:59 +0200 | [diff] [blame] | 2141 | |
| 2142 | intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); |
| 2143 | |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2144 | intel_prepare_dp_ddi_buffers(encoder); |
| 2145 | intel_ddi_init_dp_buf_reg(encoder); |
| 2146 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 2147 | intel_dp_start_link_train(intel_dp); |
| 2148 | if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) |
| 2149 | intel_dp_stop_link_train(intel_dp); |
| 2150 | } |
| 2151 | |
| 2152 | static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, |
Ville Syrjälä | b47ef0f | 2017-08-18 16:49:52 +0300 | [diff] [blame] | 2153 | bool has_infoframe, |
Maarten Lankhorst | ac24028 | 2016-11-23 15:57:00 +0100 | [diff] [blame] | 2154 | const struct intel_crtc_state *crtc_state, |
| 2155 | const struct drm_connector_state *conn_state, |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2156 | struct intel_shared_dpll *pll) |
| 2157 | { |
Ville Syrjälä | f99be1b | 2017-08-18 16:49:54 +0300 | [diff] [blame] | 2158 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
| 2159 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2160 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2161 | enum port port = intel_ddi_get_encoder_port(encoder); |
| 2162 | int level = intel_ddi_hdmi_level(dev_priv, port); |
Ander Conselvan de Oliveira | 62b6956 | 2017-02-24 16:19:59 +0200 | [diff] [blame] | 2163 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2164 | |
| 2165 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
| 2166 | intel_ddi_clk_select(encoder, pll); |
Ander Conselvan de Oliveira | 62b6956 | 2017-02-24 16:19:59 +0200 | [diff] [blame] | 2167 | |
| 2168 | intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); |
| 2169 | |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2170 | intel_prepare_hdmi_ddi_buffers(encoder); |
Rodrigo Vivi | b976dc5 | 2017-01-23 10:32:37 -0800 | [diff] [blame] | 2171 | if (IS_GEN9_BC(dev_priv)) |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2172 | skl_ddi_set_iboost(encoder, level); |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 2173 | else if (IS_GEN9_LP(dev_priv)) |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2174 | bxt_ddi_vswing_sequence(dev_priv, level, port, |
| 2175 | INTEL_OUTPUT_HDMI); |
Rodrigo Vivi | cf54ca8 | 2017-06-09 15:26:08 -0700 | [diff] [blame] | 2176 | else if (IS_CANNONLAKE(dev_priv)) |
Clint Taylor | 0091abc | 2017-06-09 15:26:09 -0700 | [diff] [blame] | 2177 | cnl_ddi_vswing_sequence(encoder, level); |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2178 | |
Ville Syrjälä | f99be1b | 2017-08-18 16:49:54 +0300 | [diff] [blame] | 2179 | intel_dig_port->set_infoframes(&encoder->base, |
| 2180 | has_infoframe, |
| 2181 | crtc_state, conn_state); |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2182 | } |
| 2183 | |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 2184 | static void intel_ddi_pre_enable(struct intel_encoder *encoder, |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2185 | struct intel_crtc_state *pipe_config, |
| 2186 | struct drm_connector_state *conn_state) |
Ville Syrjälä | e404ba8d | 2015-08-17 18:46:20 +0300 | [diff] [blame] | 2187 | { |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 2188 | int type = encoder->type; |
Ville Syrjälä | 6a7e4f9 | 2015-12-08 19:59:44 +0200 | [diff] [blame] | 2189 | |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 2190 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 2191 | intel_ddi_pre_enable_dp(encoder, |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 2192 | pipe_config->port_clock, |
| 2193 | pipe_config->lane_count, |
| 2194 | pipe_config->shared_dpll, |
| 2195 | intel_crtc_has_type(pipe_config, |
Manasi Navare | ba88d15 | 2016-09-01 15:08:08 -0700 | [diff] [blame] | 2196 | INTEL_OUTPUT_DP_MST)); |
| 2197 | } |
| 2198 | if (type == INTEL_OUTPUT_HDMI) { |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 2199 | intel_ddi_pre_enable_hdmi(encoder, |
Ville Syrjälä | b47ef0f | 2017-08-18 16:49:52 +0300 | [diff] [blame] | 2200 | pipe_config->has_infoframe, |
Maarten Lankhorst | ac24028 | 2016-11-23 15:57:00 +0100 | [diff] [blame] | 2201 | pipe_config, conn_state, |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 2202 | pipe_config->shared_dpll); |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2203 | } |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 2204 | } |
| 2205 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2206 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, |
| 2207 | struct intel_crtc_state *old_crtc_state, |
| 2208 | struct drm_connector_state *old_conn_state) |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 2209 | { |
| 2210 | struct drm_encoder *encoder = &intel_encoder->base; |
Tvrtko Ursulin | 6647847 | 2016-11-16 08:55:40 +0000 | [diff] [blame] | 2211 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 2212 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
Ander Conselvan de Oliveira | 62b6956 | 2017-02-24 16:19:59 +0200 | [diff] [blame] | 2213 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
Paulo Zanoni | 82a4d9c | 2012-10-23 18:30:07 -0200 | [diff] [blame] | 2214 | int type = intel_encoder->type; |
Paulo Zanoni | 2886e93 | 2012-10-05 12:06:00 -0300 | [diff] [blame] | 2215 | uint32_t val; |
Paulo Zanoni | a836bdf | 2012-10-15 15:51:32 -0300 | [diff] [blame] | 2216 | bool wait = false; |
Paulo Zanoni | 2886e93 | 2012-10-05 12:06:00 -0300 | [diff] [blame] | 2217 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2218 | /* old_crtc_state and old_conn_state are NULL when called from DP_MST */ |
| 2219 | |
Imre Deak | 7618138 | 2017-05-31 20:05:35 +0300 | [diff] [blame] | 2220 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { |
Ville Syrjälä | c5f93fc | 2017-08-22 17:09:14 +0300 | [diff] [blame] | 2221 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2222 | |
Imre Deak | 7618138 | 2017-05-31 20:05:35 +0300 | [diff] [blame] | 2223 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
| 2224 | } |
| 2225 | |
Paulo Zanoni | 2886e93 | 2012-10-05 12:06:00 -0300 | [diff] [blame] | 2226 | val = I915_READ(DDI_BUF_CTL(port)); |
| 2227 | if (val & DDI_BUF_CTL_ENABLE) { |
| 2228 | val &= ~DDI_BUF_CTL_ENABLE; |
| 2229 | I915_WRITE(DDI_BUF_CTL(port), val); |
Paulo Zanoni | a836bdf | 2012-10-15 15:51:32 -0300 | [diff] [blame] | 2230 | wait = true; |
Paulo Zanoni | 2886e93 | 2012-10-05 12:06:00 -0300 | [diff] [blame] | 2231 | } |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 2232 | |
Paulo Zanoni | a836bdf | 2012-10-15 15:51:32 -0300 | [diff] [blame] | 2233 | val = I915_READ(DP_TP_CTL(port)); |
| 2234 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
| 2235 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2236 | I915_WRITE(DP_TP_CTL(port), val); |
| 2237 | |
| 2238 | if (wait) |
| 2239 | intel_wait_ddi_buf_idle(dev_priv, port); |
| 2240 | |
Ville Syrjälä | c5f93fc | 2017-08-22 17:09:14 +0300 | [diff] [blame] | 2241 | if (type == INTEL_OUTPUT_HDMI) { |
Ville Syrjälä | f99be1b | 2017-08-18 16:49:54 +0300 | [diff] [blame] | 2242 | dig_port->set_infoframes(encoder, false, |
| 2243 | old_crtc_state, old_conn_state); |
Ville Syrjälä | c5f93fc | 2017-08-22 17:09:14 +0300 | [diff] [blame] | 2244 | } |
| 2245 | |
| 2246 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { |
| 2247 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2248 | |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 2249 | intel_edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2250 | intel_edp_panel_off(intel_dp); |
Paulo Zanoni | 82a4d9c | 2012-10-23 18:30:07 -0200 | [diff] [blame] | 2251 | } |
| 2252 | |
Ander Conselvan de Oliveira | 62b6956 | 2017-02-24 16:19:59 +0200 | [diff] [blame] | 2253 | if (dig_port) |
| 2254 | intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain); |
| 2255 | |
Rodrigo Vivi | 555e38d | 2017-06-09 15:26:02 -0700 | [diff] [blame] | 2256 | if (IS_CANNONLAKE(dev_priv)) |
| 2257 | I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | |
| 2258 | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); |
| 2259 | else if (IS_GEN9_BC(dev_priv)) |
Satheeshakrishna M | efa80ad | 2014-11-13 14:55:19 +0000 | [diff] [blame] | 2260 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
| 2261 | DPLL_CTRL2_DDI_CLK_OFF(port))); |
Tvrtko Ursulin | 6647847 | 2016-11-16 08:55:40 +0000 | [diff] [blame] | 2262 | else if (INTEL_GEN(dev_priv) < 9) |
Satheeshakrishna M | efa80ad | 2014-11-13 14:55:19 +0000 | [diff] [blame] | 2263 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
Ville Syrjälä | b2ccb82 | 2016-05-02 22:08:24 +0300 | [diff] [blame] | 2264 | |
| 2265 | if (type == INTEL_OUTPUT_HDMI) { |
| 2266 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 2267 | |
| 2268 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); |
| 2269 | } |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 2270 | } |
| 2271 | |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 2272 | void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, |
Maarten Lankhorst | b707654 | 2016-08-23 16:18:08 +0200 | [diff] [blame] | 2273 | struct intel_crtc_state *old_crtc_state, |
| 2274 | struct drm_connector_state *old_conn_state) |
| 2275 | { |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 2276 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Maarten Lankhorst | b707654 | 2016-08-23 16:18:08 +0200 | [diff] [blame] | 2277 | uint32_t val; |
| 2278 | |
| 2279 | /* |
| 2280 | * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) |
| 2281 | * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, |
| 2282 | * step 13 is the correct place for it. Step 18 is where it was |
| 2283 | * originally before the BUN. |
| 2284 | */ |
| 2285 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
| 2286 | val &= ~FDI_RX_ENABLE; |
| 2287 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
| 2288 | |
Shashank Sharma | 1524e93 | 2017-03-09 19:13:41 +0530 | [diff] [blame] | 2289 | intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state); |
Maarten Lankhorst | b707654 | 2016-08-23 16:18:08 +0200 | [diff] [blame] | 2290 | |
| 2291 | val = I915_READ(FDI_RX_MISC(PIPE_A)); |
| 2292 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
| 2293 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); |
| 2294 | I915_WRITE(FDI_RX_MISC(PIPE_A), val); |
| 2295 | |
| 2296 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
| 2297 | val &= ~FDI_PCDCLK; |
| 2298 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
| 2299 | |
| 2300 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
| 2301 | val &= ~FDI_RX_PLL_ENABLE; |
| 2302 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
| 2303 | } |
| 2304 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2305 | static void intel_enable_ddi(struct intel_encoder *intel_encoder, |
| 2306 | struct intel_crtc_state *pipe_config, |
| 2307 | struct drm_connector_state *conn_state) |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 2308 | { |
Paulo Zanoni | 6547fef | 2012-10-15 15:51:40 -0300 | [diff] [blame] | 2309 | struct drm_encoder *encoder = &intel_encoder->base; |
Tvrtko Ursulin | 6647847 | 2016-11-16 08:55:40 +0000 | [diff] [blame] | 2310 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
Paulo Zanoni | 6547fef | 2012-10-15 15:51:40 -0300 | [diff] [blame] | 2311 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
| 2312 | int type = intel_encoder->type; |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 2313 | |
Paulo Zanoni | 6547fef | 2012-10-15 15:51:40 -0300 | [diff] [blame] | 2314 | if (type == INTEL_OUTPUT_HDMI) { |
Damien Lespiau | 876a8cd | 2012-12-11 18:48:30 +0000 | [diff] [blame] | 2315 | struct intel_digital_port *intel_dig_port = |
| 2316 | enc_to_dig_port(encoder); |
Shashank Sharma | 1595363 | 2017-03-13 16:54:03 +0530 | [diff] [blame] | 2317 | bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio; |
| 2318 | bool scrambling = pipe_config->hdmi_scrambling; |
| 2319 | |
| 2320 | intel_hdmi_handle_sink_scrambling(intel_encoder, |
| 2321 | conn_state->connector, |
| 2322 | clock_ratio, scrambling); |
Damien Lespiau | 876a8cd | 2012-12-11 18:48:30 +0000 | [diff] [blame] | 2323 | |
Paulo Zanoni | 6547fef | 2012-10-15 15:51:40 -0300 | [diff] [blame] | 2324 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
| 2325 | * are ignored so nothing special needs to be done besides |
| 2326 | * enabling the port. |
| 2327 | */ |
Damien Lespiau | 876a8cd | 2012-12-11 18:48:30 +0000 | [diff] [blame] | 2328 | I915_WRITE(DDI_BUF_CTL(port), |
Stéphane Marchesin | bcf53de | 2013-07-12 13:54:41 -0700 | [diff] [blame] | 2329 | intel_dig_port->saved_port_bits | |
| 2330 | DDI_BUF_CTL_ENABLE); |
Paulo Zanoni | d6c50ff | 2012-10-23 18:30:06 -0200 | [diff] [blame] | 2331 | } else if (type == INTEL_OUTPUT_EDP) { |
| 2332 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2333 | |
Tvrtko Ursulin | 6647847 | 2016-11-16 08:55:40 +0000 | [diff] [blame] | 2334 | if (port == PORT_A && INTEL_GEN(dev_priv) < 9) |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2335 | intel_dp_stop_link_train(intel_dp); |
| 2336 | |
Maarten Lankhorst | b037d58 | 2017-06-12 12:21:13 +0200 | [diff] [blame] | 2337 | intel_edp_backlight_on(pipe_config, conn_state); |
Rodrigo Vivi | 0bc12bc | 2014-11-14 08:52:28 -0800 | [diff] [blame] | 2338 | intel_psr_enable(intel_dp); |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2339 | intel_edp_drrs_enable(intel_dp, pipe_config); |
Paulo Zanoni | 6547fef | 2012-10-15 15:51:40 -0300 | [diff] [blame] | 2340 | } |
Wang Xingchao | 7b9f35a | 2013-01-22 23:25:25 +0800 | [diff] [blame] | 2341 | |
Maarten Lankhorst | 37255d8 | 2016-12-15 15:29:43 +0100 | [diff] [blame] | 2342 | if (pipe_config->has_audio) |
Maarten Lankhorst | bbf35e9 | 2016-11-08 13:55:38 +0100 | [diff] [blame] | 2343 | intel_audio_codec_enable(intel_encoder, pipe_config, conn_state); |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 2344 | } |
| 2345 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2346 | static void intel_disable_ddi(struct intel_encoder *intel_encoder, |
| 2347 | struct intel_crtc_state *old_crtc_state, |
| 2348 | struct drm_connector_state *old_conn_state) |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 2349 | { |
Paulo Zanoni | d6c50ff | 2012-10-23 18:30:06 -0200 | [diff] [blame] | 2350 | struct drm_encoder *encoder = &intel_encoder->base; |
| 2351 | int type = intel_encoder->type; |
| 2352 | |
Maarten Lankhorst | 37255d8 | 2016-12-15 15:29:43 +0100 | [diff] [blame] | 2353 | if (old_crtc_state->has_audio) |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 2354 | intel_audio_codec_disable(intel_encoder); |
Paulo Zanoni | 2831d842 | 2013-03-06 20:03:09 -0300 | [diff] [blame] | 2355 | |
Shashank Sharma | 1595363 | 2017-03-13 16:54:03 +0530 | [diff] [blame] | 2356 | if (type == INTEL_OUTPUT_HDMI) { |
| 2357 | intel_hdmi_handle_sink_scrambling(intel_encoder, |
| 2358 | old_conn_state->connector, |
| 2359 | false, false); |
| 2360 | } |
| 2361 | |
Paulo Zanoni | d6c50ff | 2012-10-23 18:30:06 -0200 | [diff] [blame] | 2362 | if (type == INTEL_OUTPUT_EDP) { |
| 2363 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2364 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2365 | intel_edp_drrs_disable(intel_dp, old_crtc_state); |
Rodrigo Vivi | 0bc12bc | 2014-11-14 08:52:28 -0800 | [diff] [blame] | 2366 | intel_psr_disable(intel_dp); |
Maarten Lankhorst | b037d58 | 2017-06-12 12:21:13 +0200 | [diff] [blame] | 2367 | intel_edp_backlight_off(old_conn_state); |
Paulo Zanoni | d6c50ff | 2012-10-23 18:30:06 -0200 | [diff] [blame] | 2368 | } |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 2369 | } |
Paulo Zanoni | 79f689a | 2012-10-05 12:05:52 -0300 | [diff] [blame] | 2370 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2371 | static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder, |
| 2372 | struct intel_crtc_state *pipe_config, |
| 2373 | struct drm_connector_state *conn_state) |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2374 | { |
Ander Conselvan de Oliveira | 3dc38ee | 2017-03-02 14:58:56 +0200 | [diff] [blame] | 2375 | uint8_t mask = pipe_config->lane_lat_optim_mask; |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2376 | |
Ander Conselvan de Oliveira | 47a6bc6 | 2016-10-06 19:22:17 +0300 | [diff] [blame] | 2377 | bxt_ddi_phy_set_lane_optim_mask(encoder, mask); |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2378 | } |
| 2379 | |
Ander Conselvan de Oliveira | ad64217 | 2015-10-23 13:01:49 +0300 | [diff] [blame] | 2380 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2381 | { |
Ander Conselvan de Oliveira | ad64217 | 2015-10-23 13:01:49 +0300 | [diff] [blame] | 2382 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2383 | struct drm_i915_private *dev_priv = |
| 2384 | to_i915(intel_dig_port->base.base.dev); |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 2385 | enum port port = intel_dig_port->port; |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2386 | uint32_t val; |
Syam Sidhardhan | f3e227d | 2013-02-25 04:05:38 +0530 | [diff] [blame] | 2387 | bool wait = false; |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2388 | |
| 2389 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { |
| 2390 | val = I915_READ(DDI_BUF_CTL(port)); |
| 2391 | if (val & DDI_BUF_CTL_ENABLE) { |
| 2392 | val &= ~DDI_BUF_CTL_ENABLE; |
| 2393 | I915_WRITE(DDI_BUF_CTL(port), val); |
| 2394 | wait = true; |
| 2395 | } |
| 2396 | |
| 2397 | val = I915_READ(DP_TP_CTL(port)); |
| 2398 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
| 2399 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2400 | I915_WRITE(DP_TP_CTL(port), val); |
| 2401 | POSTING_READ(DP_TP_CTL(port)); |
| 2402 | |
| 2403 | if (wait) |
| 2404 | intel_wait_ddi_buf_idle(dev_priv, port); |
| 2405 | } |
| 2406 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 2407 | val = DP_TP_CTL_ENABLE | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2408 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
Ville Syrjälä | 64ee2fd | 2016-07-28 17:50:39 +0300 | [diff] [blame] | 2409 | if (intel_dp->link_mst) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 2410 | val |= DP_TP_CTL_MODE_MST; |
| 2411 | else { |
| 2412 | val |= DP_TP_CTL_MODE_SST; |
| 2413 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 2414 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
| 2415 | } |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2416 | I915_WRITE(DP_TP_CTL(port), val); |
| 2417 | POSTING_READ(DP_TP_CTL(port)); |
| 2418 | |
| 2419 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; |
| 2420 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); |
| 2421 | POSTING_READ(DDI_BUF_CTL(port)); |
| 2422 | |
| 2423 | udelay(600); |
| 2424 | } |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2425 | |
Libin Yang | 9935f7f | 2016-11-28 20:07:06 +0800 | [diff] [blame] | 2426 | bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, |
| 2427 | struct intel_crtc *intel_crtc) |
| 2428 | { |
| 2429 | u32 temp; |
| 2430 | |
| 2431 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
| 2432 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
| 2433 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) |
| 2434 | return true; |
| 2435 | } |
| 2436 | return false; |
| 2437 | } |
| 2438 | |
Ville Syrjälä | 6801c18 | 2013-09-24 14:24:05 +0300 | [diff] [blame] | 2439 | void intel_ddi_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 2440 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2441 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2442 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2443 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
Ander Conselvan de Oliveira | 0cb09a9 | 2015-01-30 12:17:23 +0200 | [diff] [blame] | 2444 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
Ville Syrjälä | f99be1b | 2017-08-18 16:49:54 +0300 | [diff] [blame] | 2445 | struct intel_digital_port *intel_dig_port; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2446 | u32 temp, flags = 0; |
| 2447 | |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 2448 | /* XXX: DSI transcoder paranoia */ |
| 2449 | if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) |
| 2450 | return; |
| 2451 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2452 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
| 2453 | if (temp & TRANS_DDI_PHSYNC) |
| 2454 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2455 | else |
| 2456 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 2457 | if (temp & TRANS_DDI_PVSYNC) |
| 2458 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2459 | else |
| 2460 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 2461 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 2462 | pipe_config->base.adjusted_mode.flags |= flags; |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 2463 | |
| 2464 | switch (temp & TRANS_DDI_BPC_MASK) { |
| 2465 | case TRANS_DDI_BPC_6: |
| 2466 | pipe_config->pipe_bpp = 18; |
| 2467 | break; |
| 2468 | case TRANS_DDI_BPC_8: |
| 2469 | pipe_config->pipe_bpp = 24; |
| 2470 | break; |
| 2471 | case TRANS_DDI_BPC_10: |
| 2472 | pipe_config->pipe_bpp = 30; |
| 2473 | break; |
| 2474 | case TRANS_DDI_BPC_12: |
| 2475 | pipe_config->pipe_bpp = 36; |
| 2476 | break; |
| 2477 | default: |
| 2478 | break; |
| 2479 | } |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2480 | |
| 2481 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { |
| 2482 | case TRANS_DDI_MODE_SELECT_HDMI: |
Daniel Vetter | 6897b4b | 2014-04-24 23:54:47 +0200 | [diff] [blame] | 2483 | pipe_config->has_hdmi_sink = true; |
Ville Syrjälä | f99be1b | 2017-08-18 16:49:54 +0300 | [diff] [blame] | 2484 | intel_dig_port = enc_to_dig_port(&encoder->base); |
Daniel Vetter | bbd440f | 2014-11-20 22:33:59 +0100 | [diff] [blame] | 2485 | |
Ville Syrjälä | f99be1b | 2017-08-18 16:49:54 +0300 | [diff] [blame] | 2486 | if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) |
Daniel Vetter | bbd440f | 2014-11-20 22:33:59 +0100 | [diff] [blame] | 2487 | pipe_config->has_infoframe = true; |
Shashank Sharma | 1595363 | 2017-03-13 16:54:03 +0530 | [diff] [blame] | 2488 | |
| 2489 | if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) == |
| 2490 | TRANS_DDI_HDMI_SCRAMBLING_MASK) |
| 2491 | pipe_config->hdmi_scrambling = true; |
| 2492 | if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) |
| 2493 | pipe_config->hdmi_high_tmds_clock_ratio = true; |
Ander Conselvan de Oliveira | d4d6279 | 2016-04-27 15:44:16 +0300 | [diff] [blame] | 2494 | /* fall through */ |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2495 | case TRANS_DDI_MODE_SELECT_DVI: |
Ander Conselvan de Oliveira | d4d6279 | 2016-04-27 15:44:16 +0300 | [diff] [blame] | 2496 | pipe_config->lane_count = 4; |
| 2497 | break; |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2498 | case TRANS_DDI_MODE_SELECT_FDI: |
| 2499 | break; |
| 2500 | case TRANS_DDI_MODE_SELECT_DP_SST: |
| 2501 | case TRANS_DDI_MODE_SELECT_DP_MST: |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 2502 | pipe_config->lane_count = |
| 2503 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2504 | intel_dp_get_m_n(intel_crtc, pipe_config); |
| 2505 | break; |
| 2506 | default: |
| 2507 | break; |
| 2508 | } |
Daniel Vetter | 1021442 | 2013-11-18 07:38:16 +0100 | [diff] [blame] | 2509 | |
Libin Yang | 9935f7f | 2016-11-28 20:07:06 +0800 | [diff] [blame] | 2510 | pipe_config->has_audio = |
| 2511 | intel_ddi_is_audio_enabled(dev_priv, intel_crtc); |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 2512 | |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 2513 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && |
| 2514 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
Daniel Vetter | 1021442 | 2013-11-18 07:38:16 +0100 | [diff] [blame] | 2515 | /* |
| 2516 | * This is a big fat ugly hack. |
| 2517 | * |
| 2518 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 2519 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 2520 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 2521 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 2522 | * max, not what it tells us to use. |
| 2523 | * |
| 2524 | * Note: This will still be broken if the eDP panel is not lit |
| 2525 | * up by the BIOS, and thus we can't get the mode at module |
| 2526 | * load. |
| 2527 | */ |
| 2528 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 2529 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
| 2530 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; |
Daniel Vetter | 1021442 | 2013-11-18 07:38:16 +0100 | [diff] [blame] | 2531 | } |
Jesse Barnes | 1157855 | 2014-01-21 12:42:10 -0800 | [diff] [blame] | 2532 | |
Damien Lespiau | 22606a1 | 2014-12-12 14:26:57 +0000 | [diff] [blame] | 2533 | intel_ddi_clock_get(encoder, pipe_config); |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2534 | |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 2535 | if (IS_GEN9_LP(dev_priv)) |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2536 | pipe_config->lane_lat_optim_mask = |
| 2537 | bxt_ddi_phy_get_lane_lat_optim_mask(encoder); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2538 | } |
| 2539 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 2540 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
Maarten Lankhorst | 0a478c2 | 2016-08-09 17:04:05 +0200 | [diff] [blame] | 2541 | struct intel_crtc_state *pipe_config, |
| 2542 | struct drm_connector_state *conn_state) |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2543 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2544 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 2545 | int type = encoder->type; |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 2546 | int port = intel_ddi_get_encoder_port(encoder); |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2547 | int ret; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2548 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 2549 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2550 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 2551 | if (port == PORT_A) |
| 2552 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
| 2553 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2554 | if (type == INTEL_OUTPUT_HDMI) |
Maarten Lankhorst | 0a478c2 | 2016-08-09 17:04:05 +0200 | [diff] [blame] | 2555 | ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2556 | else |
Maarten Lankhorst | 0a478c2 | 2016-08-09 17:04:05 +0200 | [diff] [blame] | 2557 | ret = intel_dp_compute_config(encoder, pipe_config, conn_state); |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2558 | |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 2559 | if (IS_GEN9_LP(dev_priv) && ret) |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2560 | pipe_config->lane_lat_optim_mask = |
| 2561 | bxt_ddi_phy_calc_lane_lat_optim_mask(encoder, |
Ander Conselvan de Oliveira | b284eed | 2016-10-06 19:22:16 +0300 | [diff] [blame] | 2562 | pipe_config->lane_count); |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2563 | |
| 2564 | return ret; |
| 2565 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2566 | } |
| 2567 | |
| 2568 | static const struct drm_encoder_funcs intel_ddi_funcs = { |
Imre Deak | bf93ba6 | 2016-04-18 10:04:21 +0300 | [diff] [blame] | 2569 | .reset = intel_dp_encoder_reset, |
| 2570 | .destroy = intel_dp_encoder_destroy, |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2571 | }; |
| 2572 | |
Paulo Zanoni | 4a28ae5 | 2013-10-09 13:52:36 -0300 | [diff] [blame] | 2573 | static struct intel_connector * |
| 2574 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) |
| 2575 | { |
| 2576 | struct intel_connector *connector; |
| 2577 | enum port port = intel_dig_port->port; |
| 2578 | |
Ander Conselvan de Oliveira | 9bdbd0b | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 2579 | connector = intel_connector_alloc(); |
Paulo Zanoni | 4a28ae5 | 2013-10-09 13:52:36 -0300 | [diff] [blame] | 2580 | if (!connector) |
| 2581 | return NULL; |
| 2582 | |
| 2583 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |
| 2584 | if (!intel_dp_init_connector(intel_dig_port, connector)) { |
| 2585 | kfree(connector); |
| 2586 | return NULL; |
| 2587 | } |
| 2588 | |
| 2589 | return connector; |
| 2590 | } |
| 2591 | |
| 2592 | static struct intel_connector * |
| 2593 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) |
| 2594 | { |
| 2595 | struct intel_connector *connector; |
| 2596 | enum port port = intel_dig_port->port; |
| 2597 | |
Ander Conselvan de Oliveira | 9bdbd0b | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 2598 | connector = intel_connector_alloc(); |
Paulo Zanoni | 4a28ae5 | 2013-10-09 13:52:36 -0300 | [diff] [blame] | 2599 | if (!connector) |
| 2600 | return NULL; |
| 2601 | |
| 2602 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); |
| 2603 | intel_hdmi_init_connector(intel_dig_port, connector); |
| 2604 | |
| 2605 | return connector; |
| 2606 | } |
| 2607 | |
Ander Conselvan de Oliveira | c39055b | 2016-11-23 16:21:44 +0200 | [diff] [blame] | 2608 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2609 | { |
| 2610 | struct intel_digital_port *intel_dig_port; |
| 2611 | struct intel_encoder *intel_encoder; |
| 2612 | struct drm_encoder *encoder; |
Shashank Sharma | ff66212 | 2016-10-14 19:56:51 +0530 | [diff] [blame] | 2613 | bool init_hdmi, init_dp, init_lspcon = false; |
Ville Syrjälä | 10e7bec | 2015-12-08 19:59:37 +0200 | [diff] [blame] | 2614 | int max_lanes; |
| 2615 | |
| 2616 | if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { |
| 2617 | switch (port) { |
| 2618 | case PORT_A: |
| 2619 | max_lanes = 4; |
| 2620 | break; |
| 2621 | case PORT_E: |
| 2622 | max_lanes = 0; |
| 2623 | break; |
| 2624 | default: |
| 2625 | max_lanes = 4; |
| 2626 | break; |
| 2627 | } |
| 2628 | } else { |
| 2629 | switch (port) { |
| 2630 | case PORT_A: |
| 2631 | max_lanes = 2; |
| 2632 | break; |
| 2633 | case PORT_E: |
| 2634 | max_lanes = 2; |
| 2635 | break; |
| 2636 | default: |
| 2637 | max_lanes = 4; |
| 2638 | break; |
| 2639 | } |
| 2640 | } |
Paulo Zanoni | 311a209 | 2013-09-12 17:12:18 -0300 | [diff] [blame] | 2641 | |
| 2642 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || |
| 2643 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); |
| 2644 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; |
Shashank Sharma | ff66212 | 2016-10-14 19:56:51 +0530 | [diff] [blame] | 2645 | |
| 2646 | if (intel_bios_is_lspcon_present(dev_priv, port)) { |
| 2647 | /* |
| 2648 | * Lspcon device needs to be driven with DP connector |
| 2649 | * with special detection sequence. So make sure DP |
| 2650 | * is initialized before lspcon. |
| 2651 | */ |
| 2652 | init_dp = true; |
| 2653 | init_lspcon = true; |
| 2654 | init_hdmi = false; |
| 2655 | DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); |
| 2656 | } |
| 2657 | |
Paulo Zanoni | 311a209 | 2013-09-12 17:12:18 -0300 | [diff] [blame] | 2658 | if (!init_dp && !init_hdmi) { |
Rodrigo Vivi | 500ea70 | 2015-08-07 17:01:16 -0700 | [diff] [blame] | 2659 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", |
Paulo Zanoni | 311a209 | 2013-09-12 17:12:18 -0300 | [diff] [blame] | 2660 | port_name(port)); |
Rodrigo Vivi | 500ea70 | 2015-08-07 17:01:16 -0700 | [diff] [blame] | 2661 | return; |
Paulo Zanoni | 311a209 | 2013-09-12 17:12:18 -0300 | [diff] [blame] | 2662 | } |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2663 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 2664 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2665 | if (!intel_dig_port) |
| 2666 | return; |
| 2667 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2668 | intel_encoder = &intel_dig_port->base; |
| 2669 | encoder = &intel_encoder->base; |
| 2670 | |
Ander Conselvan de Oliveira | c39055b | 2016-11-23 16:21:44 +0200 | [diff] [blame] | 2671 | drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, |
Ville Syrjälä | 580d8ed | 2016-05-27 20:59:24 +0300 | [diff] [blame] | 2672 | DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2673 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 2674 | intel_encoder->compute_config = intel_ddi_compute_config; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2675 | intel_encoder->enable = intel_enable_ddi; |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 2676 | if (IS_GEN9_LP(dev_priv)) |
Imre Deak | 95a7a2a | 2016-06-13 16:44:35 +0300 | [diff] [blame] | 2677 | intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2678 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
| 2679 | intel_encoder->disable = intel_disable_ddi; |
| 2680 | intel_encoder->post_disable = intel_ddi_post_disable; |
| 2681 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2682 | intel_encoder->get_config = intel_ddi_get_config; |
Imre Deak | bf93ba6 | 2016-04-18 10:04:21 +0300 | [diff] [blame] | 2683 | intel_encoder->suspend = intel_dp_encoder_suspend; |
Ander Conselvan de Oliveira | 62b6956 | 2017-02-24 16:19:59 +0200 | [diff] [blame] | 2684 | intel_encoder->get_power_domains = intel_ddi_get_power_domains; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2685 | |
| 2686 | intel_dig_port->port = port; |
Stéphane Marchesin | bcf53de | 2013-07-12 13:54:41 -0700 | [diff] [blame] | 2687 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
| 2688 | (DDI_BUF_PORT_REVERSAL | |
| 2689 | DDI_A_4_LANES); |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2690 | |
Ander Conselvan de Oliveira | 62b6956 | 2017-02-24 16:19:59 +0200 | [diff] [blame] | 2691 | switch (port) { |
| 2692 | case PORT_A: |
| 2693 | intel_dig_port->ddi_io_power_domain = |
| 2694 | POWER_DOMAIN_PORT_DDI_A_IO; |
| 2695 | break; |
| 2696 | case PORT_B: |
| 2697 | intel_dig_port->ddi_io_power_domain = |
| 2698 | POWER_DOMAIN_PORT_DDI_B_IO; |
| 2699 | break; |
| 2700 | case PORT_C: |
| 2701 | intel_dig_port->ddi_io_power_domain = |
| 2702 | POWER_DOMAIN_PORT_DDI_C_IO; |
| 2703 | break; |
| 2704 | case PORT_D: |
| 2705 | intel_dig_port->ddi_io_power_domain = |
| 2706 | POWER_DOMAIN_PORT_DDI_D_IO; |
| 2707 | break; |
| 2708 | case PORT_E: |
| 2709 | intel_dig_port->ddi_io_power_domain = |
| 2710 | POWER_DOMAIN_PORT_DDI_E_IO; |
| 2711 | break; |
| 2712 | default: |
| 2713 | MISSING_CASE(port); |
| 2714 | } |
| 2715 | |
Matt Roper | 6c566dc | 2015-11-05 14:53:32 -0800 | [diff] [blame] | 2716 | /* |
| 2717 | * Bspec says that DDI_A_4_LANES is the only supported configuration |
| 2718 | * for Broxton. Yet some BIOS fail to set this bit on port A if eDP |
| 2719 | * wasn't lit up at boot. Force this bit on in our internal |
| 2720 | * configuration so that we use the proper lane count for our |
| 2721 | * calculations. |
| 2722 | */ |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 2723 | if (IS_GEN9_LP(dev_priv) && port == PORT_A) { |
Matt Roper | 6c566dc | 2015-11-05 14:53:32 -0800 | [diff] [blame] | 2724 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { |
| 2725 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); |
| 2726 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; |
Matt Roper | ed8d60f | 2016-01-28 15:09:37 -0800 | [diff] [blame] | 2727 | max_lanes = 4; |
Matt Roper | 6c566dc | 2015-11-05 14:53:32 -0800 | [diff] [blame] | 2728 | } |
| 2729 | } |
| 2730 | |
Matt Roper | ed8d60f | 2016-01-28 15:09:37 -0800 | [diff] [blame] | 2731 | intel_dig_port->max_lanes = max_lanes; |
| 2732 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2733 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
Ander Conselvan de Oliveira | 79f255a | 2017-02-22 08:34:27 +0200 | [diff] [blame] | 2734 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
Pandiyan, Dhinakaran | 03cdc1d | 2016-09-19 18:24:38 -0700 | [diff] [blame] | 2735 | intel_encoder->port = port; |
Chris Wilson | f68d697 | 2014-08-04 07:15:09 +0100 | [diff] [blame] | 2736 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 2737 | intel_encoder->cloneable = 0; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2738 | |
Ville Syrjälä | 385e4de | 2017-08-18 16:49:55 +0300 | [diff] [blame^] | 2739 | intel_infoframe_init(intel_dig_port); |
| 2740 | |
Chris Wilson | f68d697 | 2014-08-04 07:15:09 +0100 | [diff] [blame] | 2741 | if (init_dp) { |
| 2742 | if (!intel_ddi_init_dp_connector(intel_dig_port)) |
| 2743 | goto err; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 2744 | |
Chris Wilson | f68d697 | 2014-08-04 07:15:09 +0100 | [diff] [blame] | 2745 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
Ander Conselvan de Oliveira | ca4c389 | 2017-02-03 16:03:13 +0200 | [diff] [blame] | 2746 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
Chris Wilson | f68d697 | 2014-08-04 07:15:09 +0100 | [diff] [blame] | 2747 | } |
Daniel Vetter | 21a8e6a | 2013-04-10 23:28:35 +0200 | [diff] [blame] | 2748 | |
Paulo Zanoni | 311a209 | 2013-09-12 17:12:18 -0300 | [diff] [blame] | 2749 | /* In theory we don't need the encoder->type check, but leave it just in |
| 2750 | * case we have some really bad VBTs... */ |
Chris Wilson | f68d697 | 2014-08-04 07:15:09 +0100 | [diff] [blame] | 2751 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
| 2752 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) |
| 2753 | goto err; |
Daniel Vetter | 21a8e6a | 2013-04-10 23:28:35 +0200 | [diff] [blame] | 2754 | } |
Chris Wilson | f68d697 | 2014-08-04 07:15:09 +0100 | [diff] [blame] | 2755 | |
Shashank Sharma | ff66212 | 2016-10-14 19:56:51 +0530 | [diff] [blame] | 2756 | if (init_lspcon) { |
| 2757 | if (lspcon_init(intel_dig_port)) |
| 2758 | /* TODO: handle hdmi info frame part */ |
| 2759 | DRM_DEBUG_KMS("LSPCON init success on port %c\n", |
| 2760 | port_name(port)); |
| 2761 | else |
| 2762 | /* |
| 2763 | * LSPCON init faied, but DP init was success, so |
| 2764 | * lets try to drive as DP++ port. |
| 2765 | */ |
| 2766 | DRM_ERROR("LSPCON init failed on port %c\n", |
| 2767 | port_name(port)); |
| 2768 | } |
| 2769 | |
Chris Wilson | f68d697 | 2014-08-04 07:15:09 +0100 | [diff] [blame] | 2770 | return; |
| 2771 | |
| 2772 | err: |
| 2773 | drm_encoder_cleanup(encoder); |
| 2774 | kfree(intel_dig_port); |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2775 | } |