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Nicolas Ferre49fe2ba2011-10-10 18:29:24 +02001/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +080012#include "skeleton.dtsi"
Ludovic Desrochesd4ae89c2013-05-30 18:08:22 +020013#include <dt-bindings/dma/at91.h>
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +080014#include <dt-bindings/pinctrl/at91.h>
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080015#include <dt-bindings/interrupt-controller/irq.h>
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +080016#include <dt-bindings/gpio/gpio.h>
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020017
18/ {
19 model = "Atmel AT91SAM9G45 family SoC";
20 compatible = "atmel,at91sam9g45";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
Nicolas Ferre21f81872012-02-11 15:41:40 +010029 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010034 tcb0 = &tcb0;
35 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020036 i2c0 = &i2c0;
37 i2c1 = &i2c1;
Bo Shen099343c2012-11-07 11:41:41 +080038 ssc0 = &ssc0;
39 ssc1 = &ssc1;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020040 };
41 cpus {
42 cpu@0 {
43 compatible = "arm,arm926ejs";
44 };
45 };
46
Ludovic Desrochesdcce6ce2012-04-02 20:44:20 +020047 memory {
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020048 reg = <0x70000000 0x10000000>;
49 };
50
51 ahb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 apb {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020064 #interrupt-cells = <3>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020065 compatible = "atmel,at91rm9200-aic";
66 interrupt-controller;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020067 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080068 atmel,external-irqs = <31>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020069 };
70
Jean-Christophe PLAGNIOL-VILLARDa7776ec2012-03-02 20:54:37 +080071 ramc0: ramc@ffffe400 {
72 compatible = "atmel,at91sam9g45-ddramc";
73 reg = <0xffffe400 0x200
74 0xffffe600 0x200>;
75 };
76
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080077 pmc: pmc@fffffc00 {
78 compatible = "atmel,at91rm9200-pmc";
79 reg = <0xfffffc00 0x100>;
80 };
81
Jean-Christophe PLAGNIOL-VILLARDc8082d32012-03-03 03:16:27 +080082 rstc@fffffd00 {
83 compatible = "atmel,at91sam9g45-rstc";
84 reg = <0xfffffd00 0x10>;
85 };
86
Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +010087 pit: timer@fffffd30 {
88 compatible = "atmel,at91sam9260-pit";
89 reg = <0xfffffd30 0xf>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080090 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +010091 };
92
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010093
Jean-Christophe PLAGNIOL-VILLARD82015c42012-03-02 21:01:00 +080094 shdwc@fffffd10 {
95 compatible = "atmel,at91sam9rl-shdwc";
96 reg = <0xfffffd10 0x10>;
97 };
98
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010099 tcb0: timer@fff7c000 {
100 compatible = "atmel,at91rm9200-tcb";
101 reg = <0xfff7c000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800102 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +0100103 };
104
105 tcb1: timer@fffd4000 {
106 compatible = "atmel,at91rm9200-tcb";
107 reg = <0xfffd4000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800108 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +0100109 };
110
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200111 dma: dma-controller@ffffec00 {
112 compatible = "atmel,at91sam9g45-dma";
113 reg = <0xffffec00 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800114 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desroches980ce7d2013-04-16 15:03:06 +0200115 #dma-cells = <2>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200116 };
117
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800118 pinctrl@fffff200 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
122 ranges = <0xfffff200 0xfffff200 0xa00>;
Nicolas Ferre21f81872012-02-11 15:41:40 +0100123
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800124 atmel,mux-mask = <
125 /* A B */
126 0xffffffff 0xffc003ff /* pioA */
127 0xffffffff 0x800f8f00 /* pioB */
128 0xffffffff 0x00000e00 /* pioC */
129 0xffffffff 0xff0c1381 /* pioD */
130 0xffffffff 0x81ffff81 /* pioE */
131 >;
132
133 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800134 dbgu {
135 pinctrl_dbgu: dbgu-0 {
136 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800137 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
138 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800139 };
140 };
141
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800142 usart0 {
143 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800144 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800145 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
146 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800147 };
148
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800149 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800150 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800151 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800152 };
153
154 pinctrl_usart0_cts: usart0_cts-0 {
155 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800156 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800157 };
158 };
159
160 uart1 {
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800161 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800162 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800163 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
164 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800165 };
166
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800167 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800168 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800169 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800170 };
171
172 pinctrl_usart1_cts: usart1_cts-0 {
173 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800174 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800175 };
176 };
177
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800178 usart2 {
179 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800180 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800181 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
182 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800183 };
184
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800185 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800186 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800187 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800188 };
189
190 pinctrl_usart2_cts: usart2_cts-0 {
191 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800192 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800193 };
194 };
195
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800196 usart3 {
197 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800198 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800199 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
200 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800201 };
202
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800203 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800204 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800205 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800206 };
207
208 pinctrl_usart3_cts: usart3_cts-0 {
209 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800210 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800211 };
212 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800213
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800214 nand {
215 pinctrl_nand: nand-0 {
216 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800217 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
218 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800219 };
220 };
221
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800222 macb {
223 pinctrl_macb_rmii: macb_rmii-0 {
224 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800225 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
226 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
227 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
228 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
229 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
230 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
231 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
232 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
233 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
234 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800235 };
236
237 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
238 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800239 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
240 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
241 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
242 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
243 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
244 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
245 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
246 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800247 };
248 };
249
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800250 mmc0 {
251 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
252 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800253 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
254 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
255 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800256 };
257
258 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
259 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800260 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
261 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
262 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800263 };
264
265 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
266 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800267 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
268 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
269 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
270 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800271 };
272 };
273
274 mmc1 {
275 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
276 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800277 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
278 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
279 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800280 };
281
282 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
283 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800284 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
285 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
286 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800287 };
288
289 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
290 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800291 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
292 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
293 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
294 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800295 };
296 };
297
Bo Shen544ae6b2013-01-11 15:08:30 +0100298 ssc0 {
299 pinctrl_ssc0_tx: ssc0_tx-0 {
300 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800301 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
302 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
303 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100304 };
305
306 pinctrl_ssc0_rx: ssc0_rx-0 {
307 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800308 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
309 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
310 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100311 };
312 };
313
314 ssc1 {
315 pinctrl_ssc1_tx: ssc1_tx-0 {
316 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800317 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
318 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
319 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100320 };
321
322 pinctrl_ssc1_rx: ssc1_rx-0 {
323 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800324 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
325 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
326 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100327 };
328 };
329
Wenyou Yanga68b7282013-04-03 14:03:52 +0800330 spi0 {
331 pinctrl_spi0: spi0-0 {
332 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800333 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
334 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
335 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800336 };
337 };
338
339 spi1 {
340 pinctrl_spi1: spi1-0 {
341 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800342 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
343 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
344 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800345 };
346 };
347
Boris BREZILLON028633c2013-05-24 10:05:56 +0000348 tcb0 {
349 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
350 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
351 };
352
353 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
354 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
355 };
356
357 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
358 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
359 };
360
361 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
362 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
363 };
364
365 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
366 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
367 };
368
369 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
370 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
371 };
372
373 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
374 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
375 };
376
377 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
378 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
379 };
380
381 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
382 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
383 };
384 };
385
386 tcb1 {
387 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
388 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
389 };
390
391 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
392 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
393 };
394
395 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
396 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
397 };
398
399 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
400 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
401 };
402
403 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
404 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
405 };
406
407 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
408 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
409 };
410
411 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
412 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
413 };
414
415 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
416 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
417 };
418
419 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
420 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
421 };
422 };
423
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800424 pioA: gpio@fffff200 {
425 compatible = "atmel,at91rm9200-gpio";
426 reg = <0xfffff200 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800427 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800428 #gpio-cells = <2>;
429 gpio-controller;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100433
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800434 pioB: gpio@fffff400 {
435 compatible = "atmel,at91rm9200-gpio";
436 reg = <0xfffff400 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800437 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800438 #gpio-cells = <2>;
439 gpio-controller;
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100443
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800444 pioC: gpio@fffff600 {
445 compatible = "atmel,at91rm9200-gpio";
446 reg = <0xfffff600 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800447 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800448 #gpio-cells = <2>;
449 gpio-controller;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100453
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800454 pioD: gpio@fffff800 {
455 compatible = "atmel,at91rm9200-gpio";
456 reg = <0xfffff800 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800457 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800458 #gpio-cells = <2>;
459 gpio-controller;
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 };
463
464 pioE: gpio@fffffa00 {
465 compatible = "atmel,at91rm9200-gpio";
466 reg = <0xfffffa00 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800467 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800468 #gpio-cells = <2>;
469 gpio-controller;
470 interrupt-controller;
471 #interrupt-cells = <2>;
472 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100473 };
474
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200475 dbgu: serial@ffffee00 {
476 compatible = "atmel,at91sam9260-usart";
477 reg = <0xffffee00 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800478 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800479 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_dbgu>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200481 status = "disabled";
482 };
483
484 usart0: serial@fff8c000 {
485 compatible = "atmel,at91sam9260-usart";
486 reg = <0xfff8c000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800487 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200488 atmel,use-dma-rx;
489 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800490 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800491 pinctrl-0 = <&pinctrl_usart0>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200492 status = "disabled";
493 };
494
495 usart1: serial@fff90000 {
496 compatible = "atmel,at91sam9260-usart";
497 reg = <0xfff90000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800498 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200499 atmel,use-dma-rx;
500 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800501 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800502 pinctrl-0 = <&pinctrl_usart1>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200503 status = "disabled";
504 };
505
506 usart2: serial@fff94000 {
507 compatible = "atmel,at91sam9260-usart";
508 reg = <0xfff94000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800509 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200510 atmel,use-dma-rx;
511 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800512 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800513 pinctrl-0 = <&pinctrl_usart2>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200514 status = "disabled";
515 };
516
517 usart3: serial@fff98000 {
518 compatible = "atmel,at91sam9260-usart";
519 reg = <0xfff98000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800520 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200521 atmel,use-dma-rx;
522 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800523 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800524 pinctrl-0 = <&pinctrl_usart3>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200525 status = "disabled";
526 };
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +0100527
528 macb0: ethernet@fffbc000 {
529 compatible = "cdns,at32ap7000-macb", "cdns,macb";
530 reg = <0xfffbc000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800531 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_macb_rmii>;
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +0100534 status = "disabled";
535 };
Maxime Ripard93b298b2012-05-11 15:35:38 +0200536
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200537 i2c0: i2c@fff84000 {
538 compatible = "atmel,at91sam9g10-i2c";
539 reg = <0xfff84000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800540 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
545
546 i2c1: i2c@fff88000 {
547 compatible = "atmel,at91sam9g10-i2c";
548 reg = <0xfff88000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800549 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200550 #address-cells = <1>;
551 #size-cells = <0>;
552 status = "disabled";
553 };
554
Bo Shen099343c2012-11-07 11:41:41 +0800555 ssc0: ssc@fff9c000 {
556 compatible = "atmel,at91sam9g45-ssc";
557 reg = <0xfff9c000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800558 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
Bo Shen315656b2012-12-13 10:05:07 +0800561 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800562 };
563
564 ssc1: ssc@fffa0000 {
565 compatible = "atmel,at91sam9g45-ssc";
566 reg = <0xfffa0000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800567 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
Bo Shen315656b2012-12-13 10:05:07 +0800570 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800571 };
572
Maxime Ripard93b298b2012-05-11 15:35:38 +0200573 adc0: adc@fffb0000 {
574 compatible = "atmel,at91sam9260-adc";
575 reg = <0xfffb0000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800576 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
Maxime Ripard93b298b2012-05-11 15:35:38 +0200577 atmel,adc-use-external-triggers;
578 atmel,adc-channels-used = <0xff>;
579 atmel,adc-vref = <3300>;
580 atmel,adc-num-channels = <8>;
581 atmel,adc-startup-time = <40>;
582 atmel,adc-channel-base = <0x30>;
583 atmel,adc-drdy-mask = <0x10000>;
584 atmel,adc-status-register = <0x1c>;
585 atmel,adc-trigger-register = <0x08>;
Ludovic Desroches4b50da62013-03-29 10:13:19 +0100586 atmel,adc-res = <8 10>;
587 atmel,adc-res-names = "lowres", "highres";
588 atmel,adc-use-res = "highres";
Maxime Ripard93b298b2012-05-11 15:35:38 +0200589
590 trigger@0 {
591 trigger-name = "external-rising";
592 trigger-value = <0x1>;
593 trigger-external;
594 };
595 trigger@1 {
596 trigger-name = "external-falling";
597 trigger-value = <0x2>;
598 trigger-external;
599 };
600
601 trigger@2 {
602 trigger-name = "external-any";
603 trigger-value = <0x3>;
604 trigger-external;
605 };
606
607 trigger@3 {
608 trigger-name = "continuous";
609 trigger-value = <0x6>;
610 };
611 };
Ludovic Desroches98731372012-11-19 12:23:36 +0100612
613 mmc0: mmc@fff80000 {
614 compatible = "atmel,hsmci";
615 reg = <0xfff80000 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800616 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desrochesd4ae89c2013-05-30 18:08:22 +0200617 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
Ludovic Desroches05c1bc92013-04-16 15:03:10 +0200618 dma-names = "rxtx";
Ludovic Desroches98731372012-11-19 12:23:36 +0100619 #address-cells = <1>;
620 #size-cells = <0>;
621 status = "disabled";
622 };
623
624 mmc1: mmc@fffd0000 {
625 compatible = "atmel,hsmci";
626 reg = <0xfffd0000 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800627 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desrochesd4ae89c2013-05-30 18:08:22 +0200628 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
Ludovic Desroches05c1bc92013-04-16 15:03:10 +0200629 dma-names = "rxtx";
Ludovic Desroches98731372012-11-19 12:23:36 +0100630 #address-cells = <1>;
631 #size-cells = <0>;
632 status = "disabled";
633 };
Linus Torvaldsdb5b0ae2012-12-13 10:39:26 -0800634
Fabio Porcedda7492e7c2012-11-12 09:37:26 +0100635 watchdog@fffffd40 {
636 compatible = "atmel,at91sam9260-wdt";
637 reg = <0xfffffd40 0x10>;
638 status = "disabled";
639 };
Richard Genoudd50f88a2013-04-03 14:02:18 +0800640
641 spi0: spi@fffa4000 {
642 #address-cells = <1>;
643 #size-cells = <0>;
644 compatible = "atmel,at91rm9200-spi";
645 reg = <0xfffa4000 0x200>;
646 interrupts = <14 4 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800647 pinctrl-names = "default";
648 pinctrl-0 = <&pinctrl_spi0>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800649 status = "disabled";
650 };
651
652 spi1: spi@fffa8000 {
653 #address-cells = <1>;
654 #size-cells = <0>;
655 compatible = "atmel,at91rm9200-spi";
656 reg = <0xfffa8000 0x200>;
657 interrupts = <15 4 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800658 pinctrl-names = "default";
659 pinctrl-0 = <&pinctrl_spi1>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800660 status = "disabled";
661 };
Jean-Christophe PLAGNIOL-VILLARD3cba4982013-05-03 20:56:01 +0800662
663 usb2: gadget@fff78000 {
664 #address-cells = <1>;
665 #size-cells = <0>;
666 compatible = "atmel,at91sam9rl-udc";
667 reg = <0x00600000 0x80000
668 0xfff78000 0x400>;
669 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
670 status = "disabled";
671
672 ep0 {
673 reg = <0>;
674 atmel,fifo-size = <64>;
675 atmel,nb-banks = <1>;
676 };
677
678 ep1 {
679 reg = <1>;
680 atmel,fifo-size = <1024>;
681 atmel,nb-banks = <2>;
682 atmel,can-dma;
683 atmel,can-isoc;
684 };
685
686 ep2 {
687 reg = <2>;
688 atmel,fifo-size = <1024>;
689 atmel,nb-banks = <2>;
690 atmel,can-dma;
691 atmel,can-isoc;
692 };
693
694 ep3 {
695 reg = <3>;
696 atmel,fifo-size = <1024>;
697 atmel,nb-banks = <3>;
698 atmel,can-dma;
699 };
700
701 ep4 {
702 reg = <4>;
703 atmel,fifo-size = <1024>;
704 atmel,nb-banks = <3>;
705 atmel,can-dma;
706 };
707
708 ep5 {
709 reg = <5>;
710 atmel,fifo-size = <1024>;
711 atmel,nb-banks = <3>;
712 atmel,can-dma;
713 atmel,can-isoc;
714 };
715
716 ep6 {
717 reg = <6>;
718 atmel,fifo-size = <1024>;
719 atmel,nb-banks = <3>;
720 atmel,can-dma;
721 atmel,can-isoc;
722 };
723 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200724 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800725
726 nand0: nand@40000000 {
727 compatible = "atmel,at91rm9200-nand";
728 #address-cells = <1>;
729 #size-cells = <1>;
730 reg = <0x40000000 0x10000000
731 0xffffe200 0x200
732 >;
733 atmel,nand-addr-offset = <21>;
734 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800737 gpios = <&pioC 8 GPIO_ACTIVE_HIGH
738 &pioC 14 GPIO_ACTIVE_HIGH
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800739 0
740 >;
741 status = "disabled";
742 };
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800743
744 usb0: ohci@00700000 {
745 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
746 reg = <0x00700000 0x100000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800747 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800748 status = "disabled";
749 };
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800750
751 usb1: ehci@00800000 {
752 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
753 reg = <0x00800000 0x100000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800754 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800755 status = "disabled";
756 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200757 };
Jean-Christophe PLAGNIOL-VILLARD8f24bda2012-02-05 18:32:37 +0800758
759 i2c@0 {
760 compatible = "i2c-gpio";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800761 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
762 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
Jean-Christophe PLAGNIOL-VILLARD8f24bda2012-02-05 18:32:37 +0800763 >;
764 i2c-gpio,sda-open-drain;
765 i2c-gpio,scl-open-drain;
766 i2c-gpio,delay-us = <5>; /* ~100 kHz */
767 #address-cells = <1>;
768 #size-cells = <0>;
769 status = "disabled";
770 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200771};