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gerrit-public.fairphone.software / kernel / msm-4.19 / 3f37169fb36497dec8f3fad14d835747d5552aa5 / . / arch / arm / boot / dts / vf610-cosmic.dts
blob: 5447f2594659906a126248a64b7842ae902765f2 [file] [log] [blame]
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * Copyright 2013 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11/dts-v1/;
12#include "vf610.dtsi"
13
14/ {
15 model = "PHYTEC Cosmic/Cosmic+ Board";
16 compatible = "phytec,vf610-cosmic", "fsl,vf610";
17
18 chosen {
19 bootargs = "console=ttyLP1,115200";
20 };
21
22 memory {
23 reg = <0x80000000 0x10000000>;
24 };
25
Stefan Agner3f3ebfb2014-11-02 21:36:44 +0100[diff] [blame]26 enet_ext: enet_ext {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <50000000>;
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]30 };
Stefan Agner3f3ebfb2014-11-02 21:36:44 +0100[diff] [blame]31};
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]32
Stefan Agner3f3ebfb2014-11-02 21:36:44 +0100[diff] [blame]33&clks {
34 clocks = <&sxosc>, <&fxosc>, <&enet_ext>;
35 clock-names = "sxosc", "fxosc", "enet_ext";
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]36};
37
Olof Johanssonab699bc2014-11-04 22:28:12 -0800[diff] [blame]38&esdhc1 {
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_esdhc1>;
41 bus-width = <4>;
42 status = "okay";
43};
44
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]45&fec1 {
46 phy-mode = "rmii";
47 pinctrl-names = "default";
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800[diff] [blame]48 pinctrl-0 = <&pinctrl_fec1>;
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]49 status = "okay";
50};
51
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800[diff] [blame]52&iomuxc {
53 vf610-cosmic {
Olof Johanssonab699bc2014-11-04 22:28:12 -0800[diff] [blame]54 pinctrl_esdhc1: esdhc1grp {
55 fsl,pins = <
56 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
57 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
58 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
59 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
60 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
61 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
62 VF610_PAD_PTB28__GPIO_98 0x219d
63 >;
64 };
65
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800[diff] [blame]66 pinctrl_fec1: fec1grp {
67 fsl,pins = <
68 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
69 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
70 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
Cory Tusaraa5fec22015-05-13 23:11:38 -0400[diff] [blame]71 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800[diff] [blame]72 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
73 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
74 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
75 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
76 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
77 >;
78 };
79
80 pinctrl_uart1: uart1grp {
81 fsl,pins = <
82 VF610_PAD_PTB4__UART1_TX 0x21a2
83 VF610_PAD_PTB5__UART1_RX 0x21a1
84 >;
85 };
86 };
87};
88
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]89&uart1 {
90 pinctrl-names = "default";
Shawn Guo07ed1ee2013-12-09 14:42:54 +0800[diff] [blame]91 pinctrl-0 = <&pinctrl_uart1>;
Matt Porter931398e2013-09-23 11:14:44 -0400[diff] [blame]92 status = "okay";
93};