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David J. Choid0507002010-04-29 06:12:41 +00001/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
David J. Choi7ab59dc2013-01-23 14:05:15 +00008 * Copyright (c) 2010-2013 Micrel, Inc.
Johan Hovoldee0dc2f2014-11-19 12:59:23 +01009 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
David J. Choid0507002010-04-29 06:12:41 +000010 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
David J. Choi7ab59dc2013-01-23 14:05:15 +000016 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
20 * ksz8081, ksz8091,
21 * ksz8061,
22 * Switch : ksz8873, ksz886x
David J. Choid0507002010-04-29 06:12:41 +000023 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/phy.h>
Baruch Siachd606ef32011-02-14 02:05:33 +000028#include <linux/micrel_phy.h>
Sean Cross954c3962013-08-21 01:46:12 +000029#include <linux/of.h>
Sascha Hauer1fadee02014-10-10 09:48:05 +020030#include <linux/clk.h>
David J. Choid0507002010-04-29 06:12:41 +000031
Marek Vasut212ea992012-09-23 16:58:49 +000032/* Operation Mode Strap Override */
33#define MII_KSZPHY_OMSO 0x16
Johan Hovold00aee092014-11-11 20:00:09 +010034#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
Sylvain Rochet2b0ba962015-02-13 21:35:33 +010035#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
Johan Hovold00aee092014-11-11 20:00:09 +010036#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
Marek Vasut212ea992012-09-23 16:58:49 +000038
Choi, David51f932c2010-06-28 15:23:41 +000039/* general Interrupt control/status reg in vendor specific block. */
40#define MII_KSZPHY_INTCS 0x1B
Johan Hovold00aee092014-11-11 20:00:09 +010041#define KSZPHY_INTCS_JABBER BIT(15)
42#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44#define KSZPHY_INTCS_PARELLEL BIT(12)
45#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46#define KSZPHY_INTCS_LINK_DOWN BIT(10)
47#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48#define KSZPHY_INTCS_LINK_UP BIT(8)
Choi, David51f932c2010-06-28 15:23:41 +000049#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
51
Johan Hovold5a167782014-11-11 20:00:14 +010052/* PHY Control 1 */
53#define MII_KSZPHY_CTRL_1 0x1e
54
55/* PHY Control 2 / PHY Control (if no PHY Control 1) */
56#define MII_KSZPHY_CTRL_2 0x1f
57#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
Choi, David51f932c2010-06-28 15:23:41 +000058/* bitmap of PHY register to set interrupt mode */
Johan Hovold00aee092014-11-11 20:00:09 +010059#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
Johan Hovold63f44b22014-11-19 12:59:18 +010060#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
Choi, David51f932c2010-06-28 15:23:41 +000061
Sean Cross954c3962013-08-21 01:46:12 +000062/* Write/read to/from extended registers */
63#define MII_KSZPHY_EXTREG 0x0b
64#define KSZPHY_EXTREG_WRITE 0x8000
65
66#define MII_KSZPHY_EXTREG_WRITE 0x0c
67#define MII_KSZPHY_EXTREG_READ 0x0d
68
69/* Extended registers */
70#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
73
74#define PS_TO_REG 200
75
Andrew Lunn2b2427d2015-12-30 16:28:27 +010076struct kszphy_hw_stat {
77 const char *string;
78 u8 reg;
79 u8 bits;
80};
81
82static struct kszphy_hw_stat kszphy_hw_stats[] = {
83 { "phy_receive_errors", 21, 16},
84 { "phy_idle_errors", 10, 8 },
85};
86
Johan Hovolde6a423a2014-11-19 12:59:15 +010087struct kszphy_type {
88 u32 led_mode_reg;
Johan Hovoldc6f95752014-11-19 12:59:22 +010089 u16 interrupt_level_mask;
Johan Hovold0f959032014-11-19 12:59:17 +010090 bool has_broadcast_disable;
Sylvain Rochet2b0ba962015-02-13 21:35:33 +010091 bool has_nand_tree_disable;
Johan Hovold63f44b22014-11-19 12:59:18 +010092 bool has_rmii_ref_clk_sel;
Johan Hovolde6a423a2014-11-19 12:59:15 +010093};
94
95struct kszphy_priv {
96 const struct kszphy_type *type;
Johan Hovolde7a792e2014-11-19 12:59:16 +010097 int led_mode;
Johan Hovold63f44b22014-11-19 12:59:18 +010098 bool rmii_ref_clk_sel;
99 bool rmii_ref_clk_sel_val;
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
Johan Hovolde6a423a2014-11-19 12:59:15 +0100101};
102
103static const struct kszphy_type ksz8021_type = {
104 .led_mode_reg = MII_KSZPHY_CTRL_2,
Johan Hovoldd0e1df92014-12-23 12:59:17 +0100105 .has_broadcast_disable = true,
Sylvain Rochet2b0ba962015-02-13 21:35:33 +0100106 .has_nand_tree_disable = true,
Johan Hovold63f44b22014-11-19 12:59:18 +0100107 .has_rmii_ref_clk_sel = true,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100108};
109
110static const struct kszphy_type ksz8041_type = {
111 .led_mode_reg = MII_KSZPHY_CTRL_1,
112};
113
114static const struct kszphy_type ksz8051_type = {
115 .led_mode_reg = MII_KSZPHY_CTRL_2,
Sylvain Rochet2b0ba962015-02-13 21:35:33 +0100116 .has_nand_tree_disable = true,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100117};
118
119static const struct kszphy_type ksz8081_type = {
120 .led_mode_reg = MII_KSZPHY_CTRL_2,
Johan Hovold0f959032014-11-19 12:59:17 +0100121 .has_broadcast_disable = true,
Sylvain Rochet2b0ba962015-02-13 21:35:33 +0100122 .has_nand_tree_disable = true,
Johan Hovold86dc1342014-11-19 12:59:19 +0100123 .has_rmii_ref_clk_sel = true,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100124};
125
Johan Hovoldc6f95752014-11-19 12:59:22 +0100126static const struct kszphy_type ks8737_type = {
127 .interrupt_level_mask = BIT(14),
128};
129
130static const struct kszphy_type ksz9021_type = {
131 .interrupt_level_mask = BIT(14),
132};
133
Sean Cross954c3962013-08-21 01:46:12 +0000134static int kszphy_extended_write(struct phy_device *phydev,
Florian Fainelli756b5082013-12-17 21:38:11 -0800135 u32 regnum, u16 val)
Sean Cross954c3962013-08-21 01:46:12 +0000136{
137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
139}
140
141static int kszphy_extended_read(struct phy_device *phydev,
Florian Fainelli756b5082013-12-17 21:38:11 -0800142 u32 regnum)
Sean Cross954c3962013-08-21 01:46:12 +0000143{
144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
146}
147
Choi, David51f932c2010-06-28 15:23:41 +0000148static int kszphy_ack_interrupt(struct phy_device *phydev)
149{
150 /* bit[7..0] int status, which is a read and clear register. */
151 int rc;
152
153 rc = phy_read(phydev, MII_KSZPHY_INTCS);
154
155 return (rc < 0) ? rc : 0;
156}
157
Choi, David51f932c2010-06-28 15:23:41 +0000158static int kszphy_config_intr(struct phy_device *phydev)
159{
Johan Hovoldc6f95752014-11-19 12:59:22 +0100160 const struct kszphy_type *type = phydev->drv->driver_data;
161 int temp;
162 u16 mask;
163
164 if (type && type->interrupt_level_mask)
165 mask = type->interrupt_level_mask;
166 else
167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
Choi, David51f932c2010-06-28 15:23:41 +0000168
169 /* set the interrupt pin active low */
170 temp = phy_read(phydev, MII_KSZPHY_CTRL);
Johan Hovold5bb8fc02014-11-11 20:00:08 +0100171 if (temp < 0)
172 return temp;
Johan Hovoldc6f95752014-11-19 12:59:22 +0100173 temp &= ~mask;
Choi, David51f932c2010-06-28 15:23:41 +0000174 phy_write(phydev, MII_KSZPHY_CTRL, temp);
Choi, David51f932c2010-06-28 15:23:41 +0000175
Johan Hovoldc6f95752014-11-19 12:59:22 +0100176 /* enable / disable interrupts */
177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
178 temp = KSZPHY_INTCS_ALL;
179 else
180 temp = 0;
Choi, David51f932c2010-06-28 15:23:41 +0000181
Johan Hovoldc6f95752014-11-19 12:59:22 +0100182 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
Choi, David51f932c2010-06-28 15:23:41 +0000183}
David J. Choid0507002010-04-29 06:12:41 +0000184
Johan Hovold63f44b22014-11-19 12:59:18 +0100185static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
186{
187 int ctrl;
188
189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
190 if (ctrl < 0)
191 return ctrl;
192
193 if (val)
194 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
195 else
196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
197
198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
199}
200
Johan Hovolde7a792e2014-11-19 12:59:16 +0100201static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
Ben Dooks20d84352014-02-26 11:48:00 +0000202{
Johan Hovold5a167782014-11-11 20:00:14 +0100203 int rc, temp, shift;
Johan Hovold86205462014-11-11 20:00:12 +0100204
Johan Hovold5a167782014-11-11 20:00:14 +0100205 switch (reg) {
206 case MII_KSZPHY_CTRL_1:
207 shift = 14;
208 break;
209 case MII_KSZPHY_CTRL_2:
210 shift = 4;
211 break;
212 default:
213 return -EINVAL;
214 }
215
Ben Dooks20d84352014-02-26 11:48:00 +0000216 temp = phy_read(phydev, reg);
Johan Hovoldb7035862014-11-11 20:00:13 +0100217 if (temp < 0) {
218 rc = temp;
219 goto out;
220 }
Ben Dooks20d84352014-02-26 11:48:00 +0000221
Sergei Shtylyov28bdc492014-03-19 02:58:16 +0300222 temp &= ~(3 << shift);
Ben Dooks20d84352014-02-26 11:48:00 +0000223 temp |= val << shift;
224 rc = phy_write(phydev, reg, temp);
Johan Hovoldb7035862014-11-11 20:00:13 +0100225out:
226 if (rc < 0)
Andrew Lunn72ba48b2016-01-06 20:11:09 +0100227 phydev_err(phydev, "failed to set led mode\n");
Ben Dooks20d84352014-02-26 11:48:00 +0000228
Johan Hovoldb7035862014-11-11 20:00:13 +0100229 return rc;
Ben Dooks20d84352014-02-26 11:48:00 +0000230}
231
Johan Hovoldbde15122014-11-11 20:00:10 +0100232/* Disable PHY address 0 as the broadcast address, so that it can be used as a
233 * unique (non-broadcast) address on a shared bus.
234 */
235static int kszphy_broadcast_disable(struct phy_device *phydev)
236{
237 int ret;
238
239 ret = phy_read(phydev, MII_KSZPHY_OMSO);
240 if (ret < 0)
241 goto out;
242
243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
244out:
245 if (ret)
Andrew Lunn72ba48b2016-01-06 20:11:09 +0100246 phydev_err(phydev, "failed to disable broadcast address\n");
Johan Hovoldbde15122014-11-11 20:00:10 +0100247
248 return ret;
249}
250
Sylvain Rochet2b0ba962015-02-13 21:35:33 +0100251static int kszphy_nand_tree_disable(struct phy_device *phydev)
252{
253 int ret;
254
255 ret = phy_read(phydev, MII_KSZPHY_OMSO);
256 if (ret < 0)
257 goto out;
258
259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
260 return 0;
261
262 ret = phy_write(phydev, MII_KSZPHY_OMSO,
263 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
264out:
265 if (ret)
Andrew Lunn72ba48b2016-01-06 20:11:09 +0100266 phydev_err(phydev, "failed to disable NAND tree mode\n");
Sylvain Rochet2b0ba962015-02-13 21:35:33 +0100267
268 return ret;
269}
270
David J. Choid0507002010-04-29 06:12:41 +0000271static int kszphy_config_init(struct phy_device *phydev)
272{
Johan Hovolde6a423a2014-11-19 12:59:15 +0100273 struct kszphy_priv *priv = phydev->priv;
274 const struct kszphy_type *type;
Johan Hovold63f44b22014-11-19 12:59:18 +0100275 int ret;
David J. Choid0507002010-04-29 06:12:41 +0000276
Johan Hovolde6a423a2014-11-19 12:59:15 +0100277 if (!priv)
278 return 0;
279
280 type = priv->type;
281
Johan Hovold0f959032014-11-19 12:59:17 +0100282 if (type->has_broadcast_disable)
283 kszphy_broadcast_disable(phydev);
284
Sylvain Rochet2b0ba962015-02-13 21:35:33 +0100285 if (type->has_nand_tree_disable)
286 kszphy_nand_tree_disable(phydev);
287
Johan Hovold63f44b22014-11-19 12:59:18 +0100288 if (priv->rmii_ref_clk_sel) {
289 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
290 if (ret) {
Andrew Lunn72ba48b2016-01-06 20:11:09 +0100291 phydev_err(phydev,
292 "failed to set rmii reference clock\n");
Johan Hovold63f44b22014-11-19 12:59:18 +0100293 return ret;
294 }
295 }
296
Johan Hovolde7a792e2014-11-19 12:59:16 +0100297 if (priv->led_mode >= 0)
298 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
Johan Hovolde6a423a2014-11-19 12:59:15 +0100299
300 return 0;
Ben Dooks20d84352014-02-26 11:48:00 +0000301}
302
Philipp Zabel77501a72016-07-14 16:29:43 +0200303static int ksz8041_config_init(struct phy_device *phydev)
304{
305 struct device_node *of_node = phydev->mdio.dev.of_node;
306
307 /* Limit supported and advertised modes in fiber mode */
308 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
309 phydev->dev_flags |= MICREL_PHY_FXEN;
Kirill Esipovffa54a22016-11-21 19:53:31 +0300310 phydev->supported &= SUPPORTED_100baseT_Full |
Philipp Zabel77501a72016-07-14 16:29:43 +0200311 SUPPORTED_100baseT_Half;
Kirill Esipovffa54a22016-11-21 19:53:31 +0300312 phydev->supported |= SUPPORTED_FIBRE;
313 phydev->advertising &= ADVERTISED_100baseT_Full |
Philipp Zabel77501a72016-07-14 16:29:43 +0200314 ADVERTISED_100baseT_Half;
Kirill Esipovffa54a22016-11-21 19:53:31 +0300315 phydev->advertising |= ADVERTISED_FIBRE;
Philipp Zabel77501a72016-07-14 16:29:43 +0200316 phydev->autoneg = AUTONEG_DISABLE;
317 }
318
319 return kszphy_config_init(phydev);
320}
321
322static int ksz8041_config_aneg(struct phy_device *phydev)
323{
324 /* Skip auto-negotiation in fiber mode */
325 if (phydev->dev_flags & MICREL_PHY_FXEN) {
326 phydev->speed = SPEED_100;
327 return 0;
328 }
329
330 return genphy_config_aneg(phydev);
331}
332
Sean Cross954c3962013-08-21 01:46:12 +0000333static int ksz9021_load_values_from_of(struct phy_device *phydev,
Jaeden Amero3c9a9f72015-06-05 18:00:24 -0500334 const struct device_node *of_node,
335 u16 reg,
336 const char *field1, const char *field2,
337 const char *field3, const char *field4)
Sean Cross954c3962013-08-21 01:46:12 +0000338{
339 int val1 = -1;
340 int val2 = -2;
341 int val3 = -3;
342 int val4 = -4;
343 int newval;
344 int matches = 0;
345
346 if (!of_property_read_u32(of_node, field1, &val1))
347 matches++;
348
349 if (!of_property_read_u32(of_node, field2, &val2))
350 matches++;
351
352 if (!of_property_read_u32(of_node, field3, &val3))
353 matches++;
354
355 if (!of_property_read_u32(of_node, field4, &val4))
356 matches++;
357
358 if (!matches)
359 return 0;
360
361 if (matches < 4)
362 newval = kszphy_extended_read(phydev, reg);
363 else
364 newval = 0;
365
366 if (val1 != -1)
367 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
368
Hubert Chaumette6a119742014-04-22 15:01:04 +0200369 if (val2 != -2)
Sean Cross954c3962013-08-21 01:46:12 +0000370 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
371
Hubert Chaumette6a119742014-04-22 15:01:04 +0200372 if (val3 != -3)
Sean Cross954c3962013-08-21 01:46:12 +0000373 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
374
Hubert Chaumette6a119742014-04-22 15:01:04 +0200375 if (val4 != -4)
Sean Cross954c3962013-08-21 01:46:12 +0000376 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
377
378 return kszphy_extended_write(phydev, reg, newval);
379}
380
381static int ksz9021_config_init(struct phy_device *phydev)
382{
Andrew Lunne5a03bf2016-01-06 20:11:16 +0100383 const struct device *dev = &phydev->mdio.dev;
Jaeden Amero3c9a9f72015-06-05 18:00:24 -0500384 const struct device_node *of_node = dev->of_node;
Andrew Lunn651df212015-12-09 19:56:31 +0100385 const struct device *dev_walker;
Sean Cross954c3962013-08-21 01:46:12 +0000386
Andrew Lunn651df212015-12-09 19:56:31 +0100387 /* The Micrel driver has a deprecated option to place phy OF
388 * properties in the MAC node. Walk up the tree of devices to
389 * find a device with an OF node.
390 */
Andrew Lunne5a03bf2016-01-06 20:11:16 +0100391 dev_walker = &phydev->mdio.dev;
Andrew Lunn651df212015-12-09 19:56:31 +0100392 do {
393 of_node = dev_walker->of_node;
394 dev_walker = dev_walker->parent;
395
396 } while (!of_node && dev_walker);
Sean Cross954c3962013-08-21 01:46:12 +0000397
398 if (of_node) {
399 ksz9021_load_values_from_of(phydev, of_node,
400 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
401 "txen-skew-ps", "txc-skew-ps",
402 "rxdv-skew-ps", "rxc-skew-ps");
403 ksz9021_load_values_from_of(phydev, of_node,
404 MII_KSZPHY_RX_DATA_PAD_SKEW,
405 "rxd0-skew-ps", "rxd1-skew-ps",
406 "rxd2-skew-ps", "rxd3-skew-ps");
407 ksz9021_load_values_from_of(phydev, of_node,
408 MII_KSZPHY_TX_DATA_PAD_SKEW,
409 "txd0-skew-ps", "txd1-skew-ps",
410 "txd2-skew-ps", "txd3-skew-ps");
411 }
412 return 0;
413}
414
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200415#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
416#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
417#define OP_DATA 1
418#define KSZ9031_PS_TO_REG 60
419
420/* Extended registers */
Jaeden Amero6270e1a2015-06-05 18:00:26 -0500421/* MMD Address 0x0 */
422#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
423#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
424
Jaeden Ameroae6c97b2015-06-05 18:00:25 -0500425/* MMD Address 0x2 */
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200426#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
427#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
428#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
429#define MII_KSZ9031RN_CLK_PAD_SKEW 8
430
Mike Looijmansaf70c1f2016-10-04 07:52:04 +0200431/* MMD Address 0x1C */
432#define MII_KSZ9031RN_EDPD 0x23
433#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
434
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200435static int ksz9031_extended_write(struct phy_device *phydev,
436 u8 mode, u32 dev_addr, u32 regnum, u16 val)
437{
438 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
439 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
440 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
441 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
442}
443
444static int ksz9031_extended_read(struct phy_device *phydev,
445 u8 mode, u32 dev_addr, u32 regnum)
446{
447 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
448 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
449 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
450 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
451}
452
453static int ksz9031_of_load_skew_values(struct phy_device *phydev,
Jaeden Amero3c9a9f72015-06-05 18:00:24 -0500454 const struct device_node *of_node,
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200455 u16 reg, size_t field_sz,
Jaeden Amero3c9a9f72015-06-05 18:00:24 -0500456 const char *field[], u8 numfields)
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200457{
458 int val[4] = {-1, -2, -3, -4};
459 int matches = 0;
460 u16 mask;
461 u16 maxval;
462 u16 newval;
463 int i;
464
465 for (i = 0; i < numfields; i++)
466 if (!of_property_read_u32(of_node, field[i], val + i))
467 matches++;
468
469 if (!matches)
470 return 0;
471
472 if (matches < numfields)
473 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
474 else
475 newval = 0;
476
477 maxval = (field_sz == 4) ? 0xf : 0x1f;
478 for (i = 0; i < numfields; i++)
479 if (val[i] != -(i + 1)) {
480 mask = 0xffff;
481 mask ^= maxval << (field_sz * i);
482 newval = (newval & mask) |
483 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
484 << (field_sz * i));
485 }
486
487 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
488}
489
Jaeden Amero6270e1a2015-06-05 18:00:26 -0500490static int ksz9031_center_flp_timing(struct phy_device *phydev)
491{
492 int result;
493
494 /* Center KSZ9031RNX FLP timing at 16ms. */
495 result = ksz9031_extended_write(phydev, OP_DATA, 0,
496 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
497 result = ksz9031_extended_write(phydev, OP_DATA, 0,
498 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
499
500 if (result)
501 return result;
502
503 return genphy_restart_aneg(phydev);
504}
505
Mike Looijmansaf70c1f2016-10-04 07:52:04 +0200506/* Enable energy-detect power-down mode */
507static int ksz9031_enable_edpd(struct phy_device *phydev)
508{
509 int reg;
510
511 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
512 if (reg < 0)
513 return reg;
514 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
515 reg | MII_KSZ9031RN_EDPD_ENABLE);
516}
517
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200518static int ksz9031_config_init(struct phy_device *phydev)
519{
Andrew Lunne5a03bf2016-01-06 20:11:16 +0100520 const struct device *dev = &phydev->mdio.dev;
Jaeden Amero3c9a9f72015-06-05 18:00:24 -0500521 const struct device_node *of_node = dev->of_node;
522 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
523 static const char *rx_data_skews[4] = {
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200524 "rxd0-skew-ps", "rxd1-skew-ps",
525 "rxd2-skew-ps", "rxd3-skew-ps"
526 };
Jaeden Amero3c9a9f72015-06-05 18:00:24 -0500527 static const char *tx_data_skews[4] = {
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200528 "txd0-skew-ps", "txd1-skew-ps",
529 "txd2-skew-ps", "txd3-skew-ps"
530 };
Jaeden Amero3c9a9f72015-06-05 18:00:24 -0500531 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
Roosen Henrib4c19f72016-01-07 09:31:15 +0100532 const struct device *dev_walker;
Mike Looijmansaf70c1f2016-10-04 07:52:04 +0200533 int result;
534
535 result = ksz9031_enable_edpd(phydev);
536 if (result < 0)
537 return result;
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200538
Roosen Henrib4c19f72016-01-07 09:31:15 +0100539 /* The Micrel driver has a deprecated option to place phy OF
540 * properties in the MAC node. Walk up the tree of devices to
541 * find a device with an OF node.
542 */
David S. Miller9d367ed2016-01-11 23:55:43 -0500543 dev_walker = &phydev->mdio.dev;
Roosen Henrib4c19f72016-01-07 09:31:15 +0100544 do {
545 of_node = dev_walker->of_node;
546 dev_walker = dev_walker->parent;
547 } while (!of_node && dev_walker);
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200548
549 if (of_node) {
550 ksz9031_of_load_skew_values(phydev, of_node,
551 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
552 clk_skews, 2);
553
554 ksz9031_of_load_skew_values(phydev, of_node,
555 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
556 control_skews, 2);
557
558 ksz9031_of_load_skew_values(phydev, of_node,
559 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
560 rx_data_skews, 4);
561
562 ksz9031_of_load_skew_values(phydev, of_node,
563 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
564 tx_data_skews, 4);
565 }
Jaeden Amero6270e1a2015-06-05 18:00:26 -0500566
567 return ksz9031_center_flp_timing(phydev);
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200568}
569
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000570#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
Johan Hovold00aee092014-11-11 20:00:09 +0100571#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
572#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
Jingoo Han32d73b12013-08-06 17:29:35 +0900573static int ksz8873mll_read_status(struct phy_device *phydev)
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000574{
575 int regval;
576
577 /* dummy read */
578 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
579
580 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
581
582 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
583 phydev->duplex = DUPLEX_HALF;
584 else
585 phydev->duplex = DUPLEX_FULL;
586
587 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
588 phydev->speed = SPEED_10;
589 else
590 phydev->speed = SPEED_100;
591
592 phydev->link = 1;
593 phydev->pause = phydev->asym_pause = 0;
594
595 return 0;
596}
597
Nathan Sullivand2fd7192015-10-21 14:17:04 -0500598static int ksz9031_read_status(struct phy_device *phydev)
599{
600 int err;
601 int regval;
602
603 err = genphy_read_status(phydev);
604 if (err)
605 return err;
606
607 /* Make sure the PHY is not broken. Read idle error count,
608 * and reset the PHY if it is maxed out.
609 */
610 regval = phy_read(phydev, MII_STAT1000);
611 if ((regval & 0xFF) == 0xFF) {
612 phy_init_hw(phydev);
613 phydev->link = 0;
614 }
615
616 return 0;
617}
618
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000619static int ksz8873mll_config_aneg(struct phy_device *phydev)
620{
621 return 0;
622}
623
Vince Bridgers19936942014-07-29 15:19:58 -0500624/* This routine returns -1 as an indication to the caller that the
625 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
626 * MMD extended PHY registers.
627 */
628static int
Russell Kingd11437e2017-03-21 16:36:58 +0000629ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum)
Vince Bridgers19936942014-07-29 15:19:58 -0500630{
631 return -1;
632}
633
634/* This routine does nothing since the Micrel ksz9021 does not support
635 * standard IEEE MMD extended PHY registers.
636 */
Russell Kingd11437e2017-03-21 16:36:58 +0000637static int
638ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum, u16 val)
Vince Bridgers19936942014-07-29 15:19:58 -0500639{
Russell Kingd11437e2017-03-21 16:36:58 +0000640 return -1;
Vince Bridgers19936942014-07-29 15:19:58 -0500641}
642
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100643static int kszphy_get_sset_count(struct phy_device *phydev)
644{
645 return ARRAY_SIZE(kszphy_hw_stats);
646}
647
648static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
649{
650 int i;
651
652 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
653 memcpy(data + i * ETH_GSTRING_LEN,
654 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
655 }
656}
657
658#ifndef UINT64_MAX
659#define UINT64_MAX (u64)(~((u64)0))
660#endif
661static u64 kszphy_get_stat(struct phy_device *phydev, int i)
662{
663 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
664 struct kszphy_priv *priv = phydev->priv;
Andrew Lunn321b4d42016-02-20 00:35:29 +0100665 int val;
666 u64 ret;
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100667
668 val = phy_read(phydev, stat.reg);
669 if (val < 0) {
Andrew Lunn321b4d42016-02-20 00:35:29 +0100670 ret = UINT64_MAX;
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100671 } else {
672 val = val & ((1 << stat.bits) - 1);
673 priv->stats[i] += val;
Andrew Lunn321b4d42016-02-20 00:35:29 +0100674 ret = priv->stats[i];
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100675 }
676
Andrew Lunn321b4d42016-02-20 00:35:29 +0100677 return ret;
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100678}
679
680static void kszphy_get_stats(struct phy_device *phydev,
681 struct ethtool_stats *stats, u64 *data)
682{
683 int i;
684
685 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
686 data[i] = kszphy_get_stat(phydev, i);
687}
688
Wenyou Yang836384d2016-08-05 14:35:41 +0800689static int kszphy_suspend(struct phy_device *phydev)
690{
691 /* Disable PHY Interrupts */
692 if (phy_interrupt_is_valid(phydev)) {
693 phydev->interrupts = PHY_INTERRUPT_DISABLED;
694 if (phydev->drv->config_intr)
695 phydev->drv->config_intr(phydev);
696 }
697
698 return genphy_suspend(phydev);
699}
700
Alexandre Bellonif5aba912016-02-26 19:18:22 +0100701static int kszphy_resume(struct phy_device *phydev)
702{
Wenyou Yang836384d2016-08-05 14:35:41 +0800703 genphy_resume(phydev);
Alexandre Bellonif5aba912016-02-26 19:18:22 +0100704
Wenyou Yang836384d2016-08-05 14:35:41 +0800705 /* Enable PHY Interrupts */
706 if (phy_interrupt_is_valid(phydev)) {
707 phydev->interrupts = PHY_INTERRUPT_ENABLED;
708 if (phydev->drv->config_intr)
709 phydev->drv->config_intr(phydev);
710 }
Alexandre Bellonif5aba912016-02-26 19:18:22 +0100711
712 return 0;
713}
714
Johan Hovolde6a423a2014-11-19 12:59:15 +0100715static int kszphy_probe(struct phy_device *phydev)
716{
717 const struct kszphy_type *type = phydev->drv->driver_data;
Andrew Lunne5a03bf2016-01-06 20:11:16 +0100718 const struct device_node *np = phydev->mdio.dev.of_node;
Johan Hovolde6a423a2014-11-19 12:59:15 +0100719 struct kszphy_priv *priv;
Johan Hovold63f44b22014-11-19 12:59:18 +0100720 struct clk *clk;
Johan Hovolde7a792e2014-11-19 12:59:16 +0100721 int ret;
Johan Hovolde6a423a2014-11-19 12:59:15 +0100722
Andrew Lunne5a03bf2016-01-06 20:11:16 +0100723 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
Johan Hovolde6a423a2014-11-19 12:59:15 +0100724 if (!priv)
725 return -ENOMEM;
726
727 phydev->priv = priv;
728
729 priv->type = type;
730
Johan Hovolde7a792e2014-11-19 12:59:16 +0100731 if (type->led_mode_reg) {
732 ret = of_property_read_u32(np, "micrel,led-mode",
733 &priv->led_mode);
734 if (ret)
735 priv->led_mode = -1;
736
737 if (priv->led_mode > 3) {
Andrew Lunn72ba48b2016-01-06 20:11:09 +0100738 phydev_err(phydev, "invalid led mode: 0x%02x\n",
739 priv->led_mode);
Johan Hovolde7a792e2014-11-19 12:59:16 +0100740 priv->led_mode = -1;
741 }
742 } else {
743 priv->led_mode = -1;
744 }
745
Andrew Lunne5a03bf2016-01-06 20:11:16 +0100746 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
Niklas Casselbced8702015-05-12 09:43:14 +0200747 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
748 if (!IS_ERR_OR_NULL(clk)) {
Sascha Hauer1fadee02014-10-10 09:48:05 +0200749 unsigned long rate = clk_get_rate(clk);
Johan Hovold86dc1342014-11-19 12:59:19 +0100750 bool rmii_ref_clk_sel_25_mhz;
Sascha Hauer1fadee02014-10-10 09:48:05 +0200751
Johan Hovold63f44b22014-11-19 12:59:18 +0100752 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
Johan Hovold86dc1342014-11-19 12:59:19 +0100753 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
754 "micrel,rmii-reference-clock-select-25-mhz");
Johan Hovold63f44b22014-11-19 12:59:18 +0100755
Sascha Hauer1fadee02014-10-10 09:48:05 +0200756 if (rate > 24500000 && rate < 25500000) {
Johan Hovold86dc1342014-11-19 12:59:19 +0100757 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
Sascha Hauer1fadee02014-10-10 09:48:05 +0200758 } else if (rate > 49500000 && rate < 50500000) {
Johan Hovold86dc1342014-11-19 12:59:19 +0100759 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
Sascha Hauer1fadee02014-10-10 09:48:05 +0200760 } else {
Andrew Lunn72ba48b2016-01-06 20:11:09 +0100761 phydev_err(phydev, "Clock rate out of range: %ld\n",
762 rate);
Sascha Hauer1fadee02014-10-10 09:48:05 +0200763 return -EINVAL;
764 }
765 }
766
Johan Hovold63f44b22014-11-19 12:59:18 +0100767 /* Support legacy board-file configuration */
768 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
769 priv->rmii_ref_clk_sel = true;
770 priv->rmii_ref_clk_sel_val = true;
771 }
772
773 return 0;
Sascha Hauer1fadee02014-10-10 09:48:05 +0200774}
775
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000776static struct phy_driver ksphy_driver[] = {
777{
Choi, David51f932c2010-06-28 15:23:41 +0000778 .phy_id = PHY_ID_KS8737,
Fabio Estevamf893a992016-05-11 17:02:05 -0300779 .phy_id_mask = MICREL_PHY_ID_MASK,
Choi, David51f932c2010-06-28 15:23:41 +0000780 .name = "Micrel KS8737",
Timur Tabi529ed122016-12-07 13:20:51 -0600781 .features = PHY_BASIC_FEATURES,
Choi, David51f932c2010-06-28 15:23:41 +0000782 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100783 .driver_data = &ks8737_type,
David J. Choid0507002010-04-29 06:12:41 +0000784 .config_init = kszphy_config_init,
785 .config_aneg = genphy_config_aneg,
786 .read_status = genphy_read_status,
Choi, David51f932c2010-06-28 15:23:41 +0000787 .ack_interrupt = kszphy_ack_interrupt,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100788 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200789 .suspend = genphy_suspend,
790 .resume = genphy_resume,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000791}, {
Marek Vasut212ea992012-09-23 16:58:49 +0000792 .phy_id = PHY_ID_KSZ8021,
793 .phy_id_mask = 0x00ffffff,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000794 .name = "Micrel KSZ8021 or KSZ8031",
Timur Tabi529ed122016-12-07 13:20:51 -0600795 .features = PHY_BASIC_FEATURES,
Marek Vasut212ea992012-09-23 16:58:49 +0000796 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100797 .driver_data = &ksz8021_type,
Johan Hovold63f44b22014-11-19 12:59:18 +0100798 .probe = kszphy_probe,
Johan Hovoldd0e1df92014-12-23 12:59:17 +0100799 .config_init = kszphy_config_init,
Marek Vasut212ea992012-09-23 16:58:49 +0000800 .config_aneg = genphy_config_aneg,
801 .read_status = genphy_read_status,
802 .ack_interrupt = kszphy_ack_interrupt,
803 .config_intr = kszphy_config_intr,
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100804 .get_sset_count = kszphy_get_sset_count,
805 .get_strings = kszphy_get_strings,
806 .get_stats = kszphy_get_stats,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200807 .suspend = genphy_suspend,
808 .resume = genphy_resume,
Marek Vasut212ea992012-09-23 16:58:49 +0000809}, {
Hector Palaciosb818d1a2013-03-10 22:50:02 +0000810 .phy_id = PHY_ID_KSZ8031,
811 .phy_id_mask = 0x00ffffff,
812 .name = "Micrel KSZ8031",
Timur Tabi529ed122016-12-07 13:20:51 -0600813 .features = PHY_BASIC_FEATURES,
Hector Palaciosb818d1a2013-03-10 22:50:02 +0000814 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100815 .driver_data = &ksz8021_type,
Johan Hovold63f44b22014-11-19 12:59:18 +0100816 .probe = kszphy_probe,
Johan Hovoldd0e1df92014-12-23 12:59:17 +0100817 .config_init = kszphy_config_init,
Hector Palaciosb818d1a2013-03-10 22:50:02 +0000818 .config_aneg = genphy_config_aneg,
819 .read_status = genphy_read_status,
820 .ack_interrupt = kszphy_ack_interrupt,
821 .config_intr = kszphy_config_intr,
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100822 .get_sset_count = kszphy_get_sset_count,
823 .get_strings = kszphy_get_strings,
824 .get_stats = kszphy_get_stats,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200825 .suspend = genphy_suspend,
826 .resume = genphy_resume,
Hector Palaciosb818d1a2013-03-10 22:50:02 +0000827}, {
Marek Vasut510d5732012-09-23 16:58:50 +0000828 .phy_id = PHY_ID_KSZ8041,
Fabio Estevamf893a992016-05-11 17:02:05 -0300829 .phy_id_mask = MICREL_PHY_ID_MASK,
Marek Vasut510d5732012-09-23 16:58:50 +0000830 .name = "Micrel KSZ8041",
Timur Tabi529ed122016-12-07 13:20:51 -0600831 .features = PHY_BASIC_FEATURES,
Choi, David51f932c2010-06-28 15:23:41 +0000832 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100833 .driver_data = &ksz8041_type,
834 .probe = kszphy_probe,
Philipp Zabel77501a72016-07-14 16:29:43 +0200835 .config_init = ksz8041_config_init,
836 .config_aneg = ksz8041_config_aneg,
David J. Choid0507002010-04-29 06:12:41 +0000837 .read_status = genphy_read_status,
Choi, David51f932c2010-06-28 15:23:41 +0000838 .ack_interrupt = kszphy_ack_interrupt,
839 .config_intr = kszphy_config_intr,
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100840 .get_sset_count = kszphy_get_sset_count,
841 .get_strings = kszphy_get_strings,
842 .get_stats = kszphy_get_stats,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200843 .suspend = genphy_suspend,
844 .resume = genphy_resume,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000845}, {
Sergei Shtylyov4bd7b512013-12-10 02:20:41 +0300846 .phy_id = PHY_ID_KSZ8041RNLI,
Fabio Estevamf893a992016-05-11 17:02:05 -0300847 .phy_id_mask = MICREL_PHY_ID_MASK,
Sergei Shtylyov4bd7b512013-12-10 02:20:41 +0300848 .name = "Micrel KSZ8041RNLI",
Timur Tabi529ed122016-12-07 13:20:51 -0600849 .features = PHY_BASIC_FEATURES,
Sergei Shtylyov4bd7b512013-12-10 02:20:41 +0300850 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100851 .driver_data = &ksz8041_type,
852 .probe = kszphy_probe,
853 .config_init = kszphy_config_init,
Sergei Shtylyov4bd7b512013-12-10 02:20:41 +0300854 .config_aneg = genphy_config_aneg,
855 .read_status = genphy_read_status,
856 .ack_interrupt = kszphy_ack_interrupt,
857 .config_intr = kszphy_config_intr,
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100858 .get_sset_count = kszphy_get_sset_count,
859 .get_strings = kszphy_get_strings,
860 .get_stats = kszphy_get_stats,
Sergei Shtylyov4bd7b512013-12-10 02:20:41 +0300861 .suspend = genphy_suspend,
862 .resume = genphy_resume,
Sergei Shtylyov4bd7b512013-12-10 02:20:41 +0300863}, {
Marek Vasut510d5732012-09-23 16:58:50 +0000864 .phy_id = PHY_ID_KSZ8051,
Fabio Estevamf893a992016-05-11 17:02:05 -0300865 .phy_id_mask = MICREL_PHY_ID_MASK,
Marek Vasut510d5732012-09-23 16:58:50 +0000866 .name = "Micrel KSZ8051",
Timur Tabi529ed122016-12-07 13:20:51 -0600867 .features = PHY_BASIC_FEATURES,
Choi, David51f932c2010-06-28 15:23:41 +0000868 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100869 .driver_data = &ksz8051_type,
870 .probe = kszphy_probe,
Johan Hovold63f44b22014-11-19 12:59:18 +0100871 .config_init = kszphy_config_init,
Choi, David51f932c2010-06-28 15:23:41 +0000872 .config_aneg = genphy_config_aneg,
873 .read_status = genphy_read_status,
874 .ack_interrupt = kszphy_ack_interrupt,
875 .config_intr = kszphy_config_intr,
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100876 .get_sset_count = kszphy_get_sset_count,
877 .get_strings = kszphy_get_strings,
878 .get_stats = kszphy_get_stats,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200879 .suspend = genphy_suspend,
880 .resume = genphy_resume,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000881}, {
Marek Vasut510d5732012-09-23 16:58:50 +0000882 .phy_id = PHY_ID_KSZ8001,
883 .name = "Micrel KSZ8001 or KS8721",
Alexander Steinecd5a322016-07-29 12:12:08 +0200884 .phy_id_mask = 0x00fffffc,
Timur Tabi529ed122016-12-07 13:20:51 -0600885 .features = PHY_BASIC_FEATURES,
Choi, David51f932c2010-06-28 15:23:41 +0000886 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100887 .driver_data = &ksz8041_type,
888 .probe = kszphy_probe,
889 .config_init = kszphy_config_init,
Choi, David51f932c2010-06-28 15:23:41 +0000890 .config_aneg = genphy_config_aneg,
891 .read_status = genphy_read_status,
892 .ack_interrupt = kszphy_ack_interrupt,
893 .config_intr = kszphy_config_intr,
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100894 .get_sset_count = kszphy_get_sset_count,
895 .get_strings = kszphy_get_strings,
896 .get_stats = kszphy_get_stats,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200897 .suspend = genphy_suspend,
898 .resume = genphy_resume,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000899}, {
David J. Choi7ab59dc2013-01-23 14:05:15 +0000900 .phy_id = PHY_ID_KSZ8081,
901 .name = "Micrel KSZ8081 or KSZ8091",
Fabio Estevamf893a992016-05-11 17:02:05 -0300902 .phy_id_mask = MICREL_PHY_ID_MASK,
Timur Tabi529ed122016-12-07 13:20:51 -0600903 .features = PHY_BASIC_FEATURES,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000904 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100905 .driver_data = &ksz8081_type,
906 .probe = kszphy_probe,
Johan Hovold0f959032014-11-19 12:59:17 +0100907 .config_init = kszphy_config_init,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000908 .config_aneg = genphy_config_aneg,
909 .read_status = genphy_read_status,
910 .ack_interrupt = kszphy_ack_interrupt,
911 .config_intr = kszphy_config_intr,
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100912 .get_sset_count = kszphy_get_sset_count,
913 .get_strings = kszphy_get_strings,
914 .get_stats = kszphy_get_stats,
Wenyou Yang836384d2016-08-05 14:35:41 +0800915 .suspend = kszphy_suspend,
Alexandre Bellonif5aba912016-02-26 19:18:22 +0100916 .resume = kszphy_resume,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000917}, {
918 .phy_id = PHY_ID_KSZ8061,
919 .name = "Micrel KSZ8061",
Fabio Estevamf893a992016-05-11 17:02:05 -0300920 .phy_id_mask = MICREL_PHY_ID_MASK,
Timur Tabi529ed122016-12-07 13:20:51 -0600921 .features = PHY_BASIC_FEATURES,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000922 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
923 .config_init = kszphy_config_init,
924 .config_aneg = genphy_config_aneg,
925 .read_status = genphy_read_status,
926 .ack_interrupt = kszphy_ack_interrupt,
927 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200928 .suspend = genphy_suspend,
929 .resume = genphy_resume,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000930}, {
David J. Choid0507002010-04-29 06:12:41 +0000931 .phy_id = PHY_ID_KSZ9021,
Jason Wang48d7d0a2012-06-17 22:52:09 +0000932 .phy_id_mask = 0x000ffffe,
David J. Choid0507002010-04-29 06:12:41 +0000933 .name = "Micrel KSZ9021 Gigabit PHY",
Timur Tabi529ed122016-12-07 13:20:51 -0600934 .features = PHY_GBIT_FEATURES,
Choi, David51f932c2010-06-28 15:23:41 +0000935 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100936 .driver_data = &ksz9021_type,
Grygorii Strashkobfe72442017-04-13 14:11:27 -0500937 .probe = kszphy_probe,
Sean Cross954c3962013-08-21 01:46:12 +0000938 .config_init = ksz9021_config_init,
David J. Choid0507002010-04-29 06:12:41 +0000939 .config_aneg = genphy_config_aneg,
940 .read_status = genphy_read_status,
Choi, David51f932c2010-06-28 15:23:41 +0000941 .ack_interrupt = kszphy_ack_interrupt,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100942 .config_intr = kszphy_config_intr,
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100943 .get_sset_count = kszphy_get_sset_count,
944 .get_strings = kszphy_get_strings,
945 .get_stats = kszphy_get_stats,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200946 .suspend = genphy_suspend,
947 .resume = genphy_resume,
Russell Kingd11437e2017-03-21 16:36:58 +0000948 .read_mmd = ksz9021_rd_mmd_phyreg,
949 .write_mmd = ksz9021_wr_mmd_phyreg,
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000950}, {
David J. Choi7ab59dc2013-01-23 14:05:15 +0000951 .phy_id = PHY_ID_KSZ9031,
Fabio Estevamf893a992016-05-11 17:02:05 -0300952 .phy_id_mask = MICREL_PHY_ID_MASK,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000953 .name = "Micrel KSZ9031 Gigabit PHY",
Timur Tabi529ed122016-12-07 13:20:51 -0600954 .features = PHY_GBIT_FEATURES,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000955 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100956 .driver_data = &ksz9021_type,
Grygorii Strashkobfe72442017-04-13 14:11:27 -0500957 .probe = kszphy_probe,
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200958 .config_init = ksz9031_config_init,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000959 .config_aneg = genphy_config_aneg,
Nathan Sullivand2fd7192015-10-21 14:17:04 -0500960 .read_status = ksz9031_read_status,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000961 .ack_interrupt = kszphy_ack_interrupt,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100962 .config_intr = kszphy_config_intr,
Andrew Lunn2b2427d2015-12-30 16:28:27 +0100963 .get_sset_count = kszphy_get_sset_count,
964 .get_strings = kszphy_get_strings,
965 .get_stats = kszphy_get_stats,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200966 .suspend = genphy_suspend,
Xander Hufff64f1482016-08-22 15:57:16 -0500967 .resume = kszphy_resume,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000968}, {
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000969 .phy_id = PHY_ID_KSZ8873MLL,
Fabio Estevamf893a992016-05-11 17:02:05 -0300970 .phy_id_mask = MICREL_PHY_ID_MASK,
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000971 .name = "Micrel KSZ8873MLL Switch",
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000972 .flags = PHY_HAS_MAGICANEG,
973 .config_init = kszphy_config_init,
974 .config_aneg = ksz8873mll_config_aneg,
975 .read_status = ksz8873mll_read_status,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200976 .suspend = genphy_suspend,
977 .resume = genphy_resume,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000978}, {
979 .phy_id = PHY_ID_KSZ886X,
Fabio Estevamf893a992016-05-11 17:02:05 -0300980 .phy_id_mask = MICREL_PHY_ID_MASK,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000981 .name = "Micrel KSZ886X Switch",
Timur Tabi529ed122016-12-07 13:20:51 -0600982 .features = PHY_BASIC_FEATURES,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000983 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
984 .config_init = kszphy_config_init,
985 .config_aneg = genphy_config_aneg,
986 .read_status = genphy_read_status,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200987 .suspend = genphy_suspend,
988 .resume = genphy_resume,
Sean Nyekjaer9d162ed2017-01-27 08:46:23 +0100989}, {
990 .phy_id = PHY_ID_KSZ8795,
991 .phy_id_mask = MICREL_PHY_ID_MASK,
992 .name = "Micrel KSZ8795",
Sean Nyekjaercf626c32017-01-27 21:39:03 +0100993 .features = PHY_BASIC_FEATURES,
Sean Nyekjaer9d162ed2017-01-27 08:46:23 +0100994 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
995 .config_init = kszphy_config_init,
996 .config_aneg = ksz8873mll_config_aneg,
997 .read_status = ksz8873mll_read_status,
Sean Nyekjaer9d162ed2017-01-27 08:46:23 +0100998 .suspend = genphy_suspend,
999 .resume = genphy_resume,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +00001000} };
David J. Choid0507002010-04-29 06:12:41 +00001001
Johan Hovold50fd7152014-11-11 19:45:59 +01001002module_phy_driver(ksphy_driver);
David J. Choid0507002010-04-29 06:12:41 +00001003
1004MODULE_DESCRIPTION("Micrel PHY driver");
1005MODULE_AUTHOR("David J. Choi");
1006MODULE_LICENSE("GPL");
David S. Miller52a60ed2010-05-03 15:48:29 -07001007
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +00001008static struct mdio_device_id __maybe_unused micrel_tbl[] = {
Jason Wang48d7d0a2012-06-17 22:52:09 +00001009 { PHY_ID_KSZ9021, 0x000ffffe },
Fabio Estevamf893a992016-05-11 17:02:05 -03001010 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
Alexander Steinecd5a322016-07-29 12:12:08 +02001011 { PHY_ID_KSZ8001, 0x00fffffc },
Fabio Estevamf893a992016-05-11 17:02:05 -03001012 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
Marek Vasut212ea992012-09-23 16:58:49 +00001013 { PHY_ID_KSZ8021, 0x00ffffff },
Hector Palaciosb818d1a2013-03-10 22:50:02 +00001014 { PHY_ID_KSZ8031, 0x00ffffff },
Fabio Estevamf893a992016-05-11 17:02:05 -03001015 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1016 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1017 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1018 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1019 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1020 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
David S. Miller52a60ed2010-05-03 15:48:29 -07001021 { }
1022};
1023
1024MODULE_DEVICE_TABLE(mdio, micrel_tbl);