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Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -05001/*
2 * CXL Flash Device Driver
3 *
4 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
5 * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
6 *
7 * Copyright (C) 2015 IBM Corporation
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#ifndef _CXLFLASH_COMMON_H
16#define _CXLFLASH_COMMON_H
17
Matthew R. Ochscba06e62017-04-12 14:13:20 -050018#include <linux/irq_poll.h>
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050019#include <linux/list.h>
Matthew R. Ochs0a27ae52015-10-21 15:11:52 -050020#include <linux/rwsem.h>
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050021#include <linux/types.h>
22#include <scsi/scsi.h>
Matthew R. Ochs5fbb96c2016-11-28 18:42:19 -060023#include <scsi/scsi_cmnd.h>
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050024#include <scsi/scsi_device.h>
25
Matthew R. Ochs17ead262015-10-21 15:15:37 -050026extern const struct file_operations cxlflash_cxl_fops;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050027
Matthew R. Ochs78ae0282017-04-12 14:13:50 -050028#define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */
Matthew R. Ochs565180722017-04-12 14:14:28 -050029#define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */
30#define LEGACY_FC_PORTS 2 /* legacy ports per AFU */
31
32#define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
33#define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050034
Matthew R. Ochs8fa4f172017-04-12 14:14:05 -050035#define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */
36#define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */
37#define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */
38
Matthew R. Ochsfcc87e72017-04-12 14:15:20 -050039#define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050040#define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */
41#define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants
Matthew R. Ochsfcc87e72017-04-12 14:15:20 -050042 * max_sectors
43 * in units of
44 * 512 byte
45 * sectors
46 */
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050047
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050048#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
49
50/* AFU command retry limit */
Matthew R. Ochsfcc87e72017-04-12 14:15:20 -050051#define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050052
53/* Command management definitions */
Manoj N. Kumar83430832016-03-04 15:55:20 -060054#define CXLFLASH_MAX_CMDS 256
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050055#define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS
56
Manoj N. Kumar83430832016-03-04 15:55:20 -060057/* RRQ for master issued cmds */
58#define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS
59
Matthew R. Ochs696d0b02017-01-11 19:19:33 -060060/* SQ for master issued cmds */
61#define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS
62
Matthew R. Ochs30652672017-04-12 14:15:53 -050063/* Hardware queue definitions */
64#define CXLFLASH_DEF_HWQS 1
65#define CXLFLASH_MAX_HWQS 8
Uma Krishnanbfc0bab2017-04-12 14:15:42 -050066#define PRIMARY_HWQ 0
67
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050068
69static inline void check_sizes(void)
70{
Matthew R. Ochs565180722017-04-12 14:14:28 -050071 BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
Matthew R. Ochscd41e182017-04-12 14:15:11 -050072 BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050073}
74
75/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
76#define CMD_BUFSIZE SIZE_4K
77
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050078enum cxlflash_lr_state {
79 LINK_RESET_INVALID,
80 LINK_RESET_REQUIRED,
81 LINK_RESET_COMPLETE
82};
83
84enum cxlflash_init_state {
85 INIT_STATE_NONE,
86 INIT_STATE_PCI,
87 INIT_STATE_AFU,
88 INIT_STATE_SCSI
89};
90
Matthew R. Ochs5cdac812015-08-13 21:47:34 -050091enum cxlflash_state {
Matthew R. Ochs323e3342017-04-12 14:14:51 -050092 STATE_PROBING, /* Initial state during probe */
93 STATE_PROBED, /* Temporary state, probe completed but EEH occurred */
Matthew R. Ochs5cdac812015-08-13 21:47:34 -050094 STATE_NORMAL, /* Normal running state, everything good */
Matthew R. Ochs439e85c2015-10-21 15:12:00 -050095 STATE_RESET, /* Reset state, trying to reset/recover */
Matthew R. Ochs5cdac812015-08-13 21:47:34 -050096 STATE_FAILTERM /* Failed/terminating state, error out users/threads */
97};
98
Matthew R. Ochs1dd0c0e2017-04-12 14:16:02 -050099enum cxlflash_hwq_mode {
100 HWQ_MODE_RR, /* Roundrobin (default) */
101 HWQ_MODE_TAG, /* Distribute based on block MQ tag */
102 HWQ_MODE_CPU, /* CPU affinity */
103 MAX_HWQ_MODE
104};
105
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500106/*
107 * Each context has its own set of resource handles that is visible
108 * only from that context.
109 */
110
111struct cxlflash_cfg {
112 struct afu *afu;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500113
114 struct pci_dev *dev;
115 struct pci_device_id *dev_id;
116 struct Scsi_Host *host;
Matthew R. Ochs78ae0282017-04-12 14:13:50 -0500117 int num_fc_ports;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500118
119 ulong cxlflash_regs_pci;
120
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500121 struct work_struct work_q;
122 enum cxlflash_init_state init_state;
123 enum cxlflash_lr_state lr_state;
124 int lr_port;
Matthew R. Ochsef510742015-10-21 15:13:37 -0500125 atomic_t scan_host_needed;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500126
127 struct cxl_afu *cxl_afu;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500128
Matthew R. Ochs65be2c72015-08-13 21:47:43 -0500129 atomic_t recovery_threads;
130 struct mutex ctx_recovery_mutex;
131 struct mutex ctx_tbl_list_mutex;
Matthew R. Ochs0a27ae52015-10-21 15:11:52 -0500132 struct rw_semaphore ioctl_rwsem;
Matthew R. Ochs65be2c72015-08-13 21:47:43 -0500133 struct ctx_info *ctx_tbl[MAX_CONTEXT];
134 struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
135 struct file_operations cxl_fops;
136
Matthew R. Ochs2cb79262015-08-13 21:47:53 -0500137 /* Parameters that are LUN table related */
Matthew R. Ochs78ae0282017-04-12 14:13:50 -0500138 int last_lun_index[MAX_FC_PORTS];
Matthew R. Ochs2cb79262015-08-13 21:47:53 -0500139 int promote_lun_index;
Matthew R. Ochs65be2c72015-08-13 21:47:43 -0500140 struct list_head lluns; /* list of llun_info structs */
141
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500142 wait_queue_head_t tmf_waitq;
Matthew R. Ochs018d1dc952015-10-21 15:13:21 -0500143 spinlock_t tmf_slock;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500144 bool tmf_active;
Matthew R. Ochs439e85c2015-10-21 15:12:00 -0500145 wait_queue_head_t reset_waitq;
Matthew R. Ochs5cdac812015-08-13 21:47:34 -0500146 enum cxlflash_state state;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500147};
148
149struct afu_cmd {
150 struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */
151 struct sisl_ioasa sa; /* IOASA must follow IOARCB */
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500152 struct afu *parent;
Matthew R. Ochsfe7f9692016-11-28 18:43:18 -0600153 struct scsi_cmnd *scp;
Matthew R. Ochs9ba848a2016-11-28 18:42:42 -0600154 struct completion cevent;
Matthew R. Ochsf918b4a2017-04-12 14:12:55 -0500155 struct list_head queue;
Matthew R. Ochs1dd0c0e2017-04-12 14:16:02 -0500156 u32 hwq_index;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500157
158 u8 cmd_tmf:1;
159
160 /* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
161 * However for performance reasons the IOARCB/IOASA should be
162 * cache line aligned.
163 */
164} __aligned(cache_line_size());
165
Matthew R. Ochs5fbb96c2016-11-28 18:42:19 -0600166static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc)
167{
168 return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
169}
170
171static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc)
172{
173 struct afu_cmd *afuc = sc_to_afuc(sc);
174
175 memset(afuc, 0, sizeof(*afuc));
176 return afuc;
177}
178
Uma Krishnanbfc0bab2017-04-12 14:15:42 -0500179struct hwq {
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500180 /* Stuff requiring alignment go first. */
Matthew R. Ochs696d0b02017-01-11 19:19:33 -0600181 struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */
182 u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500183
184 /* Beware of alignment till here. Preferably introduce new
185 * fields after this point
186 */
Uma Krishnanbfc0bab2017-04-12 14:15:42 -0500187 struct afu *afu;
188 struct cxl_context *ctx;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500189 struct cxl_ioctl_start_work work;
Matthew R. Ochs1786f4a2015-10-21 15:14:48 -0500190 struct sisl_host_map __iomem *host_map; /* MC host map */
191 struct sisl_ctrl_map __iomem *ctrl_map; /* MC control map */
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500192 ctx_hndl_t ctx_hndl; /* master's context handle */
Uma Krishnanbfc0bab2017-04-12 14:15:42 -0500193 u32 index; /* Index of this hwq */
Matthew R. Ochs696d0b02017-01-11 19:19:33 -0600194
195 atomic_t hsq_credits;
196 spinlock_t hsq_slock;
197 struct sisl_ioarcb *hsq_start;
198 struct sisl_ioarcb *hsq_end;
199 struct sisl_ioarcb *hsq_curr;
Matthew R. Ochsf918b4a2017-04-12 14:12:55 -0500200 spinlock_t hrrq_slock;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500201 u64 *hrrq_start;
202 u64 *hrrq_end;
203 u64 *hrrq_curr;
204 bool toggle;
Uma Krishnanbfc0bab2017-04-12 14:15:42 -0500205
Uma Krishnan11f7b182016-11-28 18:41:45 -0600206 s64 room;
207 spinlock_t rrin_slock; /* Lock to rrin queuing and cmd_room updates */
Uma Krishnanbfc0bab2017-04-12 14:15:42 -0500208
209 struct irq_poll irqpoll;
210} __aligned(cache_line_size());
211
212struct afu {
Matthew R. Ochs30652672017-04-12 14:15:53 -0500213 struct hwq hwqs[CXLFLASH_MAX_HWQS];
Uma Krishnanbfc0bab2017-04-12 14:15:42 -0500214 int (*send_cmd)(struct afu *, struct afu_cmd *);
215 void (*context_reset)(struct afu_cmd *);
216
217 /* AFU HW */
218 struct cxlflash_afu_map __iomem *afu_map; /* entire MMIO map */
219
220 atomic_t cmds_active; /* Number of currently active AFU commands */
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500221 u64 hb;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500222 u32 internal_lun; /* User-desired LUN mode for this AFU */
Matthew R. Ochs1dd0c0e2017-04-12 14:16:02 -0500223
Matthew R. Ochs30652672017-04-12 14:15:53 -0500224 u32 num_hwqs; /* Number of hardware queues */
225 u32 desired_hwqs; /* Desired h/w queues, effective on AFU reset */
Matthew R. Ochs1dd0c0e2017-04-12 14:16:02 -0500226 enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */
227 u32 hwq_rr_count; /* Count to distribute traffic for roundrobin */
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500228
Matthew R. Ochse5ce0672015-10-21 15:14:01 -0500229 char version[16];
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500230 u64 interface_version;
231
Matthew R. Ochscba06e62017-04-12 14:13:20 -0500232 u32 irqpoll_weight;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500233 struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500234};
235
Uma Krishnanbfc0bab2017-04-12 14:15:42 -0500236static inline struct hwq *get_hwq(struct afu *afu, u32 index)
237{
Matthew R. Ochs30652672017-04-12 14:15:53 -0500238 WARN_ON(index >= CXLFLASH_MAX_HWQS);
Uma Krishnanbfc0bab2017-04-12 14:15:42 -0500239
240 return &afu->hwqs[index];
241}
242
Matthew R. Ochscba06e62017-04-12 14:13:20 -0500243static inline bool afu_is_irqpoll_enabled(struct afu *afu)
244{
245 return !!afu->irqpoll_weight;
246}
247
Matthew R. Ochs696d0b02017-01-11 19:19:33 -0600248static inline bool afu_is_cmd_mode(struct afu *afu, u64 cmd_mode)
249{
250 u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;
251
252 return afu_cap & cmd_mode;
253}
254
255static inline bool afu_is_sq_cmd_mode(struct afu *afu)
256{
257 return afu_is_cmd_mode(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
258}
259
260static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
261{
262 return afu_is_cmd_mode(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
263}
264
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500265static inline u64 lun_to_lunid(u64 lun)
266{
Matthew R. Ochs1786f4a2015-10-21 15:14:48 -0500267 __be64 lun_id;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500268
269 int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
Matthew R. Ochs1786f4a2015-10-21 15:14:48 -0500270 return be64_to_cpu(lun_id);
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500271}
272
Matthew R. Ochs565180722017-04-12 14:14:28 -0500273static inline struct fc_port_bank __iomem *get_fc_port_bank(
274 struct cxlflash_cfg *cfg, int i)
Matthew R. Ochs0aa148872017-04-12 14:14:17 -0500275{
276 struct afu *afu = cfg->afu;
277
Matthew R. Ochs565180722017-04-12 14:14:28 -0500278 return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
279}
280
281static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i)
282{
283 struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
284
285 return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
Matthew R. Ochs0aa148872017-04-12 14:14:17 -0500286}
287
288static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i)
289{
Matthew R. Ochs565180722017-04-12 14:14:28 -0500290 struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
Matthew R. Ochs0aa148872017-04-12 14:14:17 -0500291
Matthew R. Ochs565180722017-04-12 14:14:28 -0500292 return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
Matthew R. Ochs0aa148872017-04-12 14:14:17 -0500293}
294
Matthew R. Ochsfcc87e72017-04-12 14:15:20 -0500295int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
Matthew R. Ochs65be2c72015-08-13 21:47:43 -0500296void cxlflash_list_init(void);
297void cxlflash_term_global_luns(void);
298void cxlflash_free_errpage(void);
Matthew R. Ochsfcc87e72017-04-12 14:15:20 -0500299int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg);
300void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
301int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
302void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
303void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);
Matthew R. Ochs65be2c72015-08-13 21:47:43 -0500304
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500305#endif /* ifndef _CXLFLASH_COMMON_H */