| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-ep93xx/include/mach/hardware.h |
| 3 | */ |
| Hubert Feurstein | 43234b1 | 2009-11-17 18:10:48 +0100 | [diff] [blame^] | 4 | |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 5 | #ifndef __ASM_ARCH_HARDWARE_H |
| 6 | #define __ASM_ARCH_HARDWARE_H |
| 7 | |
| Hartley Sweeten | 583ddaf | 2009-07-06 17:39:50 +0100 | [diff] [blame] | 8 | #include <mach/ep93xx-regs.h> |
| 9 | #include <mach/platform.h> |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 10 | |
| 11 | #define pcibios_assign_all_busses() 0 |
| 12 | |
| Hartley Sweeten | 701fac8 | 2009-06-30 23:06:43 +0100 | [diff] [blame] | 13 | /* |
| 14 | * The EP93xx has two external crystal oscillators. To generate the |
| 15 | * required high-frequency clocks, the processor uses two phase-locked- |
| 16 | * loops (PLLs) to multiply the incoming external clock signal to much |
| 17 | * higher frequencies that are then divided down by programmable dividers |
| 18 | * to produce the needed clocks. The PLLs operate independently of one |
| 19 | * another. |
| 20 | */ |
| 21 | #define EP93XX_EXT_CLK_RATE 14745600 |
| 22 | #define EP93XX_EXT_RTC_RATE 32768 |
| 23 | |
| 24 | #define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) |
| 25 | #define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) |
| 26 | |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #endif |