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Sathya Perla6b7c5b92009-03-11 23:32:03 -07001/*
Ajit Khaparded2145cd2011-03-16 08:20:46 +00002 * Copyright (C) 2005 - 2011 Emulex
Sathya Perla6b7c5b92009-03-11 23:32:03 -07003 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
Ajit Khaparded2145cd2011-03-16 08:20:46 +000011 * linux-drivers@emulex.com
Sathya Perla6b7c5b92009-03-11 23:32:03 -070012 *
Ajit Khaparded2145cd2011-03-16 08:20:46 +000013 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
Sathya Perla6b7c5b92009-03-11 23:32:03 -070016 */
17
18#include "be.h"
Sathya Perla8788fdc2009-07-27 22:52:03 +000019#include "be_cmds.h"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070020
Ajit Khaparde609ff3b2011-02-20 11:42:07 +000021/* Must be a power of 2 or else MODULO will BUG_ON */
Somnath Kotur3de09452011-09-30 07:25:05 +000022static int be_get_temp_freq = 64;
23
24static inline void *embedded_payload(struct be_mcc_wrb *wrb)
25{
26 return wrb->payload.embedded_payload;
27}
Ajit Khaparde609ff3b2011-02-20 11:42:07 +000028
Sathya Perla8788fdc2009-07-27 22:52:03 +000029static void be_mcc_notify(struct be_adapter *adapter)
Sathya Perla5fb379e2009-06-18 00:02:59 +000030{
Sathya Perla8788fdc2009-07-27 22:52:03 +000031 struct be_queue_info *mccq = &adapter->mcc_obj.q;
Sathya Perla5fb379e2009-06-18 00:02:59 +000032 u32 val = 0;
33
Sathya Perla434b3642011-11-10 19:17:59 +000034 if (adapter->eeh_err)
Ajit Khaparde7acc2082011-02-11 13:38:17 +000035 return;
Ajit Khaparde7acc2082011-02-11 13:38:17 +000036
Sathya Perla5fb379e2009-06-18 00:02:59 +000037 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
38 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
Sathya Perlaf3eb62d2010-06-29 00:11:17 +000039
40 wmb();
Sathya Perla8788fdc2009-07-27 22:52:03 +000041 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
Sathya Perla5fb379e2009-06-18 00:02:59 +000042}
43
44/* To check if valid bit is set, check the entire word as we don't know
45 * the endianness of the data (old entry is host endian while a new entry is
46 * little endian) */
Sathya Perlaefd2e402009-07-27 22:53:10 +000047static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
Sathya Perla5fb379e2009-06-18 00:02:59 +000048{
49 if (compl->flags != 0) {
50 compl->flags = le32_to_cpu(compl->flags);
51 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
52 return true;
53 } else {
54 return false;
55 }
56}
57
58/* Need to reset the entire word that houses the valid bit */
Sathya Perlaefd2e402009-07-27 22:53:10 +000059static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
Sathya Perla5fb379e2009-06-18 00:02:59 +000060{
61 compl->flags = 0;
62}
63
Sathya Perla8788fdc2009-07-27 22:52:03 +000064static int be_mcc_compl_process(struct be_adapter *adapter,
Sathya Perlaefd2e402009-07-27 22:53:10 +000065 struct be_mcc_compl *compl)
Sathya Perla5fb379e2009-06-18 00:02:59 +000066{
67 u16 compl_status, extd_status;
68
69 /* Just swap the status to host endian; mcc tag is opaquely copied
70 * from mcc_wrb */
71 be_dws_le_to_cpu(compl, 4);
72
73 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
74 CQE_STATUS_COMPL_MASK;
Sarveshwar Bandidd131e72010-05-25 16:16:32 -070075
Shripad Nunjundarao485bf562011-05-16 07:36:59 +000076 if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
77 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
Sarveshwar Bandidd131e72010-05-25 16:16:32 -070078 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
79 adapter->flash_status = compl_status;
80 complete(&adapter->flash_compl);
81 }
82
Sathya Perlab31c50a2009-09-17 10:30:13 -070083 if (compl_status == MCC_STATUS_SUCCESS) {
Selvin Xavier005d5692011-05-16 07:36:35 +000084 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
85 (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
Ajit Khaparde63499352011-04-19 12:11:02 +000086 (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
Ajit Khaparde89a88ab2011-05-16 07:36:18 +000087 be_parse_stats(adapter);
Ajit Khapardeb2aebe62011-02-20 11:41:39 +000088 adapter->stats_cmd_sent = false;
Sathya Perlab31c50a2009-09-17 10:30:13 -070089 }
Somnath Kotur3de09452011-09-30 07:25:05 +000090 if (compl->tag0 ==
91 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) {
92 struct be_mcc_wrb *mcc_wrb =
93 queue_index_node(&adapter->mcc_obj.q,
94 compl->tag1);
95 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
96 embedded_payload(mcc_wrb);
97 adapter->drv_stats.be_on_die_temperature =
98 resp->on_die_temperature;
99 }
Sathya Perla2b3f2912011-06-29 23:32:56 +0000100 } else {
Somnath Kotur3de09452011-09-30 07:25:05 +0000101 if (compl->tag0 == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
102 be_get_temp_freq = 0;
103
Sathya Perla2b3f2912011-06-29 23:32:56 +0000104 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
105 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
106 goto done;
107
108 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
109 dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
110 "permitted to execute this cmd (opcode %d)\n",
111 compl->tag0);
112 } else {
113 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
114 CQE_STATUS_EXTD_MASK;
115 dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
116 "status %d, extd-status %d\n",
117 compl->tag0, compl_status, extd_status);
118 }
Sathya Perla5fb379e2009-06-18 00:02:59 +0000119 }
Sathya Perla2b3f2912011-06-29 23:32:56 +0000120done:
Sathya Perlab31c50a2009-09-17 10:30:13 -0700121 return compl_status;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000122}
123
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000124/* Link state evt is a string of bytes; no need for endian swapping */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000125static void be_async_link_state_process(struct be_adapter *adapter,
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000126 struct be_async_event_link_state *evt)
127{
Sathya Perlaea172a02011-08-02 19:57:42 +0000128 be_link_status_update(adapter, evt->port_link_status);
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000129}
130
Somnath Koturcc4ce022010-10-21 07:11:14 -0700131/* Grp5 CoS Priority evt */
132static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
133 struct be_async_event_grp5_cos_priority *evt)
134{
135 if (evt->valid) {
136 adapter->vlan_prio_bmap = evt->available_priority_bmap;
Ajit Khaparde60964dd2011-02-11 13:37:25 +0000137 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
Somnath Koturcc4ce022010-10-21 07:11:14 -0700138 adapter->recommended_prio =
139 evt->reco_default_priority << VLAN_PRIO_SHIFT;
140 }
141}
142
143/* Grp5 QOS Speed evt */
144static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
145 struct be_async_event_grp5_qos_link_speed *evt)
146{
147 if (evt->physical_port == adapter->port_num) {
148 /* qos_link_speed is in units of 10 Mbps */
149 adapter->link_speed = evt->qos_link_speed * 10;
150 }
151}
152
Ajit Khaparde3968fa12011-02-20 11:41:53 +0000153/*Grp5 PVID evt*/
154static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
155 struct be_async_event_grp5_pvid_state *evt)
156{
157 if (evt->enabled)
Somnath Kotur939cf302011-08-18 21:51:49 -0700158 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
Ajit Khaparde3968fa12011-02-20 11:41:53 +0000159 else
160 adapter->pvid = 0;
161}
162
Somnath Koturcc4ce022010-10-21 07:11:14 -0700163static void be_async_grp5_evt_process(struct be_adapter *adapter,
164 u32 trailer, struct be_mcc_compl *evt)
165{
166 u8 event_type = 0;
167
168 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
169 ASYNC_TRAILER_EVENT_TYPE_MASK;
170
171 switch (event_type) {
172 case ASYNC_EVENT_COS_PRIORITY:
173 be_async_grp5_cos_priority_process(adapter,
174 (struct be_async_event_grp5_cos_priority *)evt);
175 break;
176 case ASYNC_EVENT_QOS_SPEED:
177 be_async_grp5_qos_speed_process(adapter,
178 (struct be_async_event_grp5_qos_link_speed *)evt);
179 break;
Ajit Khaparde3968fa12011-02-20 11:41:53 +0000180 case ASYNC_EVENT_PVID_STATE:
181 be_async_grp5_pvid_state_process(adapter,
182 (struct be_async_event_grp5_pvid_state *)evt);
183 break;
Somnath Koturcc4ce022010-10-21 07:11:14 -0700184 default:
185 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
186 break;
187 }
188}
189
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000190static inline bool is_link_state_evt(u32 trailer)
191{
Eric Dumazet807540b2010-09-23 05:40:09 +0000192 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000193 ASYNC_TRAILER_EVENT_CODE_MASK) ==
Eric Dumazet807540b2010-09-23 05:40:09 +0000194 ASYNC_EVENT_CODE_LINK_STATE;
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000195}
Sathya Perla5fb379e2009-06-18 00:02:59 +0000196
Somnath Koturcc4ce022010-10-21 07:11:14 -0700197static inline bool is_grp5_evt(u32 trailer)
198{
199 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
200 ASYNC_TRAILER_EVENT_CODE_MASK) ==
201 ASYNC_EVENT_CODE_GRP_5);
202}
203
Sathya Perlaefd2e402009-07-27 22:53:10 +0000204static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
Sathya Perla5fb379e2009-06-18 00:02:59 +0000205{
Sathya Perla8788fdc2009-07-27 22:52:03 +0000206 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
Sathya Perlaefd2e402009-07-27 22:53:10 +0000207 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
Sathya Perla5fb379e2009-06-18 00:02:59 +0000208
209 if (be_mcc_compl_is_new(compl)) {
210 queue_tail_inc(mcc_cq);
211 return compl;
212 }
213 return NULL;
214}
215
Sathya Perla7a1e9b22010-02-17 01:35:11 +0000216void be_async_mcc_enable(struct be_adapter *adapter)
217{
218 spin_lock_bh(&adapter->mcc_cq_lock);
219
220 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
221 adapter->mcc_obj.rearm_cq = true;
222
223 spin_unlock_bh(&adapter->mcc_cq_lock);
224}
225
226void be_async_mcc_disable(struct be_adapter *adapter)
227{
228 adapter->mcc_obj.rearm_cq = false;
229}
230
Sathya Perlaf31e50a2010-03-02 03:56:39 -0800231int be_process_mcc(struct be_adapter *adapter, int *status)
Sathya Perla5fb379e2009-06-18 00:02:59 +0000232{
Sathya Perlaefd2e402009-07-27 22:53:10 +0000233 struct be_mcc_compl *compl;
Sathya Perlaf31e50a2010-03-02 03:56:39 -0800234 int num = 0;
Sathya Perla7a1e9b22010-02-17 01:35:11 +0000235 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000236
Sathya Perla8788fdc2009-07-27 22:52:03 +0000237 spin_lock_bh(&adapter->mcc_cq_lock);
238 while ((compl = be_mcc_compl_get(adapter))) {
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000239 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
240 /* Interpret flags as an async trailer */
Ajit Khaparde323f30b2010-09-03 06:24:13 +0000241 if (is_link_state_evt(compl->flags))
242 be_async_link_state_process(adapter,
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000243 (struct be_async_event_link_state *) compl);
Somnath Koturcc4ce022010-10-21 07:11:14 -0700244 else if (is_grp5_evt(compl->flags))
245 be_async_grp5_evt_process(adapter,
246 compl->flags, compl);
Sathya Perlab31c50a2009-09-17 10:30:13 -0700247 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
Sathya Perlaf31e50a2010-03-02 03:56:39 -0800248 *status = be_mcc_compl_process(adapter, compl);
Sathya Perla7a1e9b22010-02-17 01:35:11 +0000249 atomic_dec(&mcc_obj->q.used);
Sathya Perla5fb379e2009-06-18 00:02:59 +0000250 }
251 be_mcc_compl_use(compl);
252 num++;
253 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700254
Sathya Perla8788fdc2009-07-27 22:52:03 +0000255 spin_unlock_bh(&adapter->mcc_cq_lock);
Sathya Perlaf31e50a2010-03-02 03:56:39 -0800256 return num;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000257}
258
Sathya Perla6ac7b682009-06-18 00:05:54 +0000259/* Wait till no more pending mcc requests are present */
Sathya Perlab31c50a2009-09-17 10:30:13 -0700260static int be_mcc_wait_compl(struct be_adapter *adapter)
Sathya Perla6ac7b682009-06-18 00:05:54 +0000261{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700262#define mcc_timeout 120000 /* 12s timeout */
Sathya Perlaf31e50a2010-03-02 03:56:39 -0800263 int i, num, status = 0;
264 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
Sathya Perlab31c50a2009-09-17 10:30:13 -0700265
Ajit Khaparde7acc2082011-02-11 13:38:17 +0000266 if (adapter->eeh_err)
267 return -EIO;
268
Sathya Perlaf31e50a2010-03-02 03:56:39 -0800269 for (i = 0; i < mcc_timeout; i++) {
270 num = be_process_mcc(adapter, &status);
271 if (num)
272 be_cq_notify(adapter, mcc_obj->cq.id,
273 mcc_obj->rearm_cq, num);
274
275 if (atomic_read(&mcc_obj->q.used) == 0)
Sathya Perla6ac7b682009-06-18 00:05:54 +0000276 break;
277 udelay(100);
278 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700279 if (i == mcc_timeout) {
Sathya Perla5f0b8492009-07-27 22:52:56 +0000280 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
Sathya Perlab31c50a2009-09-17 10:30:13 -0700281 return -1;
282 }
Sathya Perlaf31e50a2010-03-02 03:56:39 -0800283 return status;
Sathya Perla6ac7b682009-06-18 00:05:54 +0000284}
285
286/* Notify MCC requests and wait for completion */
Sathya Perlab31c50a2009-09-17 10:30:13 -0700287static int be_mcc_notify_wait(struct be_adapter *adapter)
Sathya Perla6ac7b682009-06-18 00:05:54 +0000288{
Sathya Perla8788fdc2009-07-27 22:52:03 +0000289 be_mcc_notify(adapter);
Sathya Perlab31c50a2009-09-17 10:30:13 -0700290 return be_mcc_wait_compl(adapter);
Sathya Perla6ac7b682009-06-18 00:05:54 +0000291}
292
Sathya Perla5f0b8492009-07-27 22:52:56 +0000293static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700294{
Sathya Perlaf25b03a2010-05-30 23:34:14 +0000295 int msecs = 0;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700296 u32 ready;
297
Sathya Perla434b3642011-11-10 19:17:59 +0000298 if (adapter->eeh_err)
Ajit Khaparde7acc2082011-02-11 13:38:17 +0000299 return -EIO;
Ajit Khaparde7acc2082011-02-11 13:38:17 +0000300
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700301 do {
Sathya Perlacf588472010-02-14 21:22:01 +0000302 ready = ioread32(db);
Sathya Perla434b3642011-11-10 19:17:59 +0000303 if (ready == 0xffffffff)
Sathya Perlacf588472010-02-14 21:22:01 +0000304 return -1;
Sathya Perlacf588472010-02-14 21:22:01 +0000305
306 ready &= MPU_MAILBOX_DB_RDY_MASK;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700307 if (ready)
308 break;
309
Sathya Perlaf25b03a2010-05-30 23:34:14 +0000310 if (msecs > 4000) {
Sathya Perla5f0b8492009-07-27 22:52:56 +0000311 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
Padmanabh Ratnakare1cfb672011-11-03 01:50:08 +0000312 be_detect_dump_ue(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700313 return -1;
314 }
315
Sathya Perla1dbf53a2011-05-12 19:32:16 +0000316 msleep(1);
Sathya Perlaf25b03a2010-05-30 23:34:14 +0000317 msecs++;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700318 } while (true);
319
320 return 0;
321}
322
323/*
324 * Insert the mailbox address into the doorbell in two steps
Sathya Perla5fb379e2009-06-18 00:02:59 +0000325 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700326 */
Sathya Perlab31c50a2009-09-17 10:30:13 -0700327static int be_mbox_notify_wait(struct be_adapter *adapter)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700328{
329 int status;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700330 u32 val = 0;
Sathya Perla8788fdc2009-07-27 22:52:03 +0000331 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
332 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700333 struct be_mcc_mailbox *mbox = mbox_mem->va;
Sathya Perlaefd2e402009-07-27 22:53:10 +0000334 struct be_mcc_compl *compl = &mbox->compl;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700335
Sathya Perlacf588472010-02-14 21:22:01 +0000336 /* wait for ready to be set */
337 status = be_mbox_db_ready_wait(adapter, db);
338 if (status != 0)
339 return status;
340
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700341 val |= MPU_MAILBOX_DB_HI_MASK;
342 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
343 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
344 iowrite32(val, db);
345
346 /* wait for ready to be set */
Sathya Perla5f0b8492009-07-27 22:52:56 +0000347 status = be_mbox_db_ready_wait(adapter, db);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700348 if (status != 0)
349 return status;
350
351 val = 0;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700352 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
353 val |= (u32)(mbox_mem->dma >> 4) << 2;
354 iowrite32(val, db);
355
Sathya Perla5f0b8492009-07-27 22:52:56 +0000356 status = be_mbox_db_ready_wait(adapter, db);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700357 if (status != 0)
358 return status;
359
Sathya Perla5fb379e2009-06-18 00:02:59 +0000360 /* A cq entry has been made now */
Sathya Perlaefd2e402009-07-27 22:53:10 +0000361 if (be_mcc_compl_is_new(compl)) {
362 status = be_mcc_compl_process(adapter, &mbox->compl);
363 be_mcc_compl_use(compl);
Sathya Perla5fb379e2009-06-18 00:02:59 +0000364 if (status)
365 return status;
366 } else {
Sathya Perla5f0b8492009-07-27 22:52:56 +0000367 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700368 return -1;
369 }
Sathya Perla5fb379e2009-06-18 00:02:59 +0000370 return 0;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700371}
372
Sathya Perla8788fdc2009-07-27 22:52:03 +0000373static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700374{
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000375 u32 sem;
376
377 if (lancer_chip(adapter))
378 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
379 else
380 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700381
382 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
383 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
384 return -1;
385 else
386 return 0;
387}
388
Sathya Perla8788fdc2009-07-27 22:52:03 +0000389int be_cmd_POST(struct be_adapter *adapter)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700390{
Sathya Perla43a04fdc2009-10-14 20:21:17 +0000391 u16 stage;
392 int status, timeout = 0;
Sathya Perla6ed35ee2011-05-12 19:32:15 +0000393 struct device *dev = &adapter->pdev->dev;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700394
Sathya Perla43a04fdc2009-10-14 20:21:17 +0000395 do {
396 status = be_POST_stage_get(adapter, &stage);
397 if (status) {
Sathya Perla6ed35ee2011-05-12 19:32:15 +0000398 dev_err(dev, "POST error; stage=0x%x\n", stage);
Sathya Perla43a04fdc2009-10-14 20:21:17 +0000399 return -1;
400 } else if (stage != POST_STAGE_ARMFW_RDY) {
Sathya Perla6ed35ee2011-05-12 19:32:15 +0000401 if (msleep_interruptible(2000)) {
402 dev_err(dev, "Waiting for POST aborted\n");
403 return -EINTR;
404 }
Sathya Perla43a04fdc2009-10-14 20:21:17 +0000405 timeout += 2;
406 } else {
407 return 0;
408 }
Somnath Kotur3ab81b52011-10-03 08:10:57 +0000409 } while (timeout < 60);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700410
Sathya Perla6ed35ee2011-05-12 19:32:15 +0000411 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
Sathya Perla43a04fdc2009-10-14 20:21:17 +0000412 return -1;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700413}
414
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700415
416static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
417{
418 return &wrb->payload.sgl[0];
419}
420
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700421
422/* Don't touch the hdr after it's prepared */
Somnath Kotur106df1e2011-10-27 07:12:13 +0000423/* mem will be NULL for embedded commands */
424static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
425 u8 subsystem, u8 opcode, int cmd_len,
426 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700427{
Somnath Kotur106df1e2011-10-27 07:12:13 +0000428 struct be_sge *sge;
429
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700430 req_hdr->opcode = opcode;
431 req_hdr->subsystem = subsystem;
432 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
Ajit Khaparde07793d32010-02-16 00:18:46 +0000433 req_hdr->version = 0;
Somnath Kotur106df1e2011-10-27 07:12:13 +0000434
435 wrb->tag0 = opcode;
436 wrb->tag1 = subsystem;
437 wrb->payload_length = cmd_len;
438 if (mem) {
439 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
440 MCC_WRB_SGE_CNT_SHIFT;
441 sge = nonembedded_sgl(wrb);
442 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
443 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
444 sge->len = cpu_to_le32(mem->size);
445 } else
446 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
447 be_dws_cpu_to_le(wrb, 8);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700448}
449
450static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
451 struct be_dma_mem *mem)
452{
453 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
454 u64 dma = (u64)mem->dma;
455
456 for (i = 0; i < buf_pages; i++) {
457 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
458 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
459 dma += PAGE_SIZE_4K;
460 }
461}
462
463/* Converts interrupt delay in microseconds to multiplier value */
464static u32 eq_delay_to_mult(u32 usec_delay)
465{
466#define MAX_INTR_RATE 651042
467 const u32 round = 10;
468 u32 multiplier;
469
470 if (usec_delay == 0)
471 multiplier = 0;
472 else {
473 u32 interrupt_rate = 1000000 / usec_delay;
474 /* Max delay, corresponding to the lowest interrupt rate */
475 if (interrupt_rate == 0)
476 multiplier = 1023;
477 else {
478 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
479 multiplier /= interrupt_rate;
480 /* Round the multiplier to the closest value.*/
481 multiplier = (multiplier + round/2) / round;
482 multiplier = min(multiplier, (u32)1023);
483 }
484 }
485 return multiplier;
486}
487
Sathya Perlab31c50a2009-09-17 10:30:13 -0700488static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700489{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700490 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
491 struct be_mcc_wrb *wrb
492 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
493 memset(wrb, 0, sizeof(*wrb));
494 return wrb;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700495}
496
Sathya Perlab31c50a2009-09-17 10:30:13 -0700497static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
Sathya Perla5fb379e2009-06-18 00:02:59 +0000498{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700499 struct be_queue_info *mccq = &adapter->mcc_obj.q;
500 struct be_mcc_wrb *wrb;
501
Sathya Perla713d03942009-11-22 22:02:45 +0000502 if (atomic_read(&mccq->used) >= mccq->len) {
503 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
504 return NULL;
505 }
506
Sathya Perlab31c50a2009-09-17 10:30:13 -0700507 wrb = queue_head_node(mccq);
508 queue_head_inc(mccq);
509 atomic_inc(&mccq->used);
510 memset(wrb, 0, sizeof(*wrb));
Sathya Perla5fb379e2009-06-18 00:02:59 +0000511 return wrb;
512}
513
Sathya Perla2243e2e2009-11-22 22:02:03 +0000514/* Tell fw we're about to start firing cmds by writing a
515 * special pattern across the wrb hdr; uses mbox
516 */
517int be_cmd_fw_init(struct be_adapter *adapter)
518{
519 u8 *wrb;
520 int status;
521
Ivan Vecera29849612010-12-14 05:43:19 +0000522 if (mutex_lock_interruptible(&adapter->mbox_lock))
523 return -1;
Sathya Perla2243e2e2009-11-22 22:02:03 +0000524
525 wrb = (u8 *)wrb_from_mbox(adapter);
Sathya Perla359a9722010-12-01 01:03:36 +0000526 *wrb++ = 0xFF;
527 *wrb++ = 0x12;
528 *wrb++ = 0x34;
529 *wrb++ = 0xFF;
530 *wrb++ = 0xFF;
531 *wrb++ = 0x56;
532 *wrb++ = 0x78;
533 *wrb = 0xFF;
Sathya Perla2243e2e2009-11-22 22:02:03 +0000534
535 status = be_mbox_notify_wait(adapter);
536
Ivan Vecera29849612010-12-14 05:43:19 +0000537 mutex_unlock(&adapter->mbox_lock);
Sathya Perla2243e2e2009-11-22 22:02:03 +0000538 return status;
539}
540
541/* Tell fw we're done with firing cmds by writing a
542 * special pattern across the wrb hdr; uses mbox
543 */
544int be_cmd_fw_clean(struct be_adapter *adapter)
545{
546 u8 *wrb;
547 int status;
548
Sathya Perlacf588472010-02-14 21:22:01 +0000549 if (adapter->eeh_err)
550 return -EIO;
551
Ivan Vecera29849612010-12-14 05:43:19 +0000552 if (mutex_lock_interruptible(&adapter->mbox_lock))
553 return -1;
Sathya Perla2243e2e2009-11-22 22:02:03 +0000554
555 wrb = (u8 *)wrb_from_mbox(adapter);
556 *wrb++ = 0xFF;
557 *wrb++ = 0xAA;
558 *wrb++ = 0xBB;
559 *wrb++ = 0xFF;
560 *wrb++ = 0xFF;
561 *wrb++ = 0xCC;
562 *wrb++ = 0xDD;
563 *wrb = 0xFF;
564
565 status = be_mbox_notify_wait(adapter);
566
Ivan Vecera29849612010-12-14 05:43:19 +0000567 mutex_unlock(&adapter->mbox_lock);
Sathya Perla2243e2e2009-11-22 22:02:03 +0000568 return status;
569}
Sathya Perla8788fdc2009-07-27 22:52:03 +0000570int be_cmd_eq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700571 struct be_queue_info *eq, int eq_delay)
572{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700573 struct be_mcc_wrb *wrb;
574 struct be_cmd_req_eq_create *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700575 struct be_dma_mem *q_mem = &eq->dma_mem;
576 int status;
577
Ivan Vecera29849612010-12-14 05:43:19 +0000578 if (mutex_lock_interruptible(&adapter->mbox_lock))
579 return -1;
Sathya Perlab31c50a2009-09-17 10:30:13 -0700580
581 wrb = wrb_from_mbox(adapter);
582 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700583
Somnath Kotur106df1e2011-10-27 07:12:13 +0000584 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
585 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700586
587 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
588
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700589 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
590 /* 4byte eqe*/
591 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
592 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
593 __ilog2_u32(eq->len/256));
594 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
595 eq_delay_to_mult(eq_delay));
596 be_dws_cpu_to_le(req->context, sizeof(req->context));
597
598 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
599
Sathya Perlab31c50a2009-09-17 10:30:13 -0700600 status = be_mbox_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700601 if (!status) {
Sathya Perlab31c50a2009-09-17 10:30:13 -0700602 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700603 eq->id = le16_to_cpu(resp->eq_id);
604 eq->created = true;
605 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700606
Ivan Vecera29849612010-12-14 05:43:19 +0000607 mutex_unlock(&adapter->mbox_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700608 return status;
609}
610
Sathya Perlaf9449ab2011-10-24 02:45:01 +0000611/* Use MCC */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000612int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700613 u8 type, bool permanent, u32 if_handle)
614{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700615 struct be_mcc_wrb *wrb;
616 struct be_cmd_req_mac_query *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700617 int status;
618
Sathya Perlaf9449ab2011-10-24 02:45:01 +0000619 spin_lock_bh(&adapter->mcc_lock);
Sathya Perlab31c50a2009-09-17 10:30:13 -0700620
Sathya Perlaf9449ab2011-10-24 02:45:01 +0000621 wrb = wrb_from_mccq(adapter);
622 if (!wrb) {
623 status = -EBUSY;
624 goto err;
625 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700626 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700627
Somnath Kotur106df1e2011-10-27 07:12:13 +0000628 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
629 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700630 req->type = type;
631 if (permanent) {
632 req->permanent = 1;
633 } else {
Sathya Perlab31c50a2009-09-17 10:30:13 -0700634 req->if_id = cpu_to_le16((u16) if_handle);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700635 req->permanent = 0;
636 }
637
Sathya Perlaf9449ab2011-10-24 02:45:01 +0000638 status = be_mcc_notify_wait(adapter);
Sathya Perlab31c50a2009-09-17 10:30:13 -0700639 if (!status) {
640 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700641 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
Sathya Perlab31c50a2009-09-17 10:30:13 -0700642 }
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700643
Sathya Perlaf9449ab2011-10-24 02:45:01 +0000644err:
645 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700646 return status;
647}
648
Sathya Perlab31c50a2009-09-17 10:30:13 -0700649/* Uses synchronous MCCQ */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000650int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
Ajit Khapardef8617e02011-02-11 13:36:37 +0000651 u32 if_id, u32 *pmac_id, u32 domain)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700652{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700653 struct be_mcc_wrb *wrb;
654 struct be_cmd_req_pmac_add *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700655 int status;
656
Sathya Perlab31c50a2009-09-17 10:30:13 -0700657 spin_lock_bh(&adapter->mcc_lock);
658
659 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +0000660 if (!wrb) {
661 status = -EBUSY;
662 goto err;
663 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700664 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700665
Somnath Kotur106df1e2011-10-27 07:12:13 +0000666 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
667 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700668
Ajit Khapardef8617e02011-02-11 13:36:37 +0000669 req->hdr.domain = domain;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700670 req->if_id = cpu_to_le32(if_id);
671 memcpy(req->mac_address, mac_addr, ETH_ALEN);
672
Sathya Perlab31c50a2009-09-17 10:30:13 -0700673 status = be_mcc_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700674 if (!status) {
675 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
676 *pmac_id = le32_to_cpu(resp->pmac_id);
677 }
678
Sathya Perla713d03942009-11-22 22:02:45 +0000679err:
Sathya Perlab31c50a2009-09-17 10:30:13 -0700680 spin_unlock_bh(&adapter->mcc_lock);
Somnath Koture3a7ae22011-10-27 07:14:05 +0000681
682 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
683 status = -EPERM;
684
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700685 return status;
686}
687
Sathya Perlab31c50a2009-09-17 10:30:13 -0700688/* Uses synchronous MCCQ */
Sathya Perla30128032011-11-10 19:17:57 +0000689int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700690{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700691 struct be_mcc_wrb *wrb;
692 struct be_cmd_req_pmac_del *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700693 int status;
694
Sathya Perla30128032011-11-10 19:17:57 +0000695 if (pmac_id == -1)
696 return 0;
697
Sathya Perlab31c50a2009-09-17 10:30:13 -0700698 spin_lock_bh(&adapter->mcc_lock);
699
700 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +0000701 if (!wrb) {
702 status = -EBUSY;
703 goto err;
704 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700705 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700706
Somnath Kotur106df1e2011-10-27 07:12:13 +0000707 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
708 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700709
Ajit Khapardef8617e02011-02-11 13:36:37 +0000710 req->hdr.domain = dom;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700711 req->if_id = cpu_to_le32(if_id);
712 req->pmac_id = cpu_to_le32(pmac_id);
713
Sathya Perlab31c50a2009-09-17 10:30:13 -0700714 status = be_mcc_notify_wait(adapter);
715
Sathya Perla713d03942009-11-22 22:02:45 +0000716err:
Sathya Perlab31c50a2009-09-17 10:30:13 -0700717 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700718 return status;
719}
720
Sathya Perlab31c50a2009-09-17 10:30:13 -0700721/* Uses Mbox */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000722int be_cmd_cq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700723 struct be_queue_info *cq, struct be_queue_info *eq,
724 bool sol_evts, bool no_delay, int coalesce_wm)
725{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700726 struct be_mcc_wrb *wrb;
727 struct be_cmd_req_cq_create *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700728 struct be_dma_mem *q_mem = &cq->dma_mem;
Sathya Perlab31c50a2009-09-17 10:30:13 -0700729 void *ctxt;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700730 int status;
731
Ivan Vecera29849612010-12-14 05:43:19 +0000732 if (mutex_lock_interruptible(&adapter->mbox_lock))
733 return -1;
Sathya Perlab31c50a2009-09-17 10:30:13 -0700734
735 wrb = wrb_from_mbox(adapter);
736 req = embedded_payload(wrb);
737 ctxt = &req->context;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700738
Somnath Kotur106df1e2011-10-27 07:12:13 +0000739 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
740 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700741
742 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000743 if (lancer_chip(adapter)) {
Padmanabh Ratnakar8b7756c2011-03-07 03:08:52 +0000744 req->hdr.version = 2;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000745 req->page_size = 1; /* 1 for 4K */
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000746 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
747 no_delay);
748 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
749 __ilog2_u32(cq->len/256));
750 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
751 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
752 ctxt, 1);
753 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
754 ctxt, eq->id);
755 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
756 } else {
757 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
758 coalesce_wm);
759 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
760 ctxt, no_delay);
761 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
762 __ilog2_u32(cq->len/256));
763 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
764 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
765 ctxt, sol_evts);
766 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
767 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
768 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
769 }
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700770
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700771 be_dws_cpu_to_le(ctxt, sizeof(req->context));
772
773 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
774
Sathya Perlab31c50a2009-09-17 10:30:13 -0700775 status = be_mbox_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700776 if (!status) {
Sathya Perlab31c50a2009-09-17 10:30:13 -0700777 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700778 cq->id = le16_to_cpu(resp->cq_id);
779 cq->created = true;
780 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700781
Ivan Vecera29849612010-12-14 05:43:19 +0000782 mutex_unlock(&adapter->mbox_lock);
Sathya Perla5fb379e2009-06-18 00:02:59 +0000783
784 return status;
785}
786
787static u32 be_encoded_q_len(int q_len)
788{
789 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
790 if (len_encoded == 16)
791 len_encoded = 0;
792 return len_encoded;
793}
794
Somnath Kotur34b1ef02011-06-01 00:33:22 +0000795int be_cmd_mccq_ext_create(struct be_adapter *adapter,
Sathya Perla5fb379e2009-06-18 00:02:59 +0000796 struct be_queue_info *mccq,
797 struct be_queue_info *cq)
798{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700799 struct be_mcc_wrb *wrb;
Somnath Kotur34b1ef02011-06-01 00:33:22 +0000800 struct be_cmd_req_mcc_ext_create *req;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000801 struct be_dma_mem *q_mem = &mccq->dma_mem;
Sathya Perlab31c50a2009-09-17 10:30:13 -0700802 void *ctxt;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000803 int status;
804
Ivan Vecera29849612010-12-14 05:43:19 +0000805 if (mutex_lock_interruptible(&adapter->mbox_lock))
806 return -1;
Sathya Perlab31c50a2009-09-17 10:30:13 -0700807
808 wrb = wrb_from_mbox(adapter);
809 req = embedded_payload(wrb);
810 ctxt = &req->context;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000811
Somnath Kotur106df1e2011-10-27 07:12:13 +0000812 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
813 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
Sathya Perla5fb379e2009-06-18 00:02:59 +0000814
Ajit Khaparded4a2ac32010-03-11 01:35:59 +0000815 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000816 if (lancer_chip(adapter)) {
817 req->hdr.version = 1;
818 req->cq_id = cpu_to_le16(cq->id);
Sathya Perla5fb379e2009-06-18 00:02:59 +0000819
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000820 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
821 be_encoded_q_len(mccq->len));
822 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
823 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
824 ctxt, cq->id);
825 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
826 ctxt, 1);
827
828 } else {
829 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
830 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
831 be_encoded_q_len(mccq->len));
832 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
833 }
834
Somnath Koturcc4ce022010-10-21 07:11:14 -0700835 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000836 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
Sathya Perla5fb379e2009-06-18 00:02:59 +0000837 be_dws_cpu_to_le(ctxt, sizeof(req->context));
838
839 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
840
Sathya Perlab31c50a2009-09-17 10:30:13 -0700841 status = be_mbox_notify_wait(adapter);
Sathya Perla5fb379e2009-06-18 00:02:59 +0000842 if (!status) {
843 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
844 mccq->id = le16_to_cpu(resp->id);
845 mccq->created = true;
846 }
Ivan Vecera29849612010-12-14 05:43:19 +0000847 mutex_unlock(&adapter->mbox_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700848
849 return status;
850}
851
Somnath Kotur34b1ef02011-06-01 00:33:22 +0000852int be_cmd_mccq_org_create(struct be_adapter *adapter,
853 struct be_queue_info *mccq,
854 struct be_queue_info *cq)
855{
856 struct be_mcc_wrb *wrb;
857 struct be_cmd_req_mcc_create *req;
858 struct be_dma_mem *q_mem = &mccq->dma_mem;
859 void *ctxt;
860 int status;
861
862 if (mutex_lock_interruptible(&adapter->mbox_lock))
863 return -1;
864
865 wrb = wrb_from_mbox(adapter);
866 req = embedded_payload(wrb);
867 ctxt = &req->context;
868
Somnath Kotur106df1e2011-10-27 07:12:13 +0000869 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
870 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
Somnath Kotur34b1ef02011-06-01 00:33:22 +0000871
872 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
873
874 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
875 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
876 be_encoded_q_len(mccq->len));
877 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
878
879 be_dws_cpu_to_le(ctxt, sizeof(req->context));
880
881 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
882
883 status = be_mbox_notify_wait(adapter);
884 if (!status) {
885 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
886 mccq->id = le16_to_cpu(resp->id);
887 mccq->created = true;
888 }
889
890 mutex_unlock(&adapter->mbox_lock);
891 return status;
892}
893
894int be_cmd_mccq_create(struct be_adapter *adapter,
895 struct be_queue_info *mccq,
896 struct be_queue_info *cq)
897{
898 int status;
899
900 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
901 if (status && !lancer_chip(adapter)) {
902 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
903 "or newer to avoid conflicting priorities between NIC "
904 "and FCoE traffic");
905 status = be_cmd_mccq_org_create(adapter, mccq, cq);
906 }
907 return status;
908}
909
Sathya Perla8788fdc2009-07-27 22:52:03 +0000910int be_cmd_txq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700911 struct be_queue_info *txq,
912 struct be_queue_info *cq)
913{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700914 struct be_mcc_wrb *wrb;
915 struct be_cmd_req_eth_tx_create *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700916 struct be_dma_mem *q_mem = &txq->dma_mem;
Sathya Perlab31c50a2009-09-17 10:30:13 -0700917 void *ctxt;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700918 int status;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700919
Ivan Vecera29849612010-12-14 05:43:19 +0000920 if (mutex_lock_interruptible(&adapter->mbox_lock))
921 return -1;
Sathya Perlab31c50a2009-09-17 10:30:13 -0700922
923 wrb = wrb_from_mbox(adapter);
924 req = embedded_payload(wrb);
925 ctxt = &req->context;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700926
Somnath Kotur106df1e2011-10-27 07:12:13 +0000927 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
928 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700929
Padmanabh Ratnakar8b7756c2011-03-07 03:08:52 +0000930 if (lancer_chip(adapter)) {
931 req->hdr.version = 1;
932 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
933 adapter->if_handle);
934 }
935
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700936 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
937 req->ulp_num = BE_ULP1_NUM;
938 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
939
Sathya Perlab31c50a2009-09-17 10:30:13 -0700940 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
941 be_encoded_q_len(txq->len));
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700942 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
943 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
944
945 be_dws_cpu_to_le(ctxt, sizeof(req->context));
946
947 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
948
Sathya Perlab31c50a2009-09-17 10:30:13 -0700949 status = be_mbox_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700950 if (!status) {
951 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
952 txq->id = le16_to_cpu(resp->cid);
953 txq->created = true;
954 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700955
Ivan Vecera29849612010-12-14 05:43:19 +0000956 mutex_unlock(&adapter->mbox_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700957
958 return status;
959}
960
Sathya Perla482c9e72011-06-29 23:33:17 +0000961/* Uses MCC */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000962int be_cmd_rxq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700963 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
Sathya Perla3abcded2010-10-03 22:12:27 -0700964 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700965{
Sathya Perlab31c50a2009-09-17 10:30:13 -0700966 struct be_mcc_wrb *wrb;
967 struct be_cmd_req_eth_rx_create *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700968 struct be_dma_mem *q_mem = &rxq->dma_mem;
969 int status;
970
Sathya Perla482c9e72011-06-29 23:33:17 +0000971 spin_lock_bh(&adapter->mcc_lock);
Sathya Perlab31c50a2009-09-17 10:30:13 -0700972
Sathya Perla482c9e72011-06-29 23:33:17 +0000973 wrb = wrb_from_mccq(adapter);
974 if (!wrb) {
975 status = -EBUSY;
976 goto err;
977 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700978 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700979
Somnath Kotur106df1e2011-10-27 07:12:13 +0000980 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
981 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700982
983 req->cq_id = cpu_to_le16(cq_id);
984 req->frag_size = fls(frag_size) - 1;
985 req->num_pages = 2;
986 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
987 req->interface_id = cpu_to_le32(if_id);
988 req->max_frame_size = cpu_to_le16(max_frame_size);
989 req->rss_queue = cpu_to_le32(rss);
990
Sathya Perla482c9e72011-06-29 23:33:17 +0000991 status = be_mcc_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700992 if (!status) {
993 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
994 rxq->id = le16_to_cpu(resp->id);
995 rxq->created = true;
Sathya Perla3abcded2010-10-03 22:12:27 -0700996 *rss_id = resp->rss_id;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700997 }
Sathya Perlab31c50a2009-09-17 10:30:13 -0700998
Sathya Perla482c9e72011-06-29 23:33:17 +0000999err:
1000 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001001 return status;
1002}
1003
Sathya Perlab31c50a2009-09-17 10:30:13 -07001004/* Generic destroyer function for all types of queues
1005 * Uses Mbox
1006 */
Sathya Perla8788fdc2009-07-27 22:52:03 +00001007int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001008 int queue_type)
1009{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001010 struct be_mcc_wrb *wrb;
1011 struct be_cmd_req_q_destroy *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001012 u8 subsys = 0, opcode = 0;
1013 int status;
1014
Sathya Perlacf588472010-02-14 21:22:01 +00001015 if (adapter->eeh_err)
1016 return -EIO;
1017
Ivan Vecera29849612010-12-14 05:43:19 +00001018 if (mutex_lock_interruptible(&adapter->mbox_lock))
1019 return -1;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001020
Sathya Perlab31c50a2009-09-17 10:30:13 -07001021 wrb = wrb_from_mbox(adapter);
1022 req = embedded_payload(wrb);
1023
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001024 switch (queue_type) {
1025 case QTYPE_EQ:
1026 subsys = CMD_SUBSYSTEM_COMMON;
1027 opcode = OPCODE_COMMON_EQ_DESTROY;
1028 break;
1029 case QTYPE_CQ:
1030 subsys = CMD_SUBSYSTEM_COMMON;
1031 opcode = OPCODE_COMMON_CQ_DESTROY;
1032 break;
1033 case QTYPE_TXQ:
1034 subsys = CMD_SUBSYSTEM_ETH;
1035 opcode = OPCODE_ETH_TX_DESTROY;
1036 break;
1037 case QTYPE_RXQ:
1038 subsys = CMD_SUBSYSTEM_ETH;
1039 opcode = OPCODE_ETH_RX_DESTROY;
1040 break;
Sathya Perla5fb379e2009-06-18 00:02:59 +00001041 case QTYPE_MCCQ:
1042 subsys = CMD_SUBSYSTEM_COMMON;
1043 opcode = OPCODE_COMMON_MCC_DESTROY;
1044 break;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001045 default:
Sathya Perla5f0b8492009-07-27 22:52:56 +00001046 BUG();
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001047 }
Ajit Khaparded744b442009-12-03 06:12:06 +00001048
Somnath Kotur106df1e2011-10-27 07:12:13 +00001049 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1050 NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001051 req->id = cpu_to_le16(q->id);
1052
Sathya Perlab31c50a2009-09-17 10:30:13 -07001053 status = be_mbox_notify_wait(adapter);
Sathya Perla482c9e72011-06-29 23:33:17 +00001054 if (!status)
1055 q->created = false;
Sathya Perla5f0b8492009-07-27 22:52:56 +00001056
Ivan Vecera29849612010-12-14 05:43:19 +00001057 mutex_unlock(&adapter->mbox_lock);
Sathya Perla482c9e72011-06-29 23:33:17 +00001058 return status;
1059}
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001060
Sathya Perla482c9e72011-06-29 23:33:17 +00001061/* Uses MCC */
1062int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1063{
1064 struct be_mcc_wrb *wrb;
1065 struct be_cmd_req_q_destroy *req;
1066 int status;
1067
1068 spin_lock_bh(&adapter->mcc_lock);
1069
1070 wrb = wrb_from_mccq(adapter);
1071 if (!wrb) {
1072 status = -EBUSY;
1073 goto err;
1074 }
1075 req = embedded_payload(wrb);
1076
Somnath Kotur106df1e2011-10-27 07:12:13 +00001077 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1078 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
Sathya Perla482c9e72011-06-29 23:33:17 +00001079 req->id = cpu_to_le16(q->id);
1080
1081 status = be_mcc_notify_wait(adapter);
1082 if (!status)
1083 q->created = false;
1084
1085err:
1086 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001087 return status;
1088}
1089
Sathya Perlab31c50a2009-09-17 10:30:13 -07001090/* Create an rx filtering policy configuration on an i/f
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001091 * Uses MCCQ
Sathya Perlab31c50a2009-09-17 10:30:13 -07001092 */
Sathya Perla73d540f2009-10-14 20:20:42 +00001093int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001094 u8 *mac, u32 *if_handle, u32 *pmac_id, u32 domain)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001095{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001096 struct be_mcc_wrb *wrb;
1097 struct be_cmd_req_if_create *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001098 int status;
1099
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001100 spin_lock_bh(&adapter->mcc_lock);
Sathya Perlab31c50a2009-09-17 10:30:13 -07001101
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001102 wrb = wrb_from_mccq(adapter);
1103 if (!wrb) {
1104 status = -EBUSY;
1105 goto err;
1106 }
Sathya Perlab31c50a2009-09-17 10:30:13 -07001107 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001108
Somnath Kotur106df1e2011-10-27 07:12:13 +00001109 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1110 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
Sarveshwar Bandiba343c72010-03-31 02:56:12 +00001111 req->hdr.domain = domain;
Sathya Perla73d540f2009-10-14 20:20:42 +00001112 req->capability_flags = cpu_to_le32(cap_flags);
1113 req->enable_flags = cpu_to_le32(en_flags);
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001114 if (mac)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001115 memcpy(req->mac_addr, mac, ETH_ALEN);
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001116 else
1117 req->pmac_invalid = true;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001118
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001119 status = be_mcc_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001120 if (!status) {
1121 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1122 *if_handle = le32_to_cpu(resp->interface_id);
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001123 if (mac)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001124 *pmac_id = le32_to_cpu(resp->pmac_id);
1125 }
1126
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001127err:
1128 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001129 return status;
1130}
1131
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001132/* Uses MCCQ */
Sathya Perla30128032011-11-10 19:17:57 +00001133int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001134{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001135 struct be_mcc_wrb *wrb;
1136 struct be_cmd_req_if_destroy *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001137 int status;
1138
Sathya Perlacf588472010-02-14 21:22:01 +00001139 if (adapter->eeh_err)
1140 return -EIO;
1141
Sathya Perla30128032011-11-10 19:17:57 +00001142 if (interface_id == -1)
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001143 return 0;
Sathya Perlab31c50a2009-09-17 10:30:13 -07001144
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001145 spin_lock_bh(&adapter->mcc_lock);
1146
1147 wrb = wrb_from_mccq(adapter);
1148 if (!wrb) {
1149 status = -EBUSY;
1150 goto err;
1151 }
Sathya Perlab31c50a2009-09-17 10:30:13 -07001152 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001153
Somnath Kotur106df1e2011-10-27 07:12:13 +00001154 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1155 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
Ajit Khaparde658681f2011-02-11 13:34:46 +00001156 req->hdr.domain = domain;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001157 req->interface_id = cpu_to_le32(interface_id);
Sathya Perlab31c50a2009-09-17 10:30:13 -07001158
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001159 status = be_mcc_notify_wait(adapter);
1160err:
1161 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001162 return status;
1163}
1164
1165/* Get stats is a non embedded command: the request is not embedded inside
1166 * WRB but is a separate dma memory block
Sathya Perlab31c50a2009-09-17 10:30:13 -07001167 * Uses asynchronous MCC
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001168 */
Sathya Perla8788fdc2009-07-27 22:52:03 +00001169int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001170{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001171 struct be_mcc_wrb *wrb;
Ajit Khaparde89a88ab2011-05-16 07:36:18 +00001172 struct be_cmd_req_hdr *hdr;
Sathya Perla713d03942009-11-22 22:02:45 +00001173 int status = 0;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001174
Ajit Khaparde609ff3b2011-02-20 11:42:07 +00001175 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1176 be_cmd_get_die_temperature(adapter);
1177
Sathya Perlab31c50a2009-09-17 10:30:13 -07001178 spin_lock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001179
Sathya Perlab31c50a2009-09-17 10:30:13 -07001180 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001181 if (!wrb) {
1182 status = -EBUSY;
1183 goto err;
1184 }
Ajit Khaparde89a88ab2011-05-16 07:36:18 +00001185 hdr = nonemb_cmd->va;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001186
Somnath Kotur106df1e2011-10-27 07:12:13 +00001187 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1188 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
Ajit Khaparde89a88ab2011-05-16 07:36:18 +00001189
1190 if (adapter->generation == BE_GEN3)
1191 hdr->version = 1;
1192
Sathya Perlab31c50a2009-09-17 10:30:13 -07001193 be_mcc_notify(adapter);
Ajit Khapardeb2aebe62011-02-20 11:41:39 +00001194 adapter->stats_cmd_sent = true;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001195
Sathya Perla713d03942009-11-22 22:02:45 +00001196err:
Sathya Perlab31c50a2009-09-17 10:30:13 -07001197 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla713d03942009-11-22 22:02:45 +00001198 return status;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001199}
1200
Selvin Xavier005d5692011-05-16 07:36:35 +00001201/* Lancer Stats */
1202int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1203 struct be_dma_mem *nonemb_cmd)
1204{
1205
1206 struct be_mcc_wrb *wrb;
1207 struct lancer_cmd_req_pport_stats *req;
Selvin Xavier005d5692011-05-16 07:36:35 +00001208 int status = 0;
1209
1210 spin_lock_bh(&adapter->mcc_lock);
1211
1212 wrb = wrb_from_mccq(adapter);
1213 if (!wrb) {
1214 status = -EBUSY;
1215 goto err;
1216 }
1217 req = nonemb_cmd->va;
Selvin Xavier005d5692011-05-16 07:36:35 +00001218
Somnath Kotur106df1e2011-10-27 07:12:13 +00001219 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1220 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1221 nonemb_cmd);
Selvin Xavier005d5692011-05-16 07:36:35 +00001222
1223 req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1224 req->cmd_params.params.reset_stats = 0;
1225
Selvin Xavier005d5692011-05-16 07:36:35 +00001226 be_mcc_notify(adapter);
1227 adapter->stats_cmd_sent = true;
1228
1229err:
1230 spin_unlock_bh(&adapter->mcc_lock);
1231 return status;
1232}
1233
Sathya Perlab31c50a2009-09-17 10:30:13 -07001234/* Uses synchronous mcc */
Sathya Perlaea172a02011-08-02 19:57:42 +00001235int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1236 u16 *link_speed, u32 dom)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001237{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001238 struct be_mcc_wrb *wrb;
1239 struct be_cmd_req_link_status *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001240 int status;
1241
Sathya Perlab31c50a2009-09-17 10:30:13 -07001242 spin_lock_bh(&adapter->mcc_lock);
1243
1244 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001245 if (!wrb) {
1246 status = -EBUSY;
1247 goto err;
1248 }
Sathya Perlab31c50a2009-09-17 10:30:13 -07001249 req = embedded_payload(wrb);
Sathya Perlaa8f447bd2009-06-18 00:10:27 +00001250
Somnath Kotur106df1e2011-10-27 07:12:13 +00001251 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1252 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001253
Sathya Perlab31c50a2009-09-17 10:30:13 -07001254 status = be_mcc_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001255 if (!status) {
1256 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
Sarveshwar Bandi0388f252009-10-28 04:15:20 -07001257 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
Sarveshwar Bandi0388f252009-10-28 04:15:20 -07001258 *link_speed = le16_to_cpu(resp->link_speed);
Sathya Perlaf9449ab2011-10-24 02:45:01 +00001259 if (mac_speed)
1260 *mac_speed = resp->mac_speed;
Sarveshwar Bandi0388f252009-10-28 04:15:20 -07001261 }
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001262 }
1263
Sathya Perla713d03942009-11-22 22:02:45 +00001264err:
Sathya Perlab31c50a2009-09-17 10:30:13 -07001265 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001266 return status;
1267}
1268
Ajit Khaparde609ff3b2011-02-20 11:42:07 +00001269/* Uses synchronous mcc */
1270int be_cmd_get_die_temperature(struct be_adapter *adapter)
1271{
1272 struct be_mcc_wrb *wrb;
1273 struct be_cmd_req_get_cntl_addnl_attribs *req;
Somnath Kotur3de09452011-09-30 07:25:05 +00001274 u16 mccq_index;
Ajit Khaparde609ff3b2011-02-20 11:42:07 +00001275 int status;
1276
1277 spin_lock_bh(&adapter->mcc_lock);
1278
Somnath Kotur3de09452011-09-30 07:25:05 +00001279 mccq_index = adapter->mcc_obj.q.head;
1280
Ajit Khaparde609ff3b2011-02-20 11:42:07 +00001281 wrb = wrb_from_mccq(adapter);
1282 if (!wrb) {
1283 status = -EBUSY;
1284 goto err;
1285 }
1286 req = embedded_payload(wrb);
1287
Somnath Kotur106df1e2011-10-27 07:12:13 +00001288 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1289 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1290 wrb, NULL);
Ajit Khaparde609ff3b2011-02-20 11:42:07 +00001291
Somnath Kotur3de09452011-09-30 07:25:05 +00001292 wrb->tag1 = mccq_index;
1293
1294 be_mcc_notify(adapter);
Ajit Khaparde609ff3b2011-02-20 11:42:07 +00001295
1296err:
1297 spin_unlock_bh(&adapter->mcc_lock);
1298 return status;
1299}
1300
Somnath Kotur311fddc2011-03-16 21:22:43 +00001301/* Uses synchronous mcc */
1302int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1303{
1304 struct be_mcc_wrb *wrb;
1305 struct be_cmd_req_get_fat *req;
1306 int status;
1307
1308 spin_lock_bh(&adapter->mcc_lock);
1309
1310 wrb = wrb_from_mccq(adapter);
1311 if (!wrb) {
1312 status = -EBUSY;
1313 goto err;
1314 }
1315 req = embedded_payload(wrb);
1316
Somnath Kotur106df1e2011-10-27 07:12:13 +00001317 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1318 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
Somnath Kotur311fddc2011-03-16 21:22:43 +00001319 req->fat_operation = cpu_to_le32(QUERY_FAT);
1320 status = be_mcc_notify_wait(adapter);
1321 if (!status) {
1322 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1323 if (log_size && resp->log_size)
Somnath Koturfe2a70e2011-04-21 03:18:12 +00001324 *log_size = le32_to_cpu(resp->log_size) -
1325 sizeof(u32);
Somnath Kotur311fddc2011-03-16 21:22:43 +00001326 }
1327err:
1328 spin_unlock_bh(&adapter->mcc_lock);
1329 return status;
1330}
1331
1332void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1333{
1334 struct be_dma_mem get_fat_cmd;
1335 struct be_mcc_wrb *wrb;
1336 struct be_cmd_req_get_fat *req;
Somnath Koturfe2a70e2011-04-21 03:18:12 +00001337 u32 offset = 0, total_size, buf_size,
1338 log_offset = sizeof(u32), payload_len;
Somnath Kotur311fddc2011-03-16 21:22:43 +00001339 int status;
1340
1341 if (buf_len == 0)
1342 return;
1343
1344 total_size = buf_len;
1345
Somnath Koturfe2a70e2011-04-21 03:18:12 +00001346 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1347 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1348 get_fat_cmd.size,
1349 &get_fat_cmd.dma);
1350 if (!get_fat_cmd.va) {
1351 status = -ENOMEM;
1352 dev_err(&adapter->pdev->dev,
1353 "Memory allocation failure while retrieving FAT data\n");
1354 return;
1355 }
1356
Somnath Kotur311fddc2011-03-16 21:22:43 +00001357 spin_lock_bh(&adapter->mcc_lock);
1358
Somnath Kotur311fddc2011-03-16 21:22:43 +00001359 while (total_size) {
1360 buf_size = min(total_size, (u32)60*1024);
1361 total_size -= buf_size;
1362
Somnath Koturfe2a70e2011-04-21 03:18:12 +00001363 wrb = wrb_from_mccq(adapter);
1364 if (!wrb) {
1365 status = -EBUSY;
Somnath Kotur311fddc2011-03-16 21:22:43 +00001366 goto err;
1367 }
1368 req = get_fat_cmd.va;
Somnath Kotur311fddc2011-03-16 21:22:43 +00001369
Somnath Koturfe2a70e2011-04-21 03:18:12 +00001370 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
Somnath Kotur106df1e2011-10-27 07:12:13 +00001371 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1372 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1373 &get_fat_cmd);
Somnath Kotur311fddc2011-03-16 21:22:43 +00001374
1375 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1376 req->read_log_offset = cpu_to_le32(log_offset);
1377 req->read_log_length = cpu_to_le32(buf_size);
1378 req->data_buffer_size = cpu_to_le32(buf_size);
1379
1380 status = be_mcc_notify_wait(adapter);
1381 if (!status) {
1382 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1383 memcpy(buf + offset,
1384 resp->data_buffer,
Somnath Kotur92aa9212011-09-30 07:24:00 +00001385 le32_to_cpu(resp->read_log_length));
Somnath Koturfe2a70e2011-04-21 03:18:12 +00001386 } else {
Somnath Kotur311fddc2011-03-16 21:22:43 +00001387 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
Somnath Koturfe2a70e2011-04-21 03:18:12 +00001388 goto err;
1389 }
Somnath Kotur311fddc2011-03-16 21:22:43 +00001390 offset += buf_size;
1391 log_offset += buf_size;
1392 }
1393err:
Somnath Koturfe2a70e2011-04-21 03:18:12 +00001394 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1395 get_fat_cmd.va,
1396 get_fat_cmd.dma);
Somnath Kotur311fddc2011-03-16 21:22:43 +00001397 spin_unlock_bh(&adapter->mcc_lock);
1398}
1399
Sathya Perla04b71172011-09-27 13:30:27 -04001400/* Uses synchronous mcc */
1401int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1402 char *fw_on_flash)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001403{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001404 struct be_mcc_wrb *wrb;
1405 struct be_cmd_req_get_fw_version *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001406 int status;
1407
Sathya Perla04b71172011-09-27 13:30:27 -04001408 spin_lock_bh(&adapter->mcc_lock);
Sathya Perlab31c50a2009-09-17 10:30:13 -07001409
Sathya Perla04b71172011-09-27 13:30:27 -04001410 wrb = wrb_from_mccq(adapter);
1411 if (!wrb) {
1412 status = -EBUSY;
1413 goto err;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001414 }
1415
Sathya Perla04b71172011-09-27 13:30:27 -04001416 req = embedded_payload(wrb);
Sathya Perla04b71172011-09-27 13:30:27 -04001417
Somnath Kotur106df1e2011-10-27 07:12:13 +00001418 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1419 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
Sathya Perla04b71172011-09-27 13:30:27 -04001420 status = be_mcc_notify_wait(adapter);
1421 if (!status) {
1422 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1423 strcpy(fw_ver, resp->firmware_version_string);
1424 if (fw_on_flash)
1425 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1426 }
1427err:
1428 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001429 return status;
1430}
1431
Sathya Perlab31c50a2009-09-17 10:30:13 -07001432/* set the EQ delay interval of an EQ to specified value
1433 * Uses async mcc
1434 */
Sathya Perla8788fdc2009-07-27 22:52:03 +00001435int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001436{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001437 struct be_mcc_wrb *wrb;
1438 struct be_cmd_req_modify_eq_delay *req;
Sathya Perla713d03942009-11-22 22:02:45 +00001439 int status = 0;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001440
Sathya Perlab31c50a2009-09-17 10:30:13 -07001441 spin_lock_bh(&adapter->mcc_lock);
1442
1443 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001444 if (!wrb) {
1445 status = -EBUSY;
1446 goto err;
1447 }
Sathya Perlab31c50a2009-09-17 10:30:13 -07001448 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001449
Somnath Kotur106df1e2011-10-27 07:12:13 +00001450 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1451 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001452
1453 req->num_eq = cpu_to_le32(1);
1454 req->delay[0].eq_id = cpu_to_le32(eq_id);
1455 req->delay[0].phase = 0;
1456 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1457
Sathya Perlab31c50a2009-09-17 10:30:13 -07001458 be_mcc_notify(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001459
Sathya Perla713d03942009-11-22 22:02:45 +00001460err:
Sathya Perlab31c50a2009-09-17 10:30:13 -07001461 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla713d03942009-11-22 22:02:45 +00001462 return status;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001463}
1464
Sathya Perlab31c50a2009-09-17 10:30:13 -07001465/* Uses sycnhronous mcc */
Sathya Perla8788fdc2009-07-27 22:52:03 +00001466int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001467 u32 num, bool untagged, bool promiscuous)
1468{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001469 struct be_mcc_wrb *wrb;
1470 struct be_cmd_req_vlan_config *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001471 int status;
1472
Sathya Perlab31c50a2009-09-17 10:30:13 -07001473 spin_lock_bh(&adapter->mcc_lock);
1474
1475 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001476 if (!wrb) {
1477 status = -EBUSY;
1478 goto err;
1479 }
Sathya Perlab31c50a2009-09-17 10:30:13 -07001480 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001481
Somnath Kotur106df1e2011-10-27 07:12:13 +00001482 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1483 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001484
1485 req->interface_id = if_id;
1486 req->promiscuous = promiscuous;
1487 req->untagged = untagged;
1488 req->num_vlan = num;
1489 if (!promiscuous) {
1490 memcpy(req->normal_vlan, vtag_array,
1491 req->num_vlan * sizeof(vtag_array[0]));
1492 }
1493
Sathya Perlab31c50a2009-09-17 10:30:13 -07001494 status = be_mcc_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001495
Sathya Perla713d03942009-11-22 22:02:45 +00001496err:
Sathya Perlab31c50a2009-09-17 10:30:13 -07001497 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001498 return status;
1499}
1500
Sathya Perla5b8821b2011-08-02 19:57:44 +00001501int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001502{
Sathya Perla6ac7b682009-06-18 00:05:54 +00001503 struct be_mcc_wrb *wrb;
Sathya Perla5b8821b2011-08-02 19:57:44 +00001504 struct be_dma_mem *mem = &adapter->rx_filter;
1505 struct be_cmd_req_rx_filter *req = mem->va;
Sathya Perlae7b909a2009-11-22 22:01:10 +00001506 int status;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001507
Sathya Perla8788fdc2009-07-27 22:52:03 +00001508 spin_lock_bh(&adapter->mcc_lock);
Sathya Perla6ac7b682009-06-18 00:05:54 +00001509
Sathya Perlab31c50a2009-09-17 10:30:13 -07001510 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001511 if (!wrb) {
1512 status = -EBUSY;
1513 goto err;
1514 }
Sathya Perla5b8821b2011-08-02 19:57:44 +00001515 memset(req, 0, sizeof(*req));
Somnath Kotur106df1e2011-10-27 07:12:13 +00001516 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1517 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1518 wrb, mem);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001519
Sathya Perla5b8821b2011-08-02 19:57:44 +00001520 req->if_id = cpu_to_le32(adapter->if_handle);
1521 if (flags & IFF_PROMISC) {
1522 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1523 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1524 if (value == ON)
1525 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
Sathya Perla8e7d3f62011-09-27 13:29:38 -04001526 BE_IF_FLAGS_VLAN_PROMISCUOUS);
Sathya Perla5b8821b2011-08-02 19:57:44 +00001527 } else if (flags & IFF_ALLMULTI) {
1528 req->if_flags_mask = req->if_flags =
Sathya Perla8e7d3f62011-09-27 13:29:38 -04001529 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
Sathya Perla24307ee2009-06-18 00:09:25 +00001530 } else {
Sathya Perla5b8821b2011-08-02 19:57:44 +00001531 struct netdev_hw_addr *ha;
1532 int i = 0;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001533
Sathya Perla8e7d3f62011-09-27 13:29:38 -04001534 req->if_flags_mask = req->if_flags =
1535 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
Padmanabh Ratnakar1610c792011-11-03 01:49:27 +00001536
1537 /* Reset mcast promisc mode if already set by setting mask
1538 * and not setting flags field
1539 */
1540 req->if_flags_mask |=
1541 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1542
Padmanabh Ratnakar016f97b2011-11-03 01:49:13 +00001543 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
Sathya Perla5b8821b2011-08-02 19:57:44 +00001544 netdev_for_each_mc_addr(ha, adapter->netdev)
1545 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1546 }
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001547
Sathya Perla0d1d5872011-08-03 05:19:27 -07001548 status = be_mcc_notify_wait(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001549err:
Sathya Perla8788fdc2009-07-27 22:52:03 +00001550 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perlae7b909a2009-11-22 22:01:10 +00001551 return status;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001552}
1553
Sathya Perlab31c50a2009-09-17 10:30:13 -07001554/* Uses synchrounous mcc */
Sathya Perla8788fdc2009-07-27 22:52:03 +00001555int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001556{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001557 struct be_mcc_wrb *wrb;
1558 struct be_cmd_req_set_flow_control *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001559 int status;
1560
Sathya Perlab31c50a2009-09-17 10:30:13 -07001561 spin_lock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001562
Sathya Perlab31c50a2009-09-17 10:30:13 -07001563 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001564 if (!wrb) {
1565 status = -EBUSY;
1566 goto err;
1567 }
Sathya Perlab31c50a2009-09-17 10:30:13 -07001568 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001569
Somnath Kotur106df1e2011-10-27 07:12:13 +00001570 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1571 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001572
1573 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1574 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1575
Sathya Perlab31c50a2009-09-17 10:30:13 -07001576 status = be_mcc_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001577
Sathya Perla713d03942009-11-22 22:02:45 +00001578err:
Sathya Perlab31c50a2009-09-17 10:30:13 -07001579 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001580 return status;
1581}
1582
Sathya Perlab31c50a2009-09-17 10:30:13 -07001583/* Uses sycn mcc */
Sathya Perla8788fdc2009-07-27 22:52:03 +00001584int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001585{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001586 struct be_mcc_wrb *wrb;
1587 struct be_cmd_req_get_flow_control *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001588 int status;
1589
Sathya Perlab31c50a2009-09-17 10:30:13 -07001590 spin_lock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001591
Sathya Perlab31c50a2009-09-17 10:30:13 -07001592 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001593 if (!wrb) {
1594 status = -EBUSY;
1595 goto err;
1596 }
Sathya Perlab31c50a2009-09-17 10:30:13 -07001597 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001598
Somnath Kotur106df1e2011-10-27 07:12:13 +00001599 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1600 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001601
Sathya Perlab31c50a2009-09-17 10:30:13 -07001602 status = be_mcc_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001603 if (!status) {
1604 struct be_cmd_resp_get_flow_control *resp =
1605 embedded_payload(wrb);
1606 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1607 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1608 }
1609
Sathya Perla713d03942009-11-22 22:02:45 +00001610err:
Sathya Perlab31c50a2009-09-17 10:30:13 -07001611 spin_unlock_bh(&adapter->mcc_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001612 return status;
1613}
1614
Sathya Perlab31c50a2009-09-17 10:30:13 -07001615/* Uses mbox */
Sathya Perla3abcded2010-10-03 22:12:27 -07001616int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1617 u32 *mode, u32 *caps)
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001618{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001619 struct be_mcc_wrb *wrb;
1620 struct be_cmd_req_query_fw_cfg *req;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001621 int status;
1622
Ivan Vecera29849612010-12-14 05:43:19 +00001623 if (mutex_lock_interruptible(&adapter->mbox_lock))
1624 return -1;
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001625
Sathya Perlab31c50a2009-09-17 10:30:13 -07001626 wrb = wrb_from_mbox(adapter);
1627 req = embedded_payload(wrb);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001628
Somnath Kotur106df1e2011-10-27 07:12:13 +00001629 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1630 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001631
Sathya Perlab31c50a2009-09-17 10:30:13 -07001632 status = be_mbox_notify_wait(adapter);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001633 if (!status) {
1634 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1635 *port_num = le32_to_cpu(resp->phys_port);
Ajit Khaparde3486be22010-07-23 02:04:54 +00001636 *mode = le32_to_cpu(resp->function_mode);
Sathya Perla3abcded2010-10-03 22:12:27 -07001637 *caps = le32_to_cpu(resp->function_caps);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001638 }
1639
Ivan Vecera29849612010-12-14 05:43:19 +00001640 mutex_unlock(&adapter->mbox_lock);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001641 return status;
1642}
sarveshwarb14074ea2009-08-05 13:05:24 -07001643
Sathya Perlab31c50a2009-09-17 10:30:13 -07001644/* Uses mbox */
sarveshwarb14074ea2009-08-05 13:05:24 -07001645int be_cmd_reset_function(struct be_adapter *adapter)
1646{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001647 struct be_mcc_wrb *wrb;
1648 struct be_cmd_req_hdr *req;
sarveshwarb14074ea2009-08-05 13:05:24 -07001649 int status;
1650
Ivan Vecera29849612010-12-14 05:43:19 +00001651 if (mutex_lock_interruptible(&adapter->mbox_lock))
1652 return -1;
sarveshwarb14074ea2009-08-05 13:05:24 -07001653
Sathya Perlab31c50a2009-09-17 10:30:13 -07001654 wrb = wrb_from_mbox(adapter);
1655 req = embedded_payload(wrb);
sarveshwarb14074ea2009-08-05 13:05:24 -07001656
Somnath Kotur106df1e2011-10-27 07:12:13 +00001657 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1658 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
sarveshwarb14074ea2009-08-05 13:05:24 -07001659
Sathya Perlab31c50a2009-09-17 10:30:13 -07001660 status = be_mbox_notify_wait(adapter);
sarveshwarb14074ea2009-08-05 13:05:24 -07001661
Ivan Vecera29849612010-12-14 05:43:19 +00001662 mutex_unlock(&adapter->mbox_lock);
sarveshwarb14074ea2009-08-05 13:05:24 -07001663 return status;
1664}
Ajit Khaparde84517482009-09-04 03:12:16 +00001665
Sathya Perla3abcded2010-10-03 22:12:27 -07001666int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1667{
1668 struct be_mcc_wrb *wrb;
1669 struct be_cmd_req_rss_config *req;
Sathya Perla5d8bee62011-05-23 20:29:09 +00001670 u32 myhash[10] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF,
1671 0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF};
Sathya Perla3abcded2010-10-03 22:12:27 -07001672 int status;
1673
Ivan Vecera29849612010-12-14 05:43:19 +00001674 if (mutex_lock_interruptible(&adapter->mbox_lock))
1675 return -1;
Sathya Perla3abcded2010-10-03 22:12:27 -07001676
1677 wrb = wrb_from_mbox(adapter);
1678 req = embedded_payload(wrb);
1679
Somnath Kotur106df1e2011-10-27 07:12:13 +00001680 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1681 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
Sathya Perla3abcded2010-10-03 22:12:27 -07001682
1683 req->if_id = cpu_to_le32(adapter->if_handle);
1684 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1685 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1686 memcpy(req->cpu_table, rsstable, table_size);
1687 memcpy(req->hash, myhash, sizeof(myhash));
1688 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1689
1690 status = be_mbox_notify_wait(adapter);
1691
Ivan Vecera29849612010-12-14 05:43:19 +00001692 mutex_unlock(&adapter->mbox_lock);
Sathya Perla3abcded2010-10-03 22:12:27 -07001693 return status;
1694}
1695
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -07001696/* Uses sync mcc */
1697int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1698 u8 bcn, u8 sts, u8 state)
1699{
1700 struct be_mcc_wrb *wrb;
1701 struct be_cmd_req_enable_disable_beacon *req;
1702 int status;
1703
1704 spin_lock_bh(&adapter->mcc_lock);
1705
1706 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001707 if (!wrb) {
1708 status = -EBUSY;
1709 goto err;
1710 }
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -07001711 req = embedded_payload(wrb);
1712
Somnath Kotur106df1e2011-10-27 07:12:13 +00001713 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1714 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -07001715
1716 req->port_num = port_num;
1717 req->beacon_state = state;
1718 req->beacon_duration = bcn;
1719 req->status_duration = sts;
1720
1721 status = be_mcc_notify_wait(adapter);
1722
Sathya Perla713d03942009-11-22 22:02:45 +00001723err:
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -07001724 spin_unlock_bh(&adapter->mcc_lock);
1725 return status;
1726}
1727
1728/* Uses sync mcc */
1729int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1730{
1731 struct be_mcc_wrb *wrb;
1732 struct be_cmd_req_get_beacon_state *req;
1733 int status;
1734
1735 spin_lock_bh(&adapter->mcc_lock);
1736
1737 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001738 if (!wrb) {
1739 status = -EBUSY;
1740 goto err;
1741 }
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -07001742 req = embedded_payload(wrb);
1743
Somnath Kotur106df1e2011-10-27 07:12:13 +00001744 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1745 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -07001746
1747 req->port_num = port_num;
1748
1749 status = be_mcc_notify_wait(adapter);
1750 if (!status) {
1751 struct be_cmd_resp_get_beacon_state *resp =
1752 embedded_payload(wrb);
1753 *state = resp->beacon_state;
1754 }
1755
Sathya Perla713d03942009-11-22 22:02:45 +00001756err:
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -07001757 spin_unlock_bh(&adapter->mcc_lock);
1758 return status;
1759}
1760
Shripad Nunjundarao485bf562011-05-16 07:36:59 +00001761int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1762 u32 data_size, u32 data_offset, const char *obj_name,
1763 u32 *data_written, u8 *addn_status)
1764{
1765 struct be_mcc_wrb *wrb;
1766 struct lancer_cmd_req_write_object *req;
1767 struct lancer_cmd_resp_write_object *resp;
1768 void *ctxt = NULL;
1769 int status;
1770
1771 spin_lock_bh(&adapter->mcc_lock);
1772 adapter->flash_status = 0;
1773
1774 wrb = wrb_from_mccq(adapter);
1775 if (!wrb) {
1776 status = -EBUSY;
1777 goto err_unlock;
1778 }
1779
1780 req = embedded_payload(wrb);
1781
Somnath Kotur106df1e2011-10-27 07:12:13 +00001782 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
Shripad Nunjundarao485bf562011-05-16 07:36:59 +00001783 OPCODE_COMMON_WRITE_OBJECT,
Somnath Kotur106df1e2011-10-27 07:12:13 +00001784 sizeof(struct lancer_cmd_req_write_object), wrb,
1785 NULL);
Shripad Nunjundarao485bf562011-05-16 07:36:59 +00001786
1787 ctxt = &req->context;
1788 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1789 write_length, ctxt, data_size);
1790
1791 if (data_size == 0)
1792 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1793 eof, ctxt, 1);
1794 else
1795 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1796 eof, ctxt, 0);
1797
1798 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1799 req->write_offset = cpu_to_le32(data_offset);
1800 strcpy(req->object_name, obj_name);
1801 req->descriptor_count = cpu_to_le32(1);
1802 req->buf_len = cpu_to_le32(data_size);
1803 req->addr_low = cpu_to_le32((cmd->dma +
1804 sizeof(struct lancer_cmd_req_write_object))
1805 & 0xFFFFFFFF);
1806 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1807 sizeof(struct lancer_cmd_req_write_object)));
1808
1809 be_mcc_notify(adapter);
1810 spin_unlock_bh(&adapter->mcc_lock);
1811
1812 if (!wait_for_completion_timeout(&adapter->flash_compl,
1813 msecs_to_jiffies(12000)))
1814 status = -1;
1815 else
1816 status = adapter->flash_status;
1817
1818 resp = embedded_payload(wrb);
1819 if (!status) {
1820 *data_written = le32_to_cpu(resp->actual_write_len);
1821 } else {
1822 *addn_status = resp->additional_status;
1823 status = resp->status;
1824 }
1825
1826 return status;
1827
1828err_unlock:
1829 spin_unlock_bh(&adapter->mcc_lock);
1830 return status;
1831}
1832
Ajit Khaparde84517482009-09-04 03:12:16 +00001833int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1834 u32 flash_type, u32 flash_opcode, u32 buf_size)
1835{
Sathya Perlab31c50a2009-09-17 10:30:13 -07001836 struct be_mcc_wrb *wrb;
Ajit Khaparde3f0d4562010-02-09 01:30:35 +00001837 struct be_cmd_write_flashrom *req;
Ajit Khaparde84517482009-09-04 03:12:16 +00001838 int status;
1839
Sathya Perlab31c50a2009-09-17 10:30:13 -07001840 spin_lock_bh(&adapter->mcc_lock);
Sarveshwar Bandidd131e72010-05-25 16:16:32 -07001841 adapter->flash_status = 0;
Sathya Perlab31c50a2009-09-17 10:30:13 -07001842
1843 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001844 if (!wrb) {
1845 status = -EBUSY;
Dan Carpenter2892d9c2010-05-26 04:46:35 +00001846 goto err_unlock;
Sathya Perla713d03942009-11-22 22:02:45 +00001847 }
1848 req = cmd->va;
Sathya Perlab31c50a2009-09-17 10:30:13 -07001849
Somnath Kotur106df1e2011-10-27 07:12:13 +00001850 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1851 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
Ajit Khaparde84517482009-09-04 03:12:16 +00001852
1853 req->params.op_type = cpu_to_le32(flash_type);
1854 req->params.op_code = cpu_to_le32(flash_opcode);
1855 req->params.data_buf_size = cpu_to_le32(buf_size);
1856
Sarveshwar Bandidd131e72010-05-25 16:16:32 -07001857 be_mcc_notify(adapter);
1858 spin_unlock_bh(&adapter->mcc_lock);
1859
1860 if (!wait_for_completion_timeout(&adapter->flash_compl,
Sathya Perlae2edb7d2011-08-22 19:41:54 +00001861 msecs_to_jiffies(40000)))
Sarveshwar Bandidd131e72010-05-25 16:16:32 -07001862 status = -1;
1863 else
1864 status = adapter->flash_status;
Ajit Khaparde84517482009-09-04 03:12:16 +00001865
Dan Carpenter2892d9c2010-05-26 04:46:35 +00001866 return status;
1867
1868err_unlock:
1869 spin_unlock_bh(&adapter->mcc_lock);
Ajit Khaparde84517482009-09-04 03:12:16 +00001870 return status;
1871}
Sarveshwar Bandifa9a6fe2009-11-20 14:23:47 -08001872
Ajit Khaparde3f0d4562010-02-09 01:30:35 +00001873int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1874 int offset)
Sarveshwar Bandifa9a6fe2009-11-20 14:23:47 -08001875{
1876 struct be_mcc_wrb *wrb;
1877 struct be_cmd_write_flashrom *req;
1878 int status;
1879
1880 spin_lock_bh(&adapter->mcc_lock);
1881
1882 wrb = wrb_from_mccq(adapter);
Sathya Perla713d03942009-11-22 22:02:45 +00001883 if (!wrb) {
1884 status = -EBUSY;
1885 goto err;
1886 }
Sarveshwar Bandifa9a6fe2009-11-20 14:23:47 -08001887 req = embedded_payload(wrb);
1888
Somnath Kotur106df1e2011-10-27 07:12:13 +00001889 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1890 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
Sarveshwar Bandifa9a6fe2009-11-20 14:23:47 -08001891
Ajit Khaparde3f0d4562010-02-09 01:30:35 +00001892 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
Sarveshwar Bandifa9a6fe2009-11-20 14:23:47 -08001893 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
Ajit Khaparde8b93b712010-03-31 01:57:10 +00001894 req->params.offset = cpu_to_le32(offset);
1895 req->params.data_buf_size = cpu_to_le32(0x4);
Sarveshwar Bandifa9a6fe2009-11-20 14:23:47 -08001896
1897 status = be_mcc_notify_wait(adapter);
1898 if (!status)
1899 memcpy(flashed_crc, req->params.data_buf, 4);
1900
Sathya Perla713d03942009-11-22 22:02:45 +00001901err:
Sarveshwar Bandifa9a6fe2009-11-20 14:23:47 -08001902 spin_unlock_bh(&adapter->mcc_lock);
1903 return status;
1904}
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +00001905
Dan Carpenterc196b022010-05-26 04:47:39 +00001906int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +00001907 struct be_dma_mem *nonemb_cmd)
1908{
1909 struct be_mcc_wrb *wrb;
1910 struct be_cmd_req_acpi_wol_magic_config *req;
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +00001911 int status;
1912
1913 spin_lock_bh(&adapter->mcc_lock);
1914
1915 wrb = wrb_from_mccq(adapter);
1916 if (!wrb) {
1917 status = -EBUSY;
1918 goto err;
1919 }
1920 req = nonemb_cmd->va;
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +00001921
Somnath Kotur106df1e2011-10-27 07:12:13 +00001922 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1923 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
1924 nonemb_cmd);
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +00001925 memcpy(req->magic_mac, mac, ETH_ALEN);
1926
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +00001927 status = be_mcc_notify_wait(adapter);
1928
1929err:
1930 spin_unlock_bh(&adapter->mcc_lock);
1931 return status;
1932}
Suresh Rff33a6e2009-12-03 16:15:52 -08001933
Sarveshwar Bandifced9992009-12-23 04:41:44 +00001934int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1935 u8 loopback_type, u8 enable)
1936{
1937 struct be_mcc_wrb *wrb;
1938 struct be_cmd_req_set_lmode *req;
1939 int status;
1940
1941 spin_lock_bh(&adapter->mcc_lock);
1942
1943 wrb = wrb_from_mccq(adapter);
1944 if (!wrb) {
1945 status = -EBUSY;
1946 goto err;
1947 }
1948
1949 req = embedded_payload(wrb);
1950
Somnath Kotur106df1e2011-10-27 07:12:13 +00001951 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1952 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
1953 NULL);
Sarveshwar Bandifced9992009-12-23 04:41:44 +00001954
1955 req->src_port = port_num;
1956 req->dest_port = port_num;
1957 req->loopback_type = loopback_type;
1958 req->loopback_state = enable;
1959
1960 status = be_mcc_notify_wait(adapter);
1961err:
1962 spin_unlock_bh(&adapter->mcc_lock);
1963 return status;
1964}
1965
Suresh Rff33a6e2009-12-03 16:15:52 -08001966int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1967 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1968{
1969 struct be_mcc_wrb *wrb;
1970 struct be_cmd_req_loopback_test *req;
1971 int status;
1972
1973 spin_lock_bh(&adapter->mcc_lock);
1974
1975 wrb = wrb_from_mccq(adapter);
1976 if (!wrb) {
1977 status = -EBUSY;
1978 goto err;
1979 }
1980
1981 req = embedded_payload(wrb);
1982
Somnath Kotur106df1e2011-10-27 07:12:13 +00001983 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1984 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
Sathya Perla3ffd0512010-06-01 00:19:33 -07001985 req->hdr.timeout = cpu_to_le32(4);
Suresh Rff33a6e2009-12-03 16:15:52 -08001986
1987 req->pattern = cpu_to_le64(pattern);
1988 req->src_port = cpu_to_le32(port_num);
1989 req->dest_port = cpu_to_le32(port_num);
1990 req->pkt_size = cpu_to_le32(pkt_size);
1991 req->num_pkts = cpu_to_le32(num_pkts);
1992 req->loopback_type = cpu_to_le32(loopback_type);
1993
1994 status = be_mcc_notify_wait(adapter);
1995 if (!status) {
1996 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1997 status = le32_to_cpu(resp->status);
1998 }
1999
2000err:
2001 spin_unlock_bh(&adapter->mcc_lock);
2002 return status;
2003}
2004
2005int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2006 u32 byte_cnt, struct be_dma_mem *cmd)
2007{
2008 struct be_mcc_wrb *wrb;
2009 struct be_cmd_req_ddrdma_test *req;
Suresh Rff33a6e2009-12-03 16:15:52 -08002010 int status;
2011 int i, j = 0;
2012
2013 spin_lock_bh(&adapter->mcc_lock);
2014
2015 wrb = wrb_from_mccq(adapter);
2016 if (!wrb) {
2017 status = -EBUSY;
2018 goto err;
2019 }
2020 req = cmd->va;
Somnath Kotur106df1e2011-10-27 07:12:13 +00002021 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2022 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
Suresh Rff33a6e2009-12-03 16:15:52 -08002023
2024 req->pattern = cpu_to_le64(pattern);
2025 req->byte_count = cpu_to_le32(byte_cnt);
2026 for (i = 0; i < byte_cnt; i++) {
2027 req->snd_buff[i] = (u8)(pattern >> (j*8));
2028 j++;
2029 if (j > 7)
2030 j = 0;
2031 }
2032
2033 status = be_mcc_notify_wait(adapter);
2034
2035 if (!status) {
2036 struct be_cmd_resp_ddrdma_test *resp;
2037 resp = cmd->va;
2038 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2039 resp->snd_err) {
2040 status = -1;
2041 }
2042 }
2043
2044err:
2045 spin_unlock_bh(&adapter->mcc_lock);
2046 return status;
2047}
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -08002048
Dan Carpenterc196b022010-05-26 04:47:39 +00002049int be_cmd_get_seeprom_data(struct be_adapter *adapter,
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -08002050 struct be_dma_mem *nonemb_cmd)
2051{
2052 struct be_mcc_wrb *wrb;
2053 struct be_cmd_req_seeprom_read *req;
2054 struct be_sge *sge;
2055 int status;
2056
2057 spin_lock_bh(&adapter->mcc_lock);
2058
2059 wrb = wrb_from_mccq(adapter);
Ajit Khapardee45ff012011-02-04 17:18:28 +00002060 if (!wrb) {
2061 status = -EBUSY;
2062 goto err;
2063 }
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -08002064 req = nonemb_cmd->va;
2065 sge = nonembedded_sgl(wrb);
2066
Somnath Kotur106df1e2011-10-27 07:12:13 +00002067 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2068 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2069 nonemb_cmd);
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -08002070
2071 status = be_mcc_notify_wait(adapter);
2072
Ajit Khapardee45ff012011-02-04 17:18:28 +00002073err:
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -08002074 spin_unlock_bh(&adapter->mcc_lock);
2075 return status;
2076}
Ajit Khapardeee3cb622010-07-01 03:51:00 +00002077
Sathya Perla306f1342011-08-02 19:57:45 +00002078int be_cmd_get_phy_info(struct be_adapter *adapter,
2079 struct be_phy_info *phy_info)
Ajit Khapardeee3cb622010-07-01 03:51:00 +00002080{
2081 struct be_mcc_wrb *wrb;
2082 struct be_cmd_req_get_phy_info *req;
Sathya Perla306f1342011-08-02 19:57:45 +00002083 struct be_dma_mem cmd;
Ajit Khapardeee3cb622010-07-01 03:51:00 +00002084 int status;
2085
2086 spin_lock_bh(&adapter->mcc_lock);
2087
2088 wrb = wrb_from_mccq(adapter);
2089 if (!wrb) {
2090 status = -EBUSY;
2091 goto err;
2092 }
Sathya Perla306f1342011-08-02 19:57:45 +00002093 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2094 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2095 &cmd.dma);
2096 if (!cmd.va) {
2097 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2098 status = -ENOMEM;
2099 goto err;
2100 }
Ajit Khapardeee3cb622010-07-01 03:51:00 +00002101
Sathya Perla306f1342011-08-02 19:57:45 +00002102 req = cmd.va;
Ajit Khapardeee3cb622010-07-01 03:51:00 +00002103
Somnath Kotur106df1e2011-10-27 07:12:13 +00002104 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2105 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2106 wrb, &cmd);
Ajit Khapardeee3cb622010-07-01 03:51:00 +00002107
2108 status = be_mcc_notify_wait(adapter);
Sathya Perla306f1342011-08-02 19:57:45 +00002109 if (!status) {
2110 struct be_phy_info *resp_phy_info =
2111 cmd.va + sizeof(struct be_cmd_req_hdr);
2112 phy_info->phy_type = le16_to_cpu(resp_phy_info->phy_type);
2113 phy_info->interface_type =
2114 le16_to_cpu(resp_phy_info->interface_type);
2115 }
2116 pci_free_consistent(adapter->pdev, cmd.size,
2117 cmd.va, cmd.dma);
Ajit Khapardeee3cb622010-07-01 03:51:00 +00002118err:
2119 spin_unlock_bh(&adapter->mcc_lock);
2120 return status;
2121}
Ajit Khapardee1d18732010-07-23 01:52:13 +00002122
2123int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2124{
2125 struct be_mcc_wrb *wrb;
2126 struct be_cmd_req_set_qos *req;
2127 int status;
2128
2129 spin_lock_bh(&adapter->mcc_lock);
2130
2131 wrb = wrb_from_mccq(adapter);
2132 if (!wrb) {
2133 status = -EBUSY;
2134 goto err;
2135 }
2136
2137 req = embedded_payload(wrb);
2138
Somnath Kotur106df1e2011-10-27 07:12:13 +00002139 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2140 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
Ajit Khapardee1d18732010-07-23 01:52:13 +00002141
2142 req->hdr.domain = domain;
Ajit Khaparde6bff57a2011-02-11 13:33:02 +00002143 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2144 req->max_bps_nic = cpu_to_le32(bps);
Ajit Khapardee1d18732010-07-23 01:52:13 +00002145
2146 status = be_mcc_notify_wait(adapter);
2147
2148err:
2149 spin_unlock_bh(&adapter->mcc_lock);
2150 return status;
2151}
Ajit Khaparde9e1453c2011-02-20 11:42:22 +00002152
2153int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2154{
2155 struct be_mcc_wrb *wrb;
2156 struct be_cmd_req_cntl_attribs *req;
2157 struct be_cmd_resp_cntl_attribs *resp;
Ajit Khaparde9e1453c2011-02-20 11:42:22 +00002158 int status;
2159 int payload_len = max(sizeof(*req), sizeof(*resp));
2160 struct mgmt_controller_attrib *attribs;
2161 struct be_dma_mem attribs_cmd;
2162
2163 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2164 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2165 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2166 &attribs_cmd.dma);
2167 if (!attribs_cmd.va) {
2168 dev_err(&adapter->pdev->dev,
2169 "Memory allocation failure\n");
2170 return -ENOMEM;
2171 }
2172
2173 if (mutex_lock_interruptible(&adapter->mbox_lock))
2174 return -1;
2175
2176 wrb = wrb_from_mbox(adapter);
2177 if (!wrb) {
2178 status = -EBUSY;
2179 goto err;
2180 }
2181 req = attribs_cmd.va;
Ajit Khaparde9e1453c2011-02-20 11:42:22 +00002182
Somnath Kotur106df1e2011-10-27 07:12:13 +00002183 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2184 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2185 &attribs_cmd);
Ajit Khaparde9e1453c2011-02-20 11:42:22 +00002186
2187 status = be_mbox_notify_wait(adapter);
2188 if (!status) {
Joe Perches43d620c2011-06-16 19:08:06 +00002189 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
Ajit Khaparde9e1453c2011-02-20 11:42:22 +00002190 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2191 }
2192
2193err:
2194 mutex_unlock(&adapter->mbox_lock);
2195 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2196 attribs_cmd.dma);
2197 return status;
2198}
Sathya Perla2e588f82011-03-11 02:49:26 +00002199
2200/* Uses mbox */
Sathya Perla2dc1deb2011-07-19 19:52:33 +00002201int be_cmd_req_native_mode(struct be_adapter *adapter)
Sathya Perla2e588f82011-03-11 02:49:26 +00002202{
2203 struct be_mcc_wrb *wrb;
2204 struct be_cmd_req_set_func_cap *req;
2205 int status;
2206
2207 if (mutex_lock_interruptible(&adapter->mbox_lock))
2208 return -1;
2209
2210 wrb = wrb_from_mbox(adapter);
2211 if (!wrb) {
2212 status = -EBUSY;
2213 goto err;
2214 }
2215
2216 req = embedded_payload(wrb);
2217
Somnath Kotur106df1e2011-10-27 07:12:13 +00002218 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2219 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
Sathya Perla2e588f82011-03-11 02:49:26 +00002220
2221 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2222 CAPABILITY_BE3_NATIVE_ERX_API);
2223 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2224
2225 status = be_mbox_notify_wait(adapter);
2226 if (!status) {
2227 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2228 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2229 CAPABILITY_BE3_NATIVE_ERX_API;
2230 }
2231err:
2232 mutex_unlock(&adapter->mbox_lock);
2233 return status;
2234}