blob: ed4cfc55f3a848e0daa560a0ba01b8757a4ae6ef [file] [log] [blame]
Stefan Agnere1bf86a2014-11-02 21:36:47 +01001/*
2 * Copyright 2014 Toradex AG
3 *
Stefan Agner9f3440d2015-12-07 13:51:14 -08004 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
Stefan Agnere1bf86a2014-11-02 21:36:47 +010040 */
41
42/ {
43 bl: backlight {
44 compatible = "pwm-backlight";
Bhuvanchandra DVb2e42442016-01-09 12:29:53 +053045 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_gpio_bl_on>;
Stefan Agnere1bf86a2014-11-02 21:36:47 +010047 pwms = <&pwm0 0 5000000 0>;
Bhuvanchandra DVb2e42442016-01-09 12:29:53 +053048 enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
Stefan Agnere1bf86a2014-11-02 21:36:47 +010049 status = "disabled";
50 };
Stefan Agner47b06e62016-02-17 15:40:59 -080051
52 reg_module_3v3: regulator-module-3v3 {
53 compatible = "regulator-fixed";
54 regulator-name = "+V3.3";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 };
58
59 reg_module_3v3_avdd: regulator-module-3v3-avdd {
60 compatible = "regulator-fixed";
61 regulator-name = "+V3.3_AVDD_AUDIO";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 };
Stefan Agnere1bf86a2014-11-02 21:36:47 +010065};
66
67&adc0 {
68 status = "okay";
Stefan Agner47b06e62016-02-17 15:40:59 -080069 vref-supply = <&reg_module_3v3_avdd>;
Stefan Agnere1bf86a2014-11-02 21:36:47 +010070};
71
72&adc1 {
73 status = "okay";
Stefan Agner47b06e62016-02-17 15:40:59 -080074 vref-supply = <&reg_module_3v3_avdd>;
Stefan Agnere1bf86a2014-11-02 21:36:47 +010075};
76
Stefan Agner2afa06c2015-12-02 14:11:47 -080077&can0 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_flexcan0>;
80 status = "disabled";
81};
82
83&can1 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_flexcan1>;
86 status = "disabled";
87};
88
Stefan Agner5c35b772016-02-10 16:02:26 -080089&clks {
90 assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
91 <&clks VF610_CLK_ENET_TS_SEL>;
92 assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
93 <&clks VF610_CLK_ENET_50M>;
94};
95
Bhuvanchandra DV9fca0152015-01-29 21:57:45 +053096&dspi1 {
97 bus-num = <1>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_dspi1>;
100};
101
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100102&edma0 {
103 status = "okay";
104};
105
106&esdhc1 {
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_esdhc1>;
109 bus-width = <4>;
Stefan Agner76713952015-01-16 18:06:15 +0100110 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100111};
112
113&fec1 {
114 phy-mode = "rmii";
Stefan Agner47b06e62016-02-17 15:40:59 -0800115 phy-supply = <&reg_module_3v3>;
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_fec1>;
118};
119
Bhuvanchandra DV1ddeb482014-11-13 10:05:31 +0530120&i2c0 {
121 clock-frequency = <400000>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_i2c0>;
124};
125
Stefan Agner65425262015-10-07 16:58:36 -0700126&nfc {
127 assigned-clocks = <&clks VF610_CLK_NFC>;
128 assigned-clock-rates = <33000000>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_nfc>;
131 status = "okay";
132
133 nand@0 {
134 compatible = "fsl,vf610-nfc-nandcs";
135 reg = <0>;
136 #address-cells = <1>;
137 #size-cells = <1>;
138 nand-bus-width = <8>;
139 nand-ecc-mode = "hw";
140 nand-ecc-strength = <32>;
141 nand-ecc-step-size = <2048>;
142 nand-on-flash-bbt;
143 };
144};
145
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100146&pwm0 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_pwm0>;
149};
150
151&pwm1 {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_pwm1>;
154};
155
156&uart0 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart0>;
159};
160
161&uart1 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_uart1>;
164};
165
166&uart2 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_uart2>;
169};
170
171&usbdev0 {
172 disable-over-current;
173 status = "okay";
174};
175
176&usbh1 {
177 disable-over-current;
178 status = "okay";
179};
180
Stefan Agnerac039cd2014-11-04 14:07:09 +0100181&usbmisc0 {
182 status = "okay";
183};
184
185&usbmisc1 {
186 status = "okay";
187};
188
189&usbphy0 {
190 status = "okay";
191};
192
193&usbphy1 {
194 status = "okay";
195};
196
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100197&iomuxc {
198 vf610-colibri {
Stefan Agner2afa06c2015-12-02 14:11:47 -0800199 pinctrl_flexcan0: can0grp {
200 fsl,pins = <
201 VF610_PAD_PTB14__CAN0_RX 0x31F1
202 VF610_PAD_PTB15__CAN0_TX 0x31F2
203 >;
204 };
205
206 pinctrl_flexcan1: can1grp {
207 fsl,pins = <
208 VF610_PAD_PTB16__CAN1_RX 0x31F1
209 VF610_PAD_PTB17__CAN1_TX 0x31F2
210 >;
211 };
212
Stefan Agner2b36bda2014-11-04 14:07:08 +0100213 pinctrl_gpio_ext: gpio_ext {
214 fsl,pins = <
215 VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
216 VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
217 VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
218 >;
219 };
220
Bhuvanchandra DV9fca0152015-01-29 21:57:45 +0530221 pinctrl_dspi1: dspi1grp {
222 fsl,pins = <
223 VF610_PAD_PTD5__DSPI1_CS0 0x33e2
224 VF610_PAD_PTD6__DSPI1_SIN 0x33e1
225 VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
226 VF610_PAD_PTD8__DSPI1_SCK 0x33e2
227 >;
228 };
229
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100230 pinctrl_esdhc1: esdhc1grp {
231 fsl,pins = <
232 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
233 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
234 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
235 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
236 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
237 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
238 VF610_PAD_PTB20__GPIO_42 0x219d
239 >;
240 };
241
242 pinctrl_fec1: fec1grp {
243 fsl,pins = <
Stefan Agnereddb00f2014-11-28 00:40:06 +0100244 VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100245 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
246 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
247 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
Cory Tusaraa5fec22015-05-13 23:11:38 -0400248 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100249 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
250 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
251 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
252 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
253 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
254 >;
255 };
256
Bhuvanchandra DVb2e42442016-01-09 12:29:53 +0530257 pinctrl_gpio_bl_on: gpio_bl_on {
258 fsl,pins = <
259 VF610_PAD_PTC0__GPIO_45 0x22ef
260 >;
261 };
262
Bhuvanchandra DV1ddeb482014-11-13 10:05:31 +0530263 pinctrl_i2c0: i2c0grp {
264 fsl,pins = <
265 VF610_PAD_PTB14__I2C0_SCL 0x37ff
266 VF610_PAD_PTB15__I2C0_SDA 0x37ff
267 >;
268 };
269
Stefan Agner65425262015-10-07 16:58:36 -0700270 pinctrl_nfc: nfcgrp {
271 fsl,pins = <
272 VF610_PAD_PTD23__NF_IO7 0x28df
273 VF610_PAD_PTD22__NF_IO6 0x28df
274 VF610_PAD_PTD21__NF_IO5 0x28df
275 VF610_PAD_PTD20__NF_IO4 0x28df
276 VF610_PAD_PTD19__NF_IO3 0x28df
277 VF610_PAD_PTD18__NF_IO2 0x28df
278 VF610_PAD_PTD17__NF_IO1 0x28df
279 VF610_PAD_PTD16__NF_IO0 0x28df
280 VF610_PAD_PTB24__NF_WE_B 0x28c2
281 VF610_PAD_PTB25__NF_CE0_B 0x28c2
282 VF610_PAD_PTB27__NF_RE_B 0x28c2
283 VF610_PAD_PTC26__NF_RB_B 0x283d
284 VF610_PAD_PTC27__NF_ALE 0x28c2
285 VF610_PAD_PTC28__NF_CLE 0x28c2
286 >;
287 };
288
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100289 pinctrl_pwm0: pwm0grp {
290 fsl,pins = <
291 VF610_PAD_PTB0__FTM0_CH0 0x1182
292 VF610_PAD_PTB1__FTM0_CH1 0x1182
293 >;
294 };
295
296 pinctrl_pwm1: pwm1grp {
297 fsl,pins = <
298 VF610_PAD_PTB8__FTM1_CH0 0x1182
299 VF610_PAD_PTB9__FTM1_CH1 0x1182
300 >;
301 };
302
303 pinctrl_uart0: uart0grp {
304 fsl,pins = <
305 VF610_PAD_PTB10__UART0_TX 0x21a2
306 VF610_PAD_PTB11__UART0_RX 0x21a1
307 >;
308 };
309
310 pinctrl_uart1: uart1grp {
311 fsl,pins = <
312 VF610_PAD_PTB4__UART1_TX 0x21a2
313 VF610_PAD_PTB5__UART1_RX 0x21a1
314 >;
315 };
316
317 pinctrl_uart2: uart2grp {
318 fsl,pins = <
319 VF610_PAD_PTD0__UART2_TX 0x21a2
320 VF610_PAD_PTD1__UART2_RX 0x21a1
321 VF610_PAD_PTD2__UART2_RTS 0x21a2
322 VF610_PAD_PTD3__UART2_CTS 0x21a1
323 >;
324 };
Stefan Agner505251e2014-11-16 19:00:28 +0100325
326 pinctrl_usbh1_reg: gpio_usb_vbus {
327 fsl,pins = <
328 VF610_PAD_PTD4__GPIO_83 0x22ed
329 >;
330 };
Stefan Agnere1bf86a2014-11-02 21:36:47 +0100331 };
332};