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gerrit-public.fairphone.software / kernel / msm-4.19 / 497b90db5e4643fc41dc5761e01198c50b7d9954 / . / arch / arm / boot / dts / imx28.dtsi
blob: ee3396d21c014b0fbebd1189619fc9b3c6467f32 [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Michael Heimpold25fc2282014-03-27 23:51:29 +0100[diff] [blame]12#include <dt-bindings/gpio/gpio.h>
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]13#include "imx28-pinfunc.h"
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]14
15/ {
Fabio Estevam7f107882016-11-12 13:30:35 -0200[diff] [blame]16 #address-cells = <1>;
17 #size-cells = <1>;
18
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]19 interrupt-parent = <&icoll>;
Fabio Estevama971c552017-01-23 14:54:10 -0200[diff] [blame]20 /*
21 * The decompressor and also some bootloaders rely on a
22 * pre-existing /chosen node to be available to insert the
23 * command line and merge other ATAGS info.
24 * Also for U-Boot there must be a pre-existing /memory node.
25 */
26 chosen {};
27 memory { device_type = "memory"; reg = <0 0>; };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]28
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]29 aliases {
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]32 gpio0 = &gpio0;
33 gpio1 = &gpio1;
34 gpio2 = &gpio2;
35 gpio3 = &gpio3;
36 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]37 saif0 = &saif0;
38 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]39 serial0 = &auart0;
40 serial1 = &auart1;
41 serial2 = &auart2;
42 serial3 = &auart3;
43 serial4 = &auart4;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]44 spi0 = &ssp1;
45 spi1 = &ssp2;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame]46 usbphy0 = &usbphy0;
47 usbphy1 = &usbphy1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]48 };
49
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]50 cpus {
Fabio Estevamd447dd82016-11-16 13:15:38 -0200[diff] [blame]51 #address-cells = <1>;
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]52 #size-cells = <0>;
53
Fabio Estevamd447dd82016-11-16 13:15:38 -0200[diff] [blame]54 cpu@0 {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]55 compatible = "arm,arm926ej-s";
56 device_type = "cpu";
Fabio Estevamd447dd82016-11-16 13:15:38 -0200[diff] [blame]57 reg = <0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]58 };
59 };
60
61 apb@80000000 {
62 compatible = "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x80000000 0x80000>;
66 ranges;
67
68 apbh@80000000 {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 reg = <0x80000000 0x3c900>;
73 ranges;
74
75 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]76 compatible = "fsl,imx28-icoll", "fsl,icoll";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]77 interrupt-controller;
78 #interrupt-cells = <1>;
79 reg = <0x80000000 0x2000>;
80 };
81
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]82 hsadc: hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]83 reg = <0x80002000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]84 interrupts = <13>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]85 dmas = <&dma_apbh 12>;
86 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]87 status = "disabled";
88 };
89
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]90 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]91 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]92 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]93 interrupts = <82 83 84 85
94 88 88 88 88
95 88 88 88 88
96 87 86 0 0>;
97 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
98 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
99 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
100 "hsadc", "lcdif", "empty", "empty";
101 #dma-cells = <1>;
102 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]103 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]104 };
105
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]106 perfmon: perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]107 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]108 interrupts = <27>;
109 status = "disabled";
110 };
111
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]112 gpmi: gpmi-nand@8000c000 {
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]113 compatible = "fsl,imx28-gpmi-nand";
114 #address-cells = <1>;
115 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]116 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]117 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]118 interrupts = <41>;
119 interrupt-names = "bch";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]120 clocks = <&clks 50>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]121 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]122 dmas = <&dma_apbh 4>;
123 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]124 status = "disabled";
125 };
126
127 ssp0: ssp@80010000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]128 #address-cells = <1>;
129 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]130 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]131 interrupts = <96>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]132 clocks = <&clks 46>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]133 dmas = <&dma_apbh 0>;
134 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]135 status = "disabled";
136 };
137
138 ssp1: ssp@80012000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]139 #address-cells = <1>;
140 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]141 reg = <0x80012000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]142 interrupts = <97>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]143 clocks = <&clks 47>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]144 dmas = <&dma_apbh 1>;
145 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]146 status = "disabled";
147 };
148
149 ssp2: ssp@80014000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]150 #address-cells = <1>;
151 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]152 reg = <0x80014000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]153 interrupts = <98>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]154 clocks = <&clks 48>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]155 dmas = <&dma_apbh 2>;
156 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]157 status = "disabled";
158 };
159
160 ssp3: ssp@80016000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]161 #address-cells = <1>;
162 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]163 reg = <0x80016000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]164 interrupts = <99>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]165 clocks = <&clks 49>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]166 dmas = <&dma_apbh 3>;
167 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]168 status = "disabled";
169 };
170
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]171 pinctrl: pinctrl@80018000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]172 #address-cells = <1>;
173 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]174 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]175 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]176
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]177 gpio0: gpio@0 {
178 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]179 reg = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]180 interrupts = <127>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 };
186
187 gpio1: gpio@1 {
188 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]189 reg = <1>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]190 interrupts = <126>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196
197 gpio2: gpio@2 {
198 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]199 reg = <2>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]200 interrupts = <125>;
201 gpio-controller;
202 #gpio-cells = <2>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 };
206
207 gpio3: gpio@3 {
208 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]209 reg = <3>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]210 interrupts = <124>;
211 gpio-controller;
212 #gpio-cells = <2>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
215 };
216
217 gpio4: gpio@4 {
218 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]219 reg = <4>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]220 interrupts = <123>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 };
226
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]227 duart_pins_a: duart@0 {
228 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]229 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]230 MX28_PAD_PWM0__DUART_RX
231 MX28_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]232 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]233 fsl,drive-strength = <MXS_DRIVE_4mA>;
234 fsl,voltage = <MXS_VOLTAGE_HIGH>;
235 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]236 };
237
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]238 duart_pins_b: duart@1 {
239 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]240 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]241 MX28_PAD_AUART0_CTS__DUART_RX
242 MX28_PAD_AUART0_RTS__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]243 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]244 fsl,drive-strength = <MXS_DRIVE_4mA>;
245 fsl,voltage = <MXS_VOLTAGE_HIGH>;
246 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]247 };
248
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]249 duart_4pins_a: duart-4pins@0 {
250 reg = <0>;
251 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]252 MX28_PAD_AUART0_CTS__DUART_RX
253 MX28_PAD_AUART0_RTS__DUART_TX
254 MX28_PAD_AUART0_RX__DUART_CTS
255 MX28_PAD_AUART0_TX__DUART_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]256 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]257 fsl,drive-strength = <MXS_DRIVE_4mA>;
258 fsl,voltage = <MXS_VOLTAGE_HIGH>;
259 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]260 };
261
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]262 gpmi_pins_a: gpmi-nand@0 {
263 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]264 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]265 MX28_PAD_GPMI_D00__GPMI_D0
266 MX28_PAD_GPMI_D01__GPMI_D1
267 MX28_PAD_GPMI_D02__GPMI_D2
268 MX28_PAD_GPMI_D03__GPMI_D3
269 MX28_PAD_GPMI_D04__GPMI_D4
270 MX28_PAD_GPMI_D05__GPMI_D5
271 MX28_PAD_GPMI_D06__GPMI_D6
272 MX28_PAD_GPMI_D07__GPMI_D7
273 MX28_PAD_GPMI_CE0N__GPMI_CE0N
274 MX28_PAD_GPMI_RDY0__GPMI_READY0
275 MX28_PAD_GPMI_RDN__GPMI_RDN
276 MX28_PAD_GPMI_WRN__GPMI_WRN
277 MX28_PAD_GPMI_ALE__GPMI_ALE
278 MX28_PAD_GPMI_CLE__GPMI_CLE
279 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]280 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]281 fsl,drive-strength = <MXS_DRIVE_4mA>;
282 fsl,voltage = <MXS_VOLTAGE_HIGH>;
283 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]284 };
285
Fabio Estevam497b90d2017-12-27 12:04:35 -0200[diff] [blame^]286 gpmi_status_cfg: gpmi-status-cfg@0 {
287 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]288 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]289 MX28_PAD_GPMI_RDN__GPMI_RDN
290 MX28_PAD_GPMI_WRN__GPMI_WRN
291 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]292 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]293 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]294 };
295
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]296 auart0_pins_a: auart0@0 {
297 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]298 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]299 MX28_PAD_AUART0_RX__AUART0_RX
300 MX28_PAD_AUART0_TX__AUART0_TX
301 MX28_PAD_AUART0_CTS__AUART0_CTS
302 MX28_PAD_AUART0_RTS__AUART0_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]303 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]304 fsl,drive-strength = <MXS_DRIVE_4mA>;
305 fsl,voltage = <MXS_VOLTAGE_HIGH>;
306 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]307 };
308
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]309 auart0_2pins_a: auart0-2pins@0 {
310 reg = <0>;
311 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]312 MX28_PAD_AUART0_RX__AUART0_RX
313 MX28_PAD_AUART0_TX__AUART0_TX
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]314 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]315 fsl,drive-strength = <MXS_DRIVE_4mA>;
316 fsl,voltage = <MXS_VOLTAGE_HIGH>;
317 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]318 };
319
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]320 auart1_pins_a: auart1@0 {
321 reg = <0>;
322 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]323 MX28_PAD_AUART1_RX__AUART1_RX
324 MX28_PAD_AUART1_TX__AUART1_TX
325 MX28_PAD_AUART1_CTS__AUART1_CTS
326 MX28_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]327 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]328 fsl,drive-strength = <MXS_DRIVE_4mA>;
329 fsl,voltage = <MXS_VOLTAGE_HIGH>;
330 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]331 };
332
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]333 auart1_2pins_a: auart1-2pins@0 {
334 reg = <0>;
335 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]336 MX28_PAD_AUART1_RX__AUART1_RX
337 MX28_PAD_AUART1_TX__AUART1_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]338 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]339 fsl,drive-strength = <MXS_DRIVE_4mA>;
340 fsl,voltage = <MXS_VOLTAGE_HIGH>;
341 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]342 };
343
344 auart2_2pins_a: auart2-2pins@0 {
345 reg = <0>;
346 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]347 MX28_PAD_SSP2_SCK__AUART2_RX
348 MX28_PAD_SSP2_MOSI__AUART2_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]349 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]350 fsl,drive-strength = <MXS_DRIVE_4mA>;
351 fsl,voltage = <MXS_VOLTAGE_HIGH>;
352 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]353 };
354
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]355 auart2_2pins_b: auart2-2pins@1 {
356 reg = <1>;
357 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]358 MX28_PAD_AUART2_RX__AUART2_RX
359 MX28_PAD_AUART2_TX__AUART2_TX
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]360 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]361 fsl,drive-strength = <MXS_DRIVE_4mA>;
362 fsl,voltage = <MXS_VOLTAGE_HIGH>;
363 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]364 };
365
Aida Mynzhasovacd0214c2013-10-23 10:58:57 +0400[diff] [blame]366 auart2_pins_a: auart2-pins@0 {
367 reg = <0>;
368 fsl,pinmux-ids = <
369 MX28_PAD_AUART2_RX__AUART2_RX
370 MX28_PAD_AUART2_TX__AUART2_TX
371 MX28_PAD_AUART2_CTS__AUART2_CTS
372 MX28_PAD_AUART2_RTS__AUART2_RTS
373 >;
374 fsl,drive-strength = <MXS_DRIVE_4mA>;
375 fsl,voltage = <MXS_VOLTAGE_HIGH>;
376 fsl,pull-up = <MXS_PULL_DISABLE>;
377 };
378
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]379 auart3_pins_a: auart3@0 {
380 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]381 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]382 MX28_PAD_AUART3_RX__AUART3_RX
383 MX28_PAD_AUART3_TX__AUART3_TX
384 MX28_PAD_AUART3_CTS__AUART3_CTS
385 MX28_PAD_AUART3_RTS__AUART3_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]386 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]387 fsl,drive-strength = <MXS_DRIVE_4mA>;
388 fsl,voltage = <MXS_VOLTAGE_HIGH>;
389 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]390 };
391
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]392 auart3_2pins_a: auart3-2pins@0 {
393 reg = <0>;
394 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]395 MX28_PAD_SSP2_MISO__AUART3_RX
396 MX28_PAD_SSP2_SS0__AUART3_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]397 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]398 fsl,drive-strength = <MXS_DRIVE_4mA>;
399 fsl,voltage = <MXS_VOLTAGE_HIGH>;
400 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]401 };
402
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]403 auart3_2pins_b: auart3-2pins@1 {
404 reg = <1>;
405 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]406 MX28_PAD_AUART3_RX__AUART3_RX
407 MX28_PAD_AUART3_TX__AUART3_TX
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]408 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]409 fsl,drive-strength = <MXS_DRIVE_4mA>;
410 fsl,voltage = <MXS_VOLTAGE_HIGH>;
411 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]412 };
413
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]414 auart4_2pins_a: auart4@0 {
415 reg = <0>;
416 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]417 MX28_PAD_SSP3_SCK__AUART4_TX
418 MX28_PAD_SSP3_MOSI__AUART4_RX
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]419 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]420 fsl,drive-strength = <MXS_DRIVE_4mA>;
421 fsl,voltage = <MXS_VOLTAGE_HIGH>;
422 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]423 };
424
Mans Rullgardcfa1dd92015-12-11 13:36:26 +0000[diff] [blame]425 auart4_2pins_b: auart4@1 {
426 reg = <1>;
427 fsl,pinmux-ids = <
428 MX28_PAD_AUART0_CTS__AUART4_RX
429 MX28_PAD_AUART0_RTS__AUART4_TX
430 >;
431 fsl,drive-strength = <MXS_DRIVE_4mA>;
432 fsl,voltage = <MXS_VOLTAGE_HIGH>;
433 fsl,pull-up = <MXS_PULL_DISABLE>;
434 };
435
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]436 mac0_pins_a: mac0@0 {
437 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]438 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]439 MX28_PAD_ENET0_MDC__ENET0_MDC
440 MX28_PAD_ENET0_MDIO__ENET0_MDIO
441 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
442 MX28_PAD_ENET0_RXD0__ENET0_RXD0
443 MX28_PAD_ENET0_RXD1__ENET0_RXD1
444 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
445 MX28_PAD_ENET0_TXD0__ENET0_TXD0
446 MX28_PAD_ENET0_TXD1__ENET0_TXD1
447 MX28_PAD_ENET_CLK__CLKCTRL_ENET
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]448 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]449 fsl,drive-strength = <MXS_DRIVE_8mA>;
450 fsl,voltage = <MXS_VOLTAGE_HIGH>;
451 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]452 };
453
Uwe Kleine-König9eb7db12016-04-06 09:32:59 +0200[diff] [blame]454 mac0_pins_b: mac0@1 {
455 reg = <1>;
456 fsl,pinmux-ids = <
457 MX28_PAD_ENET0_MDC__ENET0_MDC
458 MX28_PAD_ENET0_MDIO__ENET0_MDIO
459 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
460 MX28_PAD_ENET0_RXD0__ENET0_RXD0
461 MX28_PAD_ENET0_RXD1__ENET0_RXD1
462 MX28_PAD_ENET0_RXD2__ENET0_RXD2
463 MX28_PAD_ENET0_RXD3__ENET0_RXD3
464 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
465 MX28_PAD_ENET0_TXD0__ENET0_TXD0
466 MX28_PAD_ENET0_TXD1__ENET0_TXD1
467 MX28_PAD_ENET0_TXD2__ENET0_TXD2
468 MX28_PAD_ENET0_TXD3__ENET0_TXD3
469 MX28_PAD_ENET_CLK__CLKCTRL_ENET
470 MX28_PAD_ENET0_COL__ENET0_COL
471 MX28_PAD_ENET0_CRS__ENET0_CRS
472 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
473 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
474 >;
475 fsl,drive-strength = <MXS_DRIVE_8mA>;
476 fsl,voltage = <MXS_VOLTAGE_HIGH>;
477 fsl,pull-up = <MXS_PULL_ENABLE>;
478 };
479
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]480 mac1_pins_a: mac1@0 {
481 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]482 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]483 MX28_PAD_ENET0_CRS__ENET1_RX_EN
484 MX28_PAD_ENET0_RXD2__ENET1_RXD0
485 MX28_PAD_ENET0_RXD3__ENET1_RXD1
486 MX28_PAD_ENET0_COL__ENET1_TX_EN
487 MX28_PAD_ENET0_TXD2__ENET1_TXD0
488 MX28_PAD_ENET0_TXD3__ENET1_TXD1
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]489 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]490 fsl,drive-strength = <MXS_DRIVE_8mA>;
491 fsl,voltage = <MXS_VOLTAGE_HIGH>;
492 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]493 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]494
495 mmc0_8bit_pins_a: mmc0-8bit@0 {
496 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]497 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]498 MX28_PAD_SSP0_DATA0__SSP0_D0
499 MX28_PAD_SSP0_DATA1__SSP0_D1
500 MX28_PAD_SSP0_DATA2__SSP0_D2
501 MX28_PAD_SSP0_DATA3__SSP0_D3
502 MX28_PAD_SSP0_DATA4__SSP0_D4
503 MX28_PAD_SSP0_DATA5__SSP0_D5
504 MX28_PAD_SSP0_DATA6__SSP0_D6
505 MX28_PAD_SSP0_DATA7__SSP0_D7
506 MX28_PAD_SSP0_CMD__SSP0_CMD
507 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
508 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]509 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]510 fsl,drive-strength = <MXS_DRIVE_8mA>;
511 fsl,voltage = <MXS_VOLTAGE_HIGH>;
512 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]513 };
514
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]515 mmc0_4bit_pins_a: mmc0-4bit@0 {
516 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]517 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]518 MX28_PAD_SSP0_DATA0__SSP0_D0
519 MX28_PAD_SSP0_DATA1__SSP0_D1
520 MX28_PAD_SSP0_DATA2__SSP0_D2
521 MX28_PAD_SSP0_DATA3__SSP0_D3
522 MX28_PAD_SSP0_CMD__SSP0_CMD
523 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
524 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]525 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]526 fsl,drive-strength = <MXS_DRIVE_8mA>;
527 fsl,voltage = <MXS_VOLTAGE_HIGH>;
528 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]529 };
530
Fabio Estevam497b90d2017-12-27 12:04:35 -0200[diff] [blame^]531 mmc0_cd_cfg: mmc0-cd-cfg@0 {
532 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]533 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]534 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]535 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]536 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]537 };
538
Fabio Estevam497b90d2017-12-27 12:04:35 -0200[diff] [blame^]539 mmc0_sck_cfg: mmc0-sck-cfg@0 {
540 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]541 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]542 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]543 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]544 fsl,drive-strength = <MXS_DRIVE_12mA>;
545 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]546 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]547
Marc Kleine-Budde77d63862014-08-08 11:24:21 +0200[diff] [blame]548 mmc1_4bit_pins_a: mmc1-4bit@0 {
549 reg = <0>;
550 fsl,pinmux-ids = <
551 MX28_PAD_GPMI_D00__SSP1_D0
552 MX28_PAD_GPMI_D01__SSP1_D1
553 MX28_PAD_GPMI_D02__SSP1_D2
554 MX28_PAD_GPMI_D03__SSP1_D3
555 MX28_PAD_GPMI_RDY1__SSP1_CMD
556 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
557 MX28_PAD_GPMI_WRN__SSP1_SCK
558 >;
559 fsl,drive-strength = <MXS_DRIVE_8mA>;
560 fsl,voltage = <MXS_VOLTAGE_HIGH>;
561 fsl,pull-up = <MXS_PULL_ENABLE>;
562 };
563
Fabio Estevam497b90d2017-12-27 12:04:35 -0200[diff] [blame^]564 mmc1_cd_cfg: mmc1-cd-cfg@0 {
565 reg = <0>;
Marc Kleine-Budde77d63862014-08-08 11:24:21 +0200[diff] [blame]566 fsl,pinmux-ids = <
567 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
568 >;
569 fsl,pull-up = <MXS_PULL_DISABLE>;
570 };
571
Fabio Estevam497b90d2017-12-27 12:04:35 -0200[diff] [blame^]572 mmc1_sck_cfg: mmc1-sck-cfg@0 {
573 reg = <0>;
Marc Kleine-Budde77d63862014-08-08 11:24:21 +0200[diff] [blame]574 fsl,pinmux-ids = <
575 MX28_PAD_GPMI_WRN__SSP1_SCK
576 >;
577 fsl,drive-strength = <MXS_DRIVE_12mA>;
578 fsl,pull-up = <MXS_PULL_DISABLE>;
579 };
580
581
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]582 mmc2_4bit_pins_a: mmc2-4bit@0 {
583 reg = <0>;
584 fsl,pinmux-ids = <
585 MX28_PAD_SSP0_DATA4__SSP2_D0
586 MX28_PAD_SSP1_SCK__SSP2_D1
587 MX28_PAD_SSP1_CMD__SSP2_D2
588 MX28_PAD_SSP0_DATA5__SSP2_D3
589 MX28_PAD_SSP0_DATA6__SSP2_CMD
590 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
591 MX28_PAD_SSP0_DATA7__SSP2_SCK
592 >;
593 fsl,drive-strength = <MXS_DRIVE_8mA>;
594 fsl,voltage = <MXS_VOLTAGE_HIGH>;
595 fsl,pull-up = <MXS_PULL_ENABLE>;
596 };
597
Michael Heimpolddf937262017-02-09 08:42:41 +0100[diff] [blame]598 mmc2_4bit_pins_b: mmc2-4bit@1 {
599 reg = <1>;
600 fsl,pinmux-ids = <
601 MX28_PAD_SSP2_SCK__SSP2_SCK
602 MX28_PAD_SSP2_MOSI__SSP2_CMD
603 MX28_PAD_SSP2_MISO__SSP2_D0
604 MX28_PAD_SSP2_SS0__SSP2_D3
605 MX28_PAD_SSP2_SS1__SSP2_D1
606 MX28_PAD_SSP2_SS2__SSP2_D2
607 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
608 >;
609 fsl,drive-strength = <MXS_DRIVE_8mA>;
610 fsl,voltage = <MXS_VOLTAGE_HIGH>;
611 fsl,pull-up = <MXS_PULL_ENABLE>;
612 };
613
Fabio Estevam497b90d2017-12-27 12:04:35 -0200[diff] [blame^]614 mmc2_cd_cfg: mmc2-cd-cfg@0 {
615 reg = <0>;
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]616 fsl,pinmux-ids = <
617 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
618 >;
619 fsl,pull-up = <MXS_PULL_DISABLE>;
620 };
621
Michael Heimpold45e89542017-02-09 08:42:42 +0100[diff] [blame]622 mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
623 reg = <0>;
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]624 fsl,pinmux-ids = <
625 MX28_PAD_SSP0_DATA7__SSP2_SCK
626 >;
627 fsl,drive-strength = <MXS_DRIVE_12mA>;
628 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]629 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]630
Michael Heimpold620885e2017-02-09 08:42:43 +0100[diff] [blame]631 mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
632 reg = <1>;
633 fsl,pinmux-ids = <
634 MX28_PAD_SSP2_SCK__SSP2_SCK
635 >;
636 fsl,drive-strength = <MXS_DRIVE_12mA>;
637 fsl,pull-up = <MXS_PULL_DISABLE>;
638 };
639
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]640 i2c0_pins_a: i2c0@0 {
641 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]642 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]643 MX28_PAD_I2C0_SCL__I2C0_SCL
644 MX28_PAD_I2C0_SDA__I2C0_SDA
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]645 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]646 fsl,drive-strength = <MXS_DRIVE_8mA>;
647 fsl,voltage = <MXS_VOLTAGE_HIGH>;
648 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]649 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]650
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]651 i2c0_pins_b: i2c0@1 {
652 reg = <1>;
653 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]654 MX28_PAD_AUART0_RX__I2C0_SCL
655 MX28_PAD_AUART0_TX__I2C0_SDA
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]656 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]657 fsl,drive-strength = <MXS_DRIVE_8mA>;
658 fsl,voltage = <MXS_VOLTAGE_HIGH>;
659 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]660 };
661
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]662 i2c1_pins_a: i2c1@0 {
663 reg = <0>;
664 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]665 MX28_PAD_PWM0__I2C1_SCL
666 MX28_PAD_PWM1__I2C1_SDA
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]667 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]668 fsl,drive-strength = <MXS_DRIVE_8mA>;
669 fsl,voltage = <MXS_VOLTAGE_HIGH>;
670 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]671 };
672
Uwe Kleine-König17c63dd2014-08-08 11:24:22 +0200[diff] [blame]673 i2c1_pins_b: i2c1@1 {
674 reg = <1>;
675 fsl,pinmux-ids = <
676 MX28_PAD_AUART2_CTS__I2C1_SCL
677 MX28_PAD_AUART2_RTS__I2C1_SDA
678 >;
679 fsl,drive-strength = <MXS_DRIVE_8mA>;
680 fsl,voltage = <MXS_VOLTAGE_HIGH>;
681 fsl,pull-up = <MXS_PULL_ENABLE>;
682 };
683
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]684 saif0_pins_a: saif0@0 {
685 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]686 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]687 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
688 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
689 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
690 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]691 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]692 fsl,drive-strength = <MXS_DRIVE_12mA>;
693 fsl,voltage = <MXS_VOLTAGE_HIGH>;
694 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]695 };
696
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]697 saif0_pins_b: saif0@1 {
698 reg = <1>;
699 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]700 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
701 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
702 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]703 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]704 fsl,drive-strength = <MXS_DRIVE_12mA>;
705 fsl,voltage = <MXS_VOLTAGE_HIGH>;
706 fsl,pull-up = <MXS_PULL_ENABLE>;
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]707 };
708
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]709 saif1_pins_a: saif1@0 {
710 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]711 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]712 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]713 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]714 fsl,drive-strength = <MXS_DRIVE_12mA>;
715 fsl,voltage = <MXS_VOLTAGE_HIGH>;
716 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]717 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]718
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]719 pwm0_pins_a: pwm0@0 {
720 reg = <0>;
721 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]722 MX28_PAD_PWM0__PWM_0
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]723 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]724 fsl,drive-strength = <MXS_DRIVE_4mA>;
725 fsl,voltage = <MXS_VOLTAGE_HIGH>;
726 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]727 };
728
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]729 pwm2_pins_a: pwm2@0 {
730 reg = <0>;
731 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]732 MX28_PAD_PWM2__PWM_2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]733 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]734 fsl,drive-strength = <MXS_DRIVE_4mA>;
735 fsl,voltage = <MXS_VOLTAGE_HIGH>;
736 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]737 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]738
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]739 pwm3_pins_a: pwm3@0 {
740 reg = <0>;
741 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]742 MX28_PAD_PWM3__PWM_3
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]743 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]744 fsl,drive-strength = <MXS_DRIVE_4mA>;
745 fsl,voltage = <MXS_VOLTAGE_HIGH>;
746 fsl,pull-up = <MXS_PULL_DISABLE>;
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]747 };
748
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]749 pwm3_pins_b: pwm3@1 {
750 reg = <1>;
751 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]752 MX28_PAD_SAIF0_MCLK__PWM_3
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]753 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]754 fsl,drive-strength = <MXS_DRIVE_4mA>;
755 fsl,voltage = <MXS_VOLTAGE_HIGH>;
756 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]757 };
758
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]759 pwm4_pins_a: pwm4@0 {
760 reg = <0>;
761 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]762 MX28_PAD_PWM4__PWM_4
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]763 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]764 fsl,drive-strength = <MXS_DRIVE_4mA>;
765 fsl,voltage = <MXS_VOLTAGE_HIGH>;
766 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]767 };
768
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]769 lcdif_24bit_pins_a: lcdif-24bit@0 {
770 reg = <0>;
771 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]772 MX28_PAD_LCD_D00__LCD_D0
773 MX28_PAD_LCD_D01__LCD_D1
774 MX28_PAD_LCD_D02__LCD_D2
775 MX28_PAD_LCD_D03__LCD_D3
776 MX28_PAD_LCD_D04__LCD_D4
777 MX28_PAD_LCD_D05__LCD_D5
778 MX28_PAD_LCD_D06__LCD_D6
779 MX28_PAD_LCD_D07__LCD_D7
780 MX28_PAD_LCD_D08__LCD_D8
781 MX28_PAD_LCD_D09__LCD_D9
782 MX28_PAD_LCD_D10__LCD_D10
783 MX28_PAD_LCD_D11__LCD_D11
784 MX28_PAD_LCD_D12__LCD_D12
785 MX28_PAD_LCD_D13__LCD_D13
786 MX28_PAD_LCD_D14__LCD_D14
787 MX28_PAD_LCD_D15__LCD_D15
788 MX28_PAD_LCD_D16__LCD_D16
789 MX28_PAD_LCD_D17__LCD_D17
790 MX28_PAD_LCD_D18__LCD_D18
791 MX28_PAD_LCD_D19__LCD_D19
792 MX28_PAD_LCD_D20__LCD_D20
793 MX28_PAD_LCD_D21__LCD_D21
794 MX28_PAD_LCD_D22__LCD_D22
795 MX28_PAD_LCD_D23__LCD_D23
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]796 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]797 fsl,drive-strength = <MXS_DRIVE_4mA>;
798 fsl,voltage = <MXS_VOLTAGE_HIGH>;
799 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]800 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]801
Denis Carikliec985eb2013-12-05 14:28:04 +0100[diff] [blame]802 lcdif_18bit_pins_a: lcdif-18bit@0 {
803 reg = <0>;
804 fsl,pinmux-ids = <
805 MX28_PAD_LCD_D00__LCD_D0
806 MX28_PAD_LCD_D01__LCD_D1
807 MX28_PAD_LCD_D02__LCD_D2
808 MX28_PAD_LCD_D03__LCD_D3
809 MX28_PAD_LCD_D04__LCD_D4
810 MX28_PAD_LCD_D05__LCD_D5
811 MX28_PAD_LCD_D06__LCD_D6
812 MX28_PAD_LCD_D07__LCD_D7
813 MX28_PAD_LCD_D08__LCD_D8
814 MX28_PAD_LCD_D09__LCD_D9
815 MX28_PAD_LCD_D10__LCD_D10
816 MX28_PAD_LCD_D11__LCD_D11
817 MX28_PAD_LCD_D12__LCD_D12
818 MX28_PAD_LCD_D13__LCD_D13
819 MX28_PAD_LCD_D14__LCD_D14
820 MX28_PAD_LCD_D15__LCD_D15
821 MX28_PAD_LCD_D16__LCD_D16
822 MX28_PAD_LCD_D17__LCD_D17
823 >;
824 fsl,drive-strength = <MXS_DRIVE_4mA>;
825 fsl,voltage = <MXS_VOLTAGE_HIGH>;
826 fsl,pull-up = <MXS_PULL_DISABLE>;
827 };
828
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]829 lcdif_16bit_pins_a: lcdif-16bit@0 {
830 reg = <0>;
831 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]832 MX28_PAD_LCD_D00__LCD_D0
833 MX28_PAD_LCD_D01__LCD_D1
834 MX28_PAD_LCD_D02__LCD_D2
835 MX28_PAD_LCD_D03__LCD_D3
836 MX28_PAD_LCD_D04__LCD_D4
837 MX28_PAD_LCD_D05__LCD_D5
838 MX28_PAD_LCD_D06__LCD_D6
839 MX28_PAD_LCD_D07__LCD_D7
840 MX28_PAD_LCD_D08__LCD_D8
841 MX28_PAD_LCD_D09__LCD_D9
842 MX28_PAD_LCD_D10__LCD_D10
843 MX28_PAD_LCD_D11__LCD_D11
844 MX28_PAD_LCD_D12__LCD_D12
845 MX28_PAD_LCD_D13__LCD_D13
846 MX28_PAD_LCD_D14__LCD_D14
847 MX28_PAD_LCD_D15__LCD_D15
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]848 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]849 fsl,drive-strength = <MXS_DRIVE_4mA>;
850 fsl,voltage = <MXS_VOLTAGE_HIGH>;
851 fsl,pull-up = <MXS_PULL_DISABLE>;
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]852 };
853
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]854 lcdif_sync_pins_a: lcdif-sync@0 {
855 reg = <0>;
856 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]857 MX28_PAD_LCD_RS__LCD_DOTCLK
858 MX28_PAD_LCD_CS__LCD_ENABLE
859 MX28_PAD_LCD_RD_E__LCD_VSYNC
860 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]861 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]862 fsl,drive-strength = <MXS_DRIVE_4mA>;
863 fsl,voltage = <MXS_VOLTAGE_HIGH>;
864 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]865 };
866
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]867 can0_pins_a: can0@0 {
868 reg = <0>;
869 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]870 MX28_PAD_GPMI_RDY2__CAN0_TX
871 MX28_PAD_GPMI_RDY3__CAN0_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]872 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]873 fsl,drive-strength = <MXS_DRIVE_4mA>;
874 fsl,voltage = <MXS_VOLTAGE_HIGH>;
875 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]876 };
877
878 can1_pins_a: can1@0 {
879 reg = <0>;
880 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]881 MX28_PAD_GPMI_CE2N__CAN1_TX
882 MX28_PAD_GPMI_CE3N__CAN1_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]883 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]884 fsl,drive-strength = <MXS_DRIVE_4mA>;
885 fsl,voltage = <MXS_VOLTAGE_HIGH>;
886 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]887 };
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]888
889 spi2_pins_a: spi2@0 {
890 reg = <0>;
891 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]892 MX28_PAD_SSP2_SCK__SSP2_SCK
893 MX28_PAD_SSP2_MOSI__SSP2_CMD
894 MX28_PAD_SSP2_MISO__SSP2_D0
895 MX28_PAD_SSP2_SS0__SSP2_D3
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]896 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]897 fsl,drive-strength = <MXS_DRIVE_8mA>;
898 fsl,voltage = <MXS_VOLTAGE_HIGH>;
899 fsl,pull-up = <MXS_PULL_ENABLE>;
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]900 };
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]901
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]902 spi3_pins_a: spi3@0 {
903 reg = <0>;
904 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]905 MX28_PAD_AUART2_RX__SSP3_D4
906 MX28_PAD_AUART2_TX__SSP3_D5
907 MX28_PAD_SSP3_SCK__SSP3_SCK
908 MX28_PAD_SSP3_MOSI__SSP3_CMD
909 MX28_PAD_SSP3_MISO__SSP3_D0
910 MX28_PAD_SSP3_SS0__SSP3_D3
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]911 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]912 fsl,drive-strength = <MXS_DRIVE_8mA>;
913 fsl,voltage = <MXS_VOLTAGE_HIGH>;
914 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]915 };
916
Uwe Kleine-König8f0b07a2015-03-19 10:55:47 +0100[diff] [blame]917 spi3_pins_b: spi3@1 {
918 reg = <1>;
919 fsl,pinmux-ids = <
920 MX28_PAD_SSP3_SCK__SSP3_SCK
921 MX28_PAD_SSP3_MOSI__SSP3_CMD
922 MX28_PAD_SSP3_MISO__SSP3_D0
923 MX28_PAD_SSP3_SS0__SSP3_D3
924 >;
925 fsl,drive-strength = <MXS_DRIVE_8mA>;
926 fsl,voltage = <MXS_VOLTAGE_HIGH>;
927 fsl,pull-up = <MXS_PULL_ENABLE>;
928 };
929
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]930 usb0_pins_a: usb0@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]931 reg = <0>;
932 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]933 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]934 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]935 fsl,drive-strength = <MXS_DRIVE_12mA>;
936 fsl,voltage = <MXS_VOLTAGE_HIGH>;
937 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]938 };
939
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]940 usb0_pins_b: usb0@1 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]941 reg = <1>;
942 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]943 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]944 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]945 fsl,drive-strength = <MXS_DRIVE_12mA>;
946 fsl,voltage = <MXS_VOLTAGE_HIGH>;
947 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]948 };
949
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]950 usb1_pins_a: usb1@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]951 reg = <0>;
952 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]953 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]954 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]955 fsl,drive-strength = <MXS_DRIVE_12mA>;
956 fsl,voltage = <MXS_VOLTAGE_HIGH>;
957 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]958 };
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]959
960 usb0_id_pins_a: usb0id@0 {
961 reg = <0>;
962 fsl,pinmux-ids = <
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]963 MX28_PAD_AUART1_RTS__USB0_ID
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]964 >;
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]965 fsl,drive-strength = <MXS_DRIVE_12mA>;
966 fsl,voltage = <MXS_VOLTAGE_HIGH>;
967 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]968 };
Denis Cariklibb89b8d2013-12-05 14:28:05 +0100[diff] [blame]969
970 usb0_id_pins_b: usb0id1@0 {
971 reg = <0>;
972 fsl,pinmux-ids = <
973 MX28_PAD_PWM2__USB0_ID
974 >;
975 fsl,drive-strength = <MXS_DRIVE_12mA>;
976 fsl,voltage = <MXS_VOLTAGE_HIGH>;
977 fsl,pull-up = <MXS_PULL_ENABLE>;
978 };
979
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]980 };
981
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]982 digctl: digctl@8001c000 {
Fabio Estevam115581c2013-06-04 10:18:44 -0300[diff] [blame]983 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]984 reg = <0x8001c000 0x2000>;
985 interrupts = <89>;
986 status = "disabled";
987 };
988
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]989 etm: etm@80022000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]990 reg = <0x80022000 0x2000>;
991 status = "disabled";
992 };
993
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]994 dma_apbx: dma-apbx@80024000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]995 compatible = "fsl,imx28-dma-apbx";
996 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]997 interrupts = <78 79 66 0
998 80 81 68 69
999 70 71 72 73
1000 74 75 76 77>;
Marek Vasut4ada77e2015-04-24 13:29:47 +0200[diff] [blame]1001 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1002 "saif0", "saif1", "i2c0", "i2c1",
1003 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
1004 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
1005 #dma-cells = <1>;
1006 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1007 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1008 };
1009
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1010 dcp: dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]1011 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1012 reg = <0x80028000 0x2000>;
1013 interrupts = <52 53 54>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]1014 status = "okay";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1015 };
1016
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1017 pxp: pxp@8002a000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1018 reg = <0x8002a000 0x2000>;
1019 interrupts = <39>;
1020 status = "disabled";
1021 };
1022
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1023 ocotp: ocotp@8002c000 {
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]1024 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
1025 #address-cells = <1>;
1026 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1027 reg = <0x8002c000 0x2000>;
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]1028 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1029 };
1030
1031 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1032 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1033 status = "disabled";
1034 };
1035
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1036 lcdif: lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]1037 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1038 reg = <0x80030000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1039 interrupts = <38>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1040 clocks = <&clks 55>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1041 dmas = <&dma_apbh 13>;
1042 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1043 status = "disabled";
1044 };
1045
1046 can0: can@80032000 {
Pankaj Bansald50f4632017-11-24 18:52:12 +0530[diff] [blame]1047 compatible = "fsl,imx28-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1048 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1049 interrupts = <8>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1050 clocks = <&clks 58>, <&clks 58>;
1051 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1052 status = "disabled";
1053 };
1054
1055 can1: can@80034000 {
Pankaj Bansald50f4632017-11-24 18:52:12 +0530[diff] [blame]1056 compatible = "fsl,imx28-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1057 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1058 interrupts = <9>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1059 clocks = <&clks 59>, <&clks 59>;
1060 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1061 status = "disabled";
1062 };
1063
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1064 simdbg: simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1065 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1066 status = "disabled";
1067 };
1068
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1069 simgpmisel: simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1070 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1071 status = "disabled";
1072 };
1073
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1074 simsspsel: simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1075 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1076 status = "disabled";
1077 };
1078
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1079 simmemsel: simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1080 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1081 status = "disabled";
1082 };
1083
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1084 gpiomon: gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1085 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1086 status = "disabled";
1087 };
1088
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1089 simenet: simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1090 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1091 status = "disabled";
1092 };
1093
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1094 armjtag: armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1095 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1096 status = "disabled";
1097 };
Lothar Waßmann07a3ce72013-08-08 14:51:20 +0200[diff] [blame]1098 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1099
1100 apbx@80040000 {
1101 compatible = "simple-bus";
1102 #address-cells = <1>;
1103 #size-cells = <1>;
1104 reg = <0x80040000 0x40000>;
1105 ranges;
1106
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1107 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]1108 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1109 reg = <0x80040000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1110 #clock-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1111 };
1112
1113 saif0: saif@80042000 {
Jörg Krause27767d62016-12-20 16:35:16 +0100[diff] [blame]1114 #sound-dai-cells = <0>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1115 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1116 reg = <0x80042000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1117 interrupts = <59>;
Shawn Guo66acaf32013-07-01 15:46:05 +0800[diff] [blame]1118 #clock-cells = <0>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1119 clocks = <&clks 53>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1120 dmas = <&dma_apbx 4>;
1121 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1122 status = "disabled";
1123 };
1124
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1125 power: power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1126 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1127 status = "disabled";
1128 };
1129
1130 saif1: saif@80046000 {
Jörg Krause27767d62016-12-20 16:35:16 +0100[diff] [blame]1131 #sound-dai-cells = <0>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1132 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1133 reg = <0x80046000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1134 interrupts = <58>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1135 clocks = <&clks 54>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1136 dmas = <&dma_apbx 5>;
1137 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1138 status = "disabled";
1139 };
1140
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1141 lradc: lradc@80050000 {
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1142 compatible = "fsl,imx28-lradc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1143 reg = <0x80050000 0x2000>;
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1144 interrupts = <10 14 15 16 17 18 19
1145 20 21 22 23 24 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1146 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]1147 clocks = <&clks 41>;
Alexandre Belloni40dde682013-12-06 21:20:31 +0100[diff] [blame]1148 #io-channel-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1149 };
1150
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1151 spdif: spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1152 reg = <0x80054000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1153 interrupts = <45>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1154 dmas = <&dma_apbx 2>;
1155 dma-names = "tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1156 status = "disabled";
1157 };
1158
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1159 mxs_rtc: rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1160 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1161 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1162 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1163 };
1164
1165 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1169 reg = <0x80058000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1170 interrupts = <111>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1171 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1172 dmas = <&dma_apbx 6>;
1173 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1174 status = "disabled";
1175 };
1176
1177 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1178 #address-cells = <1>;
1179 #size-cells = <0>;
1180 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1181 reg = <0x8005a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1182 interrupts = <110>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1183 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1184 dmas = <&dma_apbx 7>;
1185 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1186 status = "disabled";
1187 };
1188
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1189 pwm: pwm@80064000 {
1190 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1191 reg = <0x80064000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1192 clocks = <&clks 44>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1193 #pwm-cells = <2>;
1194 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1195 status = "disabled";
1196 };
1197
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1198 timer: timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1199 compatible = "fsl,imx28-timrot", "fsl,timrot";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1200 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1201 interrupts = <48 49 50 51>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]1202 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1203 };
1204
1205 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1206 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1207 reg = <0x8006a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1208 interrupts = <112>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1209 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1210 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1211 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1212 status = "disabled";
1213 };
1214
1215 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1216 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1217 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1218 interrupts = <113>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1219 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1220 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1221 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1222 status = "disabled";
1223 };
1224
1225 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1226 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1227 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1228 interrupts = <114>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1229 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1230 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1231 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1232 status = "disabled";
1233 };
1234
1235 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1236 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1237 reg = <0x80070000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1238 interrupts = <115>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1239 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1240 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1241 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1242 status = "disabled";
1243 };
1244
1245 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1246 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1247 reg = <0x80072000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1248 interrupts = <116>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1249 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1250 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1251 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1252 status = "disabled";
1253 };
1254
1255 duart: serial@80074000 {
1256 compatible = "arm,pl011", "arm,primecell";
1257 reg = <0x80074000 0x1000>;
1258 interrupts = <47>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1259 clocks = <&clks 45>, <&clks 26>;
1260 clock-names = "uart", "apb_pclk";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1261 status = "disabled";
1262 };
1263
1264 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1265 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1266 reg = <0x8007c000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1267 clocks = <&clks 62>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1268 status = "disabled";
1269 };
1270
1271 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1272 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1273 reg = <0x8007e000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1274 clocks = <&clks 63>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1275 status = "disabled";
1276 };
1277 };
1278 };
1279
1280 ahb@80080000 {
1281 compatible = "simple-bus";
1282 #address-cells = <1>;
1283 #size-cells = <1>;
1284 reg = <0x80080000 0x80000>;
1285 ranges;
1286
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1287 usb0: usb@80080000 {
1288 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1289 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1290 interrupts = <93>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1291 clocks = <&clks 60>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1292 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1293 status = "disabled";
1294 };
1295
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1296 usb1: usb@80090000 {
1297 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1298 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1299 interrupts = <92>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1300 clocks = <&clks 61>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1301 fsl,usbphy = <&usbphy1>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]1302 dr_mode = "host";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1303 status = "disabled";
1304 };
1305
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1306 dflpt: dflpt@800c0000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1307 reg = <0x800c0000 0x10000>;
1308 status = "disabled";
1309 };
1310
1311 mac0: ethernet@800f0000 {
1312 compatible = "fsl,imx28-fec";
1313 reg = <0x800f0000 0x4000>;
1314 interrupts = <101>;
Wolfram Sangf231a9f2013-01-29 15:46:12 +0100[diff] [blame]1315 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1316 clock-names = "ipg", "ahb", "enet_out";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1317 status = "disabled";
1318 };
1319
1320 mac1: ethernet@800f4000 {
1321 compatible = "fsl,imx28-fec";
1322 reg = <0x800f4000 0x4000>;
1323 interrupts = <102>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1324 clocks = <&clks 57>, <&clks 57>;
1325 clock-names = "ipg", "ahb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1326 status = "disabled";
1327 };
1328
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1329 etn_switch: switch@800f8000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1330 reg = <0x800f8000 0x8000>;
1331 status = "disabled";
1332 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1333 };
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1334
Sanchayan Maity0b452cc2016-02-16 10:30:54 +0530[diff] [blame]1335 iio-hwmon {
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1336 compatible = "iio-hwmon";
1337 io-channels = <&lradc 8>;
1338 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1339};