Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | /include/ "skeleton.dtsi" |
| 14 | |
| 15 | / { |
| 16 | aliases { |
Richard Zhao | 8f9ffec | 2011-12-14 09:26:45 +0800 | [diff] [blame] | 17 | serial0 = &uart1; |
| 18 | serial1 = &uart2; |
| 19 | serial2 = &uart3; |
| 20 | serial3 = &uart4; |
| 21 | serial4 = &uart5; |
Shawn Guo | 5230f8f | 2012-08-05 14:01:28 +0800 | [diff] [blame] | 22 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; |
| 24 | gpio2 = &gpio3; |
| 25 | gpio3 = &gpio4; |
| 26 | gpio4 = &gpio5; |
| 27 | gpio5 = &gpio6; |
| 28 | gpio6 = &gpio7; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 29 | }; |
| 30 | |
| 31 | tzic: tz-interrupt-controller@0fffc000 { |
| 32 | compatible = "fsl,imx53-tzic", "fsl,tzic"; |
| 33 | interrupt-controller; |
| 34 | #interrupt-cells = <1>; |
| 35 | reg = <0x0fffc000 0x4000>; |
| 36 | }; |
| 37 | |
| 38 | clocks { |
| 39 | #address-cells = <1>; |
| 40 | #size-cells = <0>; |
| 41 | |
| 42 | ckil { |
| 43 | compatible = "fsl,imx-ckil", "fixed-clock"; |
| 44 | clock-frequency = <32768>; |
| 45 | }; |
| 46 | |
| 47 | ckih1 { |
| 48 | compatible = "fsl,imx-ckih1", "fixed-clock"; |
| 49 | clock-frequency = <22579200>; |
| 50 | }; |
| 51 | |
| 52 | ckih2 { |
| 53 | compatible = "fsl,imx-ckih2", "fixed-clock"; |
| 54 | clock-frequency = <0>; |
| 55 | }; |
| 56 | |
| 57 | osc { |
| 58 | compatible = "fsl,imx-osc", "fixed-clock"; |
| 59 | clock-frequency = <24000000>; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | soc { |
| 64 | #address-cells = <1>; |
| 65 | #size-cells = <1>; |
| 66 | compatible = "simple-bus"; |
| 67 | interrupt-parent = <&tzic>; |
| 68 | ranges; |
| 69 | |
| 70 | aips@50000000 { /* AIPS1 */ |
| 71 | compatible = "fsl,aips-bus", "simple-bus"; |
| 72 | #address-cells = <1>; |
| 73 | #size-cells = <1>; |
| 74 | reg = <0x50000000 0x10000000>; |
| 75 | ranges; |
| 76 | |
| 77 | spba@50000000 { |
| 78 | compatible = "fsl,spba-bus", "simple-bus"; |
| 79 | #address-cells = <1>; |
| 80 | #size-cells = <1>; |
| 81 | reg = <0x50000000 0x40000>; |
| 82 | ranges; |
| 83 | |
| 84 | esdhc@50004000 { /* ESDHC1 */ |
| 85 | compatible = "fsl,imx53-esdhc"; |
| 86 | reg = <0x50004000 0x4000>; |
| 87 | interrupts = <1>; |
| 88 | status = "disabled"; |
| 89 | }; |
| 90 | |
| 91 | esdhc@50008000 { /* ESDHC2 */ |
| 92 | compatible = "fsl,imx53-esdhc"; |
| 93 | reg = <0x50008000 0x4000>; |
| 94 | interrupts = <2>; |
| 95 | status = "disabled"; |
| 96 | }; |
| 97 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 98 | uart3: serial@5000c000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 99 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 100 | reg = <0x5000c000 0x4000>; |
| 101 | interrupts = <33>; |
| 102 | status = "disabled"; |
| 103 | }; |
| 104 | |
| 105 | ecspi@50010000 { /* ECSPI1 */ |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <0>; |
| 108 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; |
| 109 | reg = <0x50010000 0x4000>; |
| 110 | interrupts = <36>; |
| 111 | status = "disabled"; |
| 112 | }; |
| 113 | |
Shawn Guo | ffc505c | 2012-05-11 13:12:01 +0800 | [diff] [blame] | 114 | ssi2: ssi@50014000 { |
| 115 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; |
| 116 | reg = <0x50014000 0x4000>; |
| 117 | interrupts = <30>; |
| 118 | fsl,fifo-depth = <15>; |
| 119 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ |
| 120 | status = "disabled"; |
| 121 | }; |
| 122 | |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 123 | esdhc@50020000 { /* ESDHC3 */ |
| 124 | compatible = "fsl,imx53-esdhc"; |
| 125 | reg = <0x50020000 0x4000>; |
| 126 | interrupts = <3>; |
| 127 | status = "disabled"; |
| 128 | }; |
| 129 | |
| 130 | esdhc@50024000 { /* ESDHC4 */ |
| 131 | compatible = "fsl,imx53-esdhc"; |
| 132 | reg = <0x50024000 0x4000>; |
| 133 | interrupts = <4>; |
| 134 | status = "disabled"; |
| 135 | }; |
| 136 | }; |
| 137 | |
Michael Grzeschik | 212d0b8 | 2012-08-23 12:35:57 +0200 | [diff] [blame] | 138 | usb@53f80000 { |
| 139 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 140 | reg = <0x53f80000 0x0200>; |
| 141 | interrupts = <18>; |
| 142 | status = "disabled"; |
| 143 | }; |
| 144 | |
| 145 | usb@53f80200 { |
| 146 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 147 | reg = <0x53f80200 0x0200>; |
| 148 | interrupts = <14>; |
| 149 | status = "disabled"; |
| 150 | }; |
| 151 | |
| 152 | usb@53f80400 { |
| 153 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 154 | reg = <0x53f80400 0x0200>; |
| 155 | interrupts = <16>; |
| 156 | status = "disabled"; |
| 157 | }; |
| 158 | |
| 159 | usb@53f80600 { |
| 160 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 161 | reg = <0x53f80600 0x0200>; |
| 162 | interrupts = <17>; |
| 163 | status = "disabled"; |
| 164 | }; |
| 165 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 166 | gpio1: gpio@53f84000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 167 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 168 | reg = <0x53f84000 0x4000>; |
| 169 | interrupts = <50 51>; |
| 170 | gpio-controller; |
| 171 | #gpio-cells = <2>; |
| 172 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 173 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 174 | }; |
| 175 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 176 | gpio2: gpio@53f88000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 177 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 178 | reg = <0x53f88000 0x4000>; |
| 179 | interrupts = <52 53>; |
| 180 | gpio-controller; |
| 181 | #gpio-cells = <2>; |
| 182 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 183 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 184 | }; |
| 185 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 186 | gpio3: gpio@53f8c000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 187 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 188 | reg = <0x53f8c000 0x4000>; |
| 189 | interrupts = <54 55>; |
| 190 | gpio-controller; |
| 191 | #gpio-cells = <2>; |
| 192 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 193 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 194 | }; |
| 195 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 196 | gpio4: gpio@53f90000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 197 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 198 | reg = <0x53f90000 0x4000>; |
| 199 | interrupts = <56 57>; |
| 200 | gpio-controller; |
| 201 | #gpio-cells = <2>; |
| 202 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 203 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 204 | }; |
| 205 | |
| 206 | wdog@53f98000 { /* WDOG1 */ |
| 207 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 208 | reg = <0x53f98000 0x4000>; |
| 209 | interrupts = <58>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 210 | }; |
| 211 | |
| 212 | wdog@53f9c000 { /* WDOG2 */ |
| 213 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 214 | reg = <0x53f9c000 0x4000>; |
| 215 | interrupts = <59>; |
| 216 | status = "disabled"; |
| 217 | }; |
| 218 | |
Shawn Guo | 5be03a7 | 2012-08-12 20:02:10 +0800 | [diff] [blame] | 219 | iomuxc@53fa8000 { |
| 220 | compatible = "fsl,imx53-iomuxc"; |
| 221 | reg = <0x53fa8000 0x4000>; |
| 222 | |
| 223 | audmux { |
| 224 | pinctrl_audmux_1: audmuxgrp-1 { |
| 225 | fsl,pins = < |
| 226 | 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ |
| 227 | 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ |
| 228 | 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ |
| 229 | 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ |
| 230 | >; |
| 231 | }; |
| 232 | }; |
| 233 | |
| 234 | fec { |
| 235 | pinctrl_fec_1: fecgrp-1 { |
| 236 | fsl,pins = < |
| 237 | 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ |
| 238 | 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ |
| 239 | 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ |
| 240 | 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ |
| 241 | 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ |
| 242 | 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ |
| 243 | 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ |
| 244 | 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ |
| 245 | 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ |
| 246 | 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ |
| 247 | >; |
| 248 | }; |
| 249 | }; |
| 250 | |
| 251 | esdhc1 { |
| 252 | pinctrl_esdhc1_1: esdhc1grp-1 { |
| 253 | fsl,pins = < |
| 254 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ |
| 255 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ |
| 256 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ |
| 257 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ |
| 258 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ |
| 259 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ |
| 260 | >; |
| 261 | }; |
Shawn Guo | 4bb6143 | 2012-08-02 22:48:39 +0800 | [diff] [blame^] | 262 | |
| 263 | pinctrl_esdhc1_2: esdhc1grp-2 { |
| 264 | fsl,pins = < |
| 265 | 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ |
| 266 | 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ |
| 267 | 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ |
| 268 | 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ |
| 269 | 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ |
| 270 | 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ |
| 271 | 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ |
| 272 | 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ |
| 273 | 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ |
| 274 | 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ |
| 275 | >; |
| 276 | }; |
Shawn Guo | 5be03a7 | 2012-08-12 20:02:10 +0800 | [diff] [blame] | 277 | }; |
| 278 | |
| 279 | esdhc3 { |
| 280 | pinctrl_esdhc3_1: esdhc3grp-1 { |
| 281 | fsl,pins = < |
| 282 | 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ |
| 283 | 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ |
| 284 | 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ |
| 285 | 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ |
| 286 | 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ |
| 287 | 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ |
| 288 | 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ |
| 289 | 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ |
| 290 | 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ |
| 291 | 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ |
| 292 | >; |
| 293 | }; |
| 294 | }; |
| 295 | |
| 296 | i2c1 { |
| 297 | pinctrl_i2c1_1: i2c1grp-1 { |
| 298 | fsl,pins = < |
| 299 | 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ |
| 300 | 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ |
| 301 | >; |
| 302 | }; |
| 303 | }; |
| 304 | |
| 305 | i2c2 { |
| 306 | pinctrl_i2c2_1: i2c2grp-1 { |
| 307 | fsl,pins = < |
| 308 | 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ |
| 309 | 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ |
| 310 | >; |
| 311 | }; |
| 312 | }; |
| 313 | |
| 314 | uart1 { |
| 315 | pinctrl_uart1_1: uart1grp-1 { |
| 316 | fsl,pins = < |
| 317 | 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ |
| 318 | 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ |
| 319 | >; |
| 320 | }; |
Shawn Guo | 4bb6143 | 2012-08-02 22:48:39 +0800 | [diff] [blame^] | 321 | |
| 322 | pinctrl_uart1_2: uart1grp-2 { |
| 323 | fsl,pins = < |
| 324 | 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ |
| 325 | 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ |
| 326 | >; |
| 327 | }; |
Shawn Guo | 5be03a7 | 2012-08-12 20:02:10 +0800 | [diff] [blame] | 328 | }; |
| 329 | }; |
| 330 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 331 | uart1: serial@53fbc000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 332 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 333 | reg = <0x53fbc000 0x4000>; |
| 334 | interrupts = <31>; |
| 335 | status = "disabled"; |
| 336 | }; |
| 337 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 338 | uart2: serial@53fc0000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 339 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 340 | reg = <0x53fc0000 0x4000>; |
| 341 | interrupts = <32>; |
| 342 | status = "disabled"; |
| 343 | }; |
| 344 | |
Steffen Trumtrar | a9d1f92 | 2012-07-18 11:42:43 +0200 | [diff] [blame] | 345 | can1: can@53fc8000 { |
| 346 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; |
| 347 | reg = <0x53fc8000 0x4000>; |
| 348 | interrupts = <82>; |
| 349 | status = "disabled"; |
| 350 | }; |
| 351 | |
| 352 | can2: can@53fcc000 { |
| 353 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; |
| 354 | reg = <0x53fcc000 0x4000>; |
| 355 | interrupts = <83>; |
| 356 | status = "disabled"; |
| 357 | }; |
| 358 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 359 | gpio5: gpio@53fdc000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 360 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 361 | reg = <0x53fdc000 0x4000>; |
| 362 | interrupts = <103 104>; |
| 363 | gpio-controller; |
| 364 | #gpio-cells = <2>; |
| 365 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 366 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 367 | }; |
| 368 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 369 | gpio6: gpio@53fe0000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 370 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 371 | reg = <0x53fe0000 0x4000>; |
| 372 | interrupts = <105 106>; |
| 373 | gpio-controller; |
| 374 | #gpio-cells = <2>; |
| 375 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 376 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 377 | }; |
| 378 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 379 | gpio7: gpio@53fe4000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 380 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 381 | reg = <0x53fe4000 0x4000>; |
| 382 | interrupts = <107 108>; |
| 383 | gpio-controller; |
| 384 | #gpio-cells = <2>; |
| 385 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 386 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 387 | }; |
| 388 | |
| 389 | i2c@53fec000 { /* I2C3 */ |
| 390 | #address-cells = <1>; |
| 391 | #size-cells = <0>; |
| 392 | compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; |
| 393 | reg = <0x53fec000 0x4000>; |
| 394 | interrupts = <64>; |
| 395 | status = "disabled"; |
| 396 | }; |
| 397 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 398 | uart4: serial@53ff0000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 399 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 400 | reg = <0x53ff0000 0x4000>; |
| 401 | interrupts = <13>; |
| 402 | status = "disabled"; |
| 403 | }; |
| 404 | }; |
| 405 | |
| 406 | aips@60000000 { /* AIPS2 */ |
| 407 | compatible = "fsl,aips-bus", "simple-bus"; |
| 408 | #address-cells = <1>; |
| 409 | #size-cells = <1>; |
| 410 | reg = <0x60000000 0x10000000>; |
| 411 | ranges; |
| 412 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 413 | uart5: serial@63f90000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 414 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 415 | reg = <0x63f90000 0x4000>; |
| 416 | interrupts = <86>; |
| 417 | status = "disabled"; |
| 418 | }; |
| 419 | |
| 420 | ecspi@63fac000 { /* ECSPI2 */ |
| 421 | #address-cells = <1>; |
| 422 | #size-cells = <0>; |
| 423 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; |
| 424 | reg = <0x63fac000 0x4000>; |
| 425 | interrupts = <37>; |
| 426 | status = "disabled"; |
| 427 | }; |
| 428 | |
| 429 | sdma@63fb0000 { |
| 430 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 431 | reg = <0x63fb0000 0x4000>; |
| 432 | interrupts = <6>; |
Fabio Estevam | 7e4f036 | 2012-08-08 11:28:07 -0300 | [diff] [blame] | 433 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 434 | }; |
| 435 | |
| 436 | cspi@63fc0000 { |
| 437 | #address-cells = <1>; |
| 438 | #size-cells = <0>; |
| 439 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; |
| 440 | reg = <0x63fc0000 0x4000>; |
| 441 | interrupts = <38>; |
| 442 | status = "disabled"; |
| 443 | }; |
| 444 | |
| 445 | i2c@63fc4000 { /* I2C2 */ |
| 446 | #address-cells = <1>; |
| 447 | #size-cells = <0>; |
| 448 | compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; |
| 449 | reg = <0x63fc4000 0x4000>; |
| 450 | interrupts = <63>; |
| 451 | status = "disabled"; |
| 452 | }; |
| 453 | |
| 454 | i2c@63fc8000 { /* I2C1 */ |
| 455 | #address-cells = <1>; |
| 456 | #size-cells = <0>; |
| 457 | compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; |
| 458 | reg = <0x63fc8000 0x4000>; |
| 459 | interrupts = <62>; |
| 460 | status = "disabled"; |
| 461 | }; |
| 462 | |
Shawn Guo | ffc505c | 2012-05-11 13:12:01 +0800 | [diff] [blame] | 463 | ssi1: ssi@63fcc000 { |
| 464 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; |
| 465 | reg = <0x63fcc000 0x4000>; |
| 466 | interrupts = <29>; |
| 467 | fsl,fifo-depth = <15>; |
| 468 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ |
| 469 | status = "disabled"; |
| 470 | }; |
| 471 | |
| 472 | audmux@63fd0000 { |
| 473 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
| 474 | reg = <0x63fd0000 0x4000>; |
| 475 | status = "disabled"; |
| 476 | }; |
| 477 | |
| 478 | ssi3: ssi@63fe8000 { |
| 479 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; |
| 480 | reg = <0x63fe8000 0x4000>; |
| 481 | interrupts = <96>; |
| 482 | fsl,fifo-depth = <15>; |
| 483 | fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ |
| 484 | status = "disabled"; |
| 485 | }; |
| 486 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 487 | ethernet@63fec000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 488 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 489 | reg = <0x63fec000 0x4000>; |
| 490 | interrupts = <87>; |
| 491 | status = "disabled"; |
| 492 | }; |
| 493 | }; |
| 494 | }; |
| 495 | }; |