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gerrit-public.fairphone.software / kernel / msm-4.19 / 4c94ac29b5c1f0cef2281df97609f2cbcc09cf9c / . / arch / arm / boot / dts / am33xx.dtsi
blob: 470926946ed6e25c198e78c6afb8e560328dd47c [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame^]15 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]16
17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
23 serial5 = &uart6;
24 };
25
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a8";
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]29
30 /*
31 * To consider voltage drop between PMIC and SoC,
32 * tolerance value is reduced to 2% from 4% and
33 * voltage value is increased as a precaution.
34 */
35 operating-points = <
36 /* kHz uV */
37 720000 1285000
38 600000 1225000
39 500000 1125000
40 275000 1125000
41 >;
42 voltage-tolerance = <2>; /* 2 percentage */
43 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]44 };
45 };
46
47 /*
48 * The soc node represents the soc top level view. It is uses for IPs
49 * that are not memory mapped in the MPU view or for the MPU itself.
50 */
51 soc {
52 compatible = "ti,omap-infra";
53 mpu {
54 compatible = "ti,omap3-mpu";
55 ti,hwmods = "mpu";
56 };
57 };
58
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]59 am33xx_pinmux: pinmux@44e10800 {
60 compatible = "pinctrl-single";
61 reg = <0x44e10800 0x0238>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64 pinctrl-single,register-width = <32>;
65 pinctrl-single,function-mask = <0x7f>;
66 };
67
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]68 /*
69 * XXX: Use a flat representation of the AM33XX interconnect.
70 * The real AM33XX interconnect network is quite complex.Since
71 * that will not bring real advantage to represent that in DT
72 * for the moment, just use a fake OCP bus entry to represent
73 * the whole bus hierarchy.
74 */
75 ocp {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 ti,hwmods = "l3_main";
81
82 intc: interrupt-controller@48200000 {
83 compatible = "ti,omap2-intc";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 ti,intc-size = <128>;
87 reg = <0x48200000 0x1000>;
88 };
89
90 gpio1: gpio@44e07000 {
91 compatible = "ti,omap4-gpio";
92 ti,hwmods = "gpio1";
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]97 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]98 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]99 };
100
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]101 gpio2: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]102 compatible = "ti,omap4-gpio";
103 ti,hwmods = "gpio2";
104 gpio-controller;
105 #gpio-cells = <2>;
106 interrupt-controller;
107 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]108 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]109 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]110 };
111
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]112 gpio3: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]113 compatible = "ti,omap4-gpio";
114 ti,hwmods = "gpio3";
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]119 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]120 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]121 };
122
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]123 gpio4: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]124 compatible = "ti,omap4-gpio";
125 ti,hwmods = "gpio4";
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]130 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]131 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]132 };
133
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]134 uart1: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]135 compatible = "ti,omap3-uart";
136 ti,hwmods = "uart1";
137 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]138 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]139 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]140 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]141 };
142
143 uart2: serial@48022000 {
144 compatible = "ti,omap3-uart";
145 ti,hwmods = "uart2";
146 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]147 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]148 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]149 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]150 };
151
152 uart3: serial@48024000 {
153 compatible = "ti,omap3-uart";
154 ti,hwmods = "uart3";
155 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]156 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]157 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]158 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]159 };
160
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]161 uart4: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]162 compatible = "ti,omap3-uart";
163 ti,hwmods = "uart4";
164 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]165 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]166 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]167 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]168 };
169
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]170 uart5: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]171 compatible = "ti,omap3-uart";
172 ti,hwmods = "uart5";
173 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]174 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]175 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]176 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]177 };
178
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]179 uart6: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]180 compatible = "ti,omap3-uart";
181 ti,hwmods = "uart6";
182 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]183 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]184 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]185 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]186 };
187
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]188 i2c1: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]189 compatible = "ti,omap4-i2c";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]193 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]194 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]195 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]196 };
197
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]198 i2c2: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]199 compatible = "ti,omap4-i2c";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]203 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]204 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]205 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]206 };
207
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]208 i2c3: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]209 compatible = "ti,omap4-i2c";
210 #address-cells = <1>;
211 #size-cells = <0>;
212 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]213 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]214 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]215 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]216 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]217
218 wdt2: wdt@44e35000 {
219 compatible = "ti,omap3-wdt";
220 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]221 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]222 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]223 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]224
225 dcan0: d_can@481cc000 {
226 compatible = "bosch,d_can";
227 ti,hwmods = "d_can0";
228 reg = <0x481cc000 0x2000>;
229 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]230 status = "disabled";
231 };
232
233 dcan1: d_can@481d0000 {
234 compatible = "bosch,d_can";
235 ti,hwmods = "d_can1";
236 reg = <0x481d0000 0x2000>;
237 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]238 status = "disabled";
239 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]240 };
241};