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Shawn Guo117ccd552013-05-03 11:28:42 +08001/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6sl.dtsi"
12
13/ {
14 model = "Freescale i.MX6 SoloLite EVK Board";
15 compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
16
17 memory {
18 reg = <0x80000000 0x40000000>;
19 };
Peter Chen60222322013-09-10 10:23:16 +080020
21 regulators {
22 compatible = "simple-bus";
Shawn Guo56160e32014-02-07 23:22:50 +080023 #address-cells = <1>;
24 #size-cells = <0>;
Peter Chen60222322013-09-10 10:23:16 +080025
Shawn Guo56160e32014-02-07 23:22:50 +080026 reg_usb_otg1_vbus: regulator@0 {
Peter Chen60222322013-09-10 10:23:16 +080027 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080028 reg = <0>;
Peter Chen60222322013-09-10 10:23:16 +080029 regulator-name = "usb_otg1_vbus";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 gpio = <&gpio4 0 0>;
33 enable-active-high;
34 };
35
Shawn Guo56160e32014-02-07 23:22:50 +080036 reg_usb_otg2_vbus: regulator@1 {
Peter Chen60222322013-09-10 10:23:16 +080037 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080038 reg = <1>;
Peter Chen60222322013-09-10 10:23:16 +080039 regulator-name = "usb_otg2_vbus";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
42 gpio = <&gpio4 2 0>;
43 enable-active-high;
44 };
45 };
Shawn Guo117ccd552013-05-03 11:28:42 +080046};
47
Huang Shijied1b53972013-10-18 10:32:53 +080048&ecspi1 {
49 fsl,spi-num-chipselects = <1>;
50 cs-gpios = <&gpio4 11 0>;
51 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +080052 pinctrl-0 = <&pinctrl_ecspi1>;
Huang Shijied1b53972013-10-18 10:32:53 +080053 status = "okay";
54
55 flash: m25p80@0 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "st,m25p32";
59 spi-max-frequency = <20000000>;
60 reg = <0>;
61 };
62};
63
Shawn Guo117ccd552013-05-03 11:28:42 +080064&fec {
65 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +080066 pinctrl-0 = <&pinctrl_fec>;
Shawn Guo117ccd552013-05-03 11:28:42 +080067 phy-mode = "rmii";
68 status = "okay";
69};
70
71&iomuxc {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_hog>;
74
Shawn Guofffaa652013-11-04 10:49:04 +080075 imx6sl-evk {
Shawn Guo117ccd552013-05-03 11:28:42 +080076 pinctrl_hog: hoggrp {
77 fsl,pins = <
78 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
79 MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
80 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
81 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
82 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
Peter Chen60222322013-09-10 10:23:16 +080083 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
84 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
Shawn Guo117ccd552013-05-03 11:28:42 +080085 >;
86 };
Shawn Guofffaa652013-11-04 10:49:04 +080087
88 pinctrl_ecspi1: ecspi1grp {
89 fsl,pins = <
90 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
91 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
92 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
93 >;
94 };
95
96 pinctrl_fec: fecgrp {
97 fsl,pins = <
98 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
99 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
100 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
101 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
102 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
103 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
104 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
105 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
106 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
107 >;
108 };
109
110 pinctrl_uart1: uart1grp {
111 fsl,pins = <
112 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
113 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
114 >;
115 };
116
117 pinctrl_usbotg1: usbotg1grp {
118 fsl,pins = <
119 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
120 >;
121 };
122
123 pinctrl_usdhc1: usdhc1grp {
124 fsl,pins = <
125 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
126 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
127 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
128 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
129 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
130 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
131 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
132 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
133 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
134 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
135 >;
136 };
137
138 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
139 fsl,pins = <
140 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
141 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
142 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
143 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
144 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
145 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
146 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
147 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
148 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
149 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
150 >;
151 };
152
153 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
154 fsl,pins = <
155 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
156 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
157 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
158 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
159 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
160 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
161 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
162 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
163 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
164 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
165 >;
166 };
167
168 pinctrl_usdhc2: usdhc2grp {
169 fsl,pins = <
170 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
171 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
172 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
173 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
174 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
175 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
176 >;
177 };
178
179 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
180 fsl,pins = <
181 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
182 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
183 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
184 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
185 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
186 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
187 >;
188 };
189
190 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
191 fsl,pins = <
192 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
193 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
194 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
195 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
196 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
197 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
198 >;
199 };
200
201 pinctrl_usdhc3: usdhc3grp {
202 fsl,pins = <
203 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
204 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
205 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
206 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
207 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
208 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
209 >;
210 };
211
212 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
213 fsl,pins = <
214 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
215 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
216 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
217 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
218 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
219 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
220 >;
221 };
222
223 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
224 fsl,pins = <
225 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
226 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
227 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
228 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
229 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
230 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
231 >;
232 };
Shawn Guo117ccd552013-05-03 11:28:42 +0800233 };
234};
235
236&uart1 {
237 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800238 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800239 status = "okay";
240};
241
Peter Chen60222322013-09-10 10:23:16 +0800242&usbotg1 {
243 vbus-supply = <&reg_usb_otg1_vbus>;
244 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800245 pinctrl-0 = <&pinctrl_usbotg1>;
Peter Chen60222322013-09-10 10:23:16 +0800246 disable-over-current;
247 status = "okay";
248};
249
250&usbotg2 {
251 vbus-supply = <&reg_usb_otg2_vbus>;
252 dr_mode = "host";
253 disable-over-current;
254 status = "okay";
255};
256
Shawn Guo117ccd552013-05-03 11:28:42 +0800257&usdhc1 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800258 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800259 pinctrl-0 = <&pinctrl_usdhc1>;
260 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
261 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800262 bus-width = <8>;
263 cd-gpios = <&gpio4 7 0>;
264 wp-gpios = <&gpio4 6 0>;
265 status = "okay";
266};
267
268&usdhc2 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800269 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800270 pinctrl-0 = <&pinctrl_usdhc2>;
271 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
272 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800273 cd-gpios = <&gpio5 0 0>;
274 wp-gpios = <&gpio4 29 0>;
275 status = "okay";
276};
277
278&usdhc3 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800279 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800280 pinctrl-0 = <&pinctrl_usdhc3>;
281 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
282 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800283 cd-gpios = <&gpio3 22 0>;
284 status = "okay";
285};