blob: 07ff55a0d631ce6fbc46e65dcaa3408a5c5e0de2 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -06001/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -06003#include "tegra20.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -06004
5/ {
6 model = "NVIDIA Seaboard";
7 compatible = "nvidia,seaboard", "nvidia,tegra20";
8
Grant Likely8e267f32011-07-19 17:26:54 -06009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -060011 };
12
Stephen Warren58ecb232013-11-25 17:53:16 -070013 host1x@50000000 {
14 hdmi@54280000 {
Stephen Warrena75191e2013-01-02 14:53:20 -070015 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070021 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
Stephen Warrena75191e2013-01-02 14:53:20 -070023 };
24 };
25
Stephen Warren58ecb232013-11-25 17:53:16 -070026 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060027 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>;
29
30 state_default: pinmux {
31 ata {
32 nvidia,pins = "ata";
33 nvidia,function = "ide";
34 };
35 atb {
36 nvidia,pins = "atb", "gma", "gme";
37 nvidia,function = "sdio4";
38 };
39 atc {
40 nvidia,pins = "atc";
41 nvidia,function = "nand";
42 };
43 atd {
44 nvidia,pins = "atd", "ate", "gmb", "spia",
45 "spib", "spic";
46 nvidia,function = "gmi";
47 };
48 cdev1 {
49 nvidia,pins = "cdev1";
50 nvidia,function = "plla_out";
51 };
52 cdev2 {
53 nvidia,pins = "cdev2";
54 nvidia,function = "pllp_out4";
55 };
56 crtp {
57 nvidia,pins = "crtp", "lm1";
58 nvidia,function = "crt";
59 };
60 csus {
61 nvidia,pins = "csus";
62 nvidia,function = "vi_sensor_clk";
63 };
64 dap1 {
65 nvidia,pins = "dap1";
66 nvidia,function = "dap1";
67 };
68 dap2 {
69 nvidia,pins = "dap2";
70 nvidia,function = "dap2";
71 };
72 dap3 {
73 nvidia,pins = "dap3";
74 nvidia,function = "dap3";
75 };
76 dap4 {
77 nvidia,pins = "dap4";
78 nvidia,function = "dap4";
79 };
Stephen Warrenecc295b2012-03-15 16:27:36 -060080 dta {
81 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
82 nvidia,function = "vi";
83 };
84 dtf {
85 nvidia,pins = "dtf";
86 nvidia,function = "i2c3";
87 };
88 gmc {
89 nvidia,pins = "gmc";
90 nvidia,function = "uartd";
91 };
92 gmd {
93 nvidia,pins = "gmd";
94 nvidia,function = "sflash";
95 };
96 gpu {
97 nvidia,pins = "gpu";
98 nvidia,function = "pwm";
99 };
100 gpu7 {
101 nvidia,pins = "gpu7";
102 nvidia,function = "rtck";
103 };
104 gpv {
105 nvidia,pins = "gpv", "slxa", "slxk";
106 nvidia,function = "pcie";
107 };
108 hdint {
109 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
Stephen Warren802a8492012-04-26 11:21:54 -0600110 "lsck", "lsda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600111 nvidia,function = "hdmi";
112 };
113 i2cp {
114 nvidia,pins = "i2cp";
115 nvidia,function = "i2cp";
116 };
117 irrx {
118 nvidia,pins = "irrx", "irtx";
119 nvidia,function = "uartb";
120 };
121 kbca {
122 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
123 "kbce", "kbcf";
124 nvidia,function = "kbc";
125 };
126 lcsn {
127 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
128 "lsdi", "lvp0";
129 nvidia,function = "rsvd4";
130 };
131 ld0 {
132 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
133 "ld5", "ld6", "ld7", "ld8", "ld9",
134 "ld10", "ld11", "ld12", "ld13", "ld14",
135 "ld15", "ld16", "ld17", "ldi", "lhp0",
136 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
137 "lspi", "lvp1", "lvs";
138 nvidia,function = "displaya";
139 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600140 owc {
141 nvidia,pins = "owc", "spdi", "spdo", "uac";
142 nvidia,function = "rsvd2";
143 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600144 pmc {
145 nvidia,pins = "pmc";
146 nvidia,function = "pwr_on";
147 };
148 rm {
149 nvidia,pins = "rm";
150 nvidia,function = "i2c1";
151 };
152 sdb {
153 nvidia,pins = "sdb", "sdc", "sdd";
154 nvidia,function = "sdio3";
155 };
156 sdio1 {
157 nvidia,pins = "sdio1";
158 nvidia,function = "sdio1";
159 };
160 slxc {
161 nvidia,pins = "slxc", "slxd";
162 nvidia,function = "spdif";
163 };
164 spid {
165 nvidia,pins = "spid", "spie", "spif";
166 nvidia,function = "spi1";
167 };
168 spig {
169 nvidia,pins = "spig", "spih";
170 nvidia,function = "spi2_alt";
171 };
172 uaa {
173 nvidia,pins = "uaa", "uab", "uda";
174 nvidia,function = "ulpi";
175 };
176 uad {
177 nvidia,pins = "uad";
178 nvidia,function = "irda";
179 };
180 uca {
181 nvidia,pins = "uca", "ucb";
182 nvidia,function = "uartc";
183 };
184 conf_ata {
185 nvidia,pins = "ata", "atb", "atc", "atd",
186 "cdev1", "cdev2", "dap1", "dap2",
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600187 "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
Stephen Warrenecc295b2012-03-15 16:27:36 -0600188 "gme", "gpu", "gpu7", "i2cp", "irrx",
189 "irtx", "pta", "rm", "sdc", "sdd",
190 "slxd", "slxk", "spdi", "spdo", "uac",
191 "uad", "uca", "ucb", "uda";
192 nvidia,pull = <0>;
193 nvidia,tristate = <0>;
194 };
195 conf_ate {
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600196 nvidia,pins = "ate", "csus", "dap3",
Stephen Warrenecc295b2012-03-15 16:27:36 -0600197 "gpv", "owc", "slxc", "spib", "spid",
198 "spie";
199 nvidia,pull = <0>;
200 nvidia,tristate = <1>;
201 };
202 conf_ck32 {
203 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
204 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
205 nvidia,pull = <0>;
206 };
207 conf_crtp {
208 nvidia,pins = "crtp", "gmb", "slxa", "spia",
209 "spig", "spih";
210 nvidia,pull = <2>;
211 nvidia,tristate = <1>;
212 };
213 conf_dta {
214 nvidia,pins = "dta", "dtb", "dtc", "dtd";
215 nvidia,pull = <1>;
216 nvidia,tristate = <0>;
217 };
218 conf_dte {
219 nvidia,pins = "dte", "spif";
220 nvidia,pull = <1>;
221 nvidia,tristate = <1>;
222 };
223 conf_hdint {
224 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
225 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
226 "lvp0";
227 nvidia,tristate = <1>;
228 };
229 conf_kbca {
230 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
231 "kbce", "kbcf", "sdio1", "spic", "uaa",
232 "uab";
233 nvidia,pull = <2>;
234 nvidia,tristate = <0>;
235 };
236 conf_lc {
237 nvidia,pins = "lc", "ls";
238 nvidia,pull = <2>;
239 };
240 conf_ld0 {
241 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
242 "ld5", "ld6", "ld7", "ld8", "ld9",
243 "ld10", "ld11", "ld12", "ld13", "ld14",
244 "ld15", "ld16", "ld17", "ldi", "lhp0",
245 "lhp1", "lhp2", "lhs", "lm0", "lpp",
246 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
247 "lvs", "pmc", "sdb";
248 nvidia,tristate = <0>;
249 };
250 conf_ld17_0 {
251 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
252 "ld23_22";
253 nvidia,pull = <1>;
254 };
255 drive_sdio1 {
256 nvidia,pins = "drive_sdio1";
257 nvidia,high-speed-mode = <0>;
258 nvidia,schmitt = <0>;
259 nvidia,low-power-mode = <3>;
260 nvidia,pull-down-strength = <31>;
261 nvidia,pull-up-strength = <31>;
262 nvidia,slew-rate-rising = <3>;
263 nvidia,slew-rate-falling = <3>;
264 };
265 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600266
267 state_i2cmux_ddc: pinmux_i2cmux_ddc {
268 ddc {
269 nvidia,pins = "ddc";
270 nvidia,function = "i2c2";
271 };
272 pta {
273 nvidia,pins = "pta";
274 nvidia,function = "rsvd4";
275 };
276 };
277
278 state_i2cmux_pta: pinmux_i2cmux_pta {
279 ddc {
280 nvidia,pins = "ddc";
281 nvidia,function = "rsvd4";
282 };
283 pta {
284 nvidia,pins = "pta";
285 nvidia,function = "i2c2";
286 };
287 };
288
289 state_i2cmux_idle: pinmux_i2cmux_idle {
290 ddc {
291 nvidia,pins = "ddc";
292 nvidia,function = "rsvd4";
293 };
294 pta {
295 nvidia,pins = "pta";
296 nvidia,function = "rsvd4";
297 };
298 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600299 };
300
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600301 i2s@70002800 {
302 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600303 };
304
305 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600306 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600307 };
308
Stephen Warren88950f3b2011-11-21 14:44:09 -0700309 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600310 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700311 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700312
313 wm8903: wm8903@1a {
314 compatible = "wlf,wm8903";
315 reg = <0x1a>;
316 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700317 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren797acf72012-01-11 16:09:57 -0700318
319 gpio-controller;
320 #gpio-cells = <2>;
321
322 micdet-cfg = <0>;
323 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600324 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700325 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530326
327 /* ALS and proximity sensor */
328 isl29018@44 {
329 compatible = "isil,isl29018";
330 reg = <0x44>;
331 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700332 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530333 };
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000334
335 gyrometer@68 {
336 compatible = "invn,mpu3050";
337 reg = <0x68>;
338 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700339 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000340 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700341 };
342
343 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600344 status = "okay";
Stephen Warren22bd1f72012-04-26 11:19:03 -0600345 clock-frequency = <100000>;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700346 };
347
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600348 i2cmux {
349 compatible = "i2c-mux-pinctrl";
350 #address-cells = <1>;
351 #size-cells = <0>;
352
353 i2c-parent = <&{/i2c@7000c400}>;
354
355 pinctrl-names = "ddc", "pta", "idle";
356 pinctrl-0 = <&state_i2cmux_ddc>;
357 pinctrl-1 = <&state_i2cmux_pta>;
358 pinctrl-2 = <&state_i2cmux_idle>;
359
Stephen Warrena75191e2013-01-02 14:53:20 -0700360 hdmi_ddc: i2c@0 {
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600361 reg = <0>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 };
365
366 i2c@1 {
367 reg = <1>;
368 #address-cells = <1>;
369 #size-cells = <0>;
Stephen Warren0879c5f2012-04-25 16:57:28 -0600370
371 smart-battery@b {
372 compatible = "ti,bq20z75", "smart-battery-1.1";
373 reg = <0xb>;
374 ti,i2c-retry-count = <2>;
375 ti,poll-retry-count = <10>;
376 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600377 };
378 };
379
Stephen Warren88950f3b2011-11-21 14:44:09 -0700380 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600381 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700382 clock-frequency = <400000>;
383 };
384
385 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600386 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700387 clock-frequency = <400000>;
Stephen Warren401c9a52011-12-17 23:29:32 -0700388
Stephen Warren57899052013-11-26 14:43:45 -0700389 magnetometer@c {
390 compatible = "ak,ak8975";
391 reg = <0xc>;
392 interrupt-parent = <&gpio>;
393 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
394 };
395
Stephen Warren6529e632012-06-20 15:58:34 -0600396 pmic: tps6586x@34 {
397 compatible = "ti,tps6586x";
398 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700399 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600400
Stephen Warren44b12ef2012-09-11 11:42:26 -0600401 ti,system-power-controller;
402
Stephen Warren6529e632012-06-20 15:58:34 -0600403 #gpio-cells = <2>;
404 gpio-controller;
405
406 sys-supply = <&vdd_5v0_reg>;
407 vin-sm0-supply = <&sys_reg>;
408 vin-sm1-supply = <&sys_reg>;
409 vin-sm2-supply = <&sys_reg>;
410 vinldo01-supply = <&sm2_reg>;
411 vinldo23-supply = <&sm2_reg>;
412 vinldo4-supply = <&sm2_reg>;
413 vinldo678-supply = <&sm2_reg>;
414 vinldo9-supply = <&sm2_reg>;
415
416 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600417 sys_reg: sys {
Stephen Warren6529e632012-06-20 15:58:34 -0600418 regulator-name = "vdd_sys";
419 regulator-always-on;
420 };
421
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600422 sm0 {
Stephen Warren6529e632012-06-20 15:58:34 -0600423 regulator-name = "vdd_sm0,vdd_core";
424 regulator-min-microvolt = <1300000>;
425 regulator-max-microvolt = <1300000>;
426 regulator-always-on;
427 };
428
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600429 sm1 {
Stephen Warren6529e632012-06-20 15:58:34 -0600430 regulator-name = "vdd_sm1,vdd_cpu";
431 regulator-min-microvolt = <1125000>;
432 regulator-max-microvolt = <1125000>;
433 regulator-always-on;
434 };
435
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600436 sm2_reg: sm2 {
Stephen Warren6529e632012-06-20 15:58:34 -0600437 regulator-name = "vdd_sm2,vin_ldo*";
438 regulator-min-microvolt = <3700000>;
439 regulator-max-microvolt = <3700000>;
440 regulator-always-on;
441 };
442
443 /* LDO0 is not connected to anything */
444
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600445 ldo1 {
Stephen Warren6529e632012-06-20 15:58:34 -0600446 regulator-name = "vdd_ldo1,avdd_pll*";
447 regulator-min-microvolt = <1100000>;
448 regulator-max-microvolt = <1100000>;
449 regulator-always-on;
450 };
451
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600452 ldo2 {
Stephen Warren6529e632012-06-20 15:58:34 -0600453 regulator-name = "vdd_ldo2,vdd_rtc";
454 regulator-min-microvolt = <1200000>;
455 regulator-max-microvolt = <1200000>;
456 };
457
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600458 ldo3 {
Stephen Warren6529e632012-06-20 15:58:34 -0600459 regulator-name = "vdd_ldo3,avdd_usb*";
460 regulator-min-microvolt = <3300000>;
461 regulator-max-microvolt = <3300000>;
462 regulator-always-on;
463 };
464
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600465 ldo4 {
Stephen Warren6529e632012-06-20 15:58:34 -0600466 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
467 regulator-min-microvolt = <1800000>;
468 regulator-max-microvolt = <1800000>;
469 regulator-always-on;
470 };
471
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600472 ldo5 {
Stephen Warren6529e632012-06-20 15:58:34 -0600473 regulator-name = "vdd_ldo5,vcore_mmc";
474 regulator-min-microvolt = <2850000>;
475 regulator-max-microvolt = <2850000>;
476 regulator-always-on;
477 };
478
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600479 ldo6 {
Stephen Warren6529e632012-06-20 15:58:34 -0600480 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
481 regulator-min-microvolt = <1800000>;
482 regulator-max-microvolt = <1800000>;
483 };
484
Stephen Warrena75191e2013-01-02 14:53:20 -0700485 hdmi_vdd_reg: ldo7 {
Stephen Warren6529e632012-06-20 15:58:34 -0600486 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
487 regulator-min-microvolt = <3300000>;
488 regulator-max-microvolt = <3300000>;
489 };
490
Stephen Warrena75191e2013-01-02 14:53:20 -0700491 hdmi_pll_reg: ldo8 {
Stephen Warren6529e632012-06-20 15:58:34 -0600492 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
493 regulator-min-microvolt = <1800000>;
494 regulator-max-microvolt = <1800000>;
495 };
496
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600497 ldo9 {
Stephen Warren6529e632012-06-20 15:58:34 -0600498 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
499 regulator-min-microvolt = <2850000>;
500 regulator-max-microvolt = <2850000>;
501 regulator-always-on;
502 };
503
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600504 ldo_rtc {
Stephen Warren6529e632012-06-20 15:58:34 -0600505 regulator-name = "vdd_rtc_out,vdd_cell";
506 regulator-min-microvolt = <3300000>;
507 regulator-max-microvolt = <3300000>;
508 regulator-always-on;
509 };
510 };
511 };
512
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000513 temperature-sensor@4c {
Stephen Warren98462102012-11-19 15:34:44 -0700514 compatible = "onnn,nct1008";
Stephen Warren401c9a52011-12-17 23:29:32 -0700515 reg = <0x4c>;
516 };
Stephen Warrenc04abb32012-05-11 17:03:26 -0600517 };
518
Stephen Warren58ecb232013-11-25 17:53:16 -0700519 kbc@7000e200 {
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530520 status = "okay";
521 nvidia,debounce-delay-ms = <32>;
522 nvidia,repeat-delay-ms = <160>;
523 nvidia,ghost-filter;
524 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
525 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
526 linux,keymap = <0x00020011 /* KEY_W */
527 0x0003001F /* KEY_S */
528 0x0004001E /* KEY_A */
529 0x0005002C /* KEY_Z */
530 0x000701d0 /* KEY_FN */
531
532 0x0107007D /* KEY_LEFTMETA */
533 0x02060064 /* KEY_RIGHTALT */
534 0x02070038 /* KEY_LEFTALT */
535
536 0x03000006 /* KEY_5 */
537 0x03010005 /* KEY_4 */
538 0x03020013 /* KEY_R */
539 0x03030012 /* KEY_E */
540 0x03040021 /* KEY_F */
541 0x03050020 /* KEY_D */
542 0x0306002D /* KEY_X */
543
544 0x04000008 /* KEY_7 */
545 0x04010007 /* KEY_6 */
546 0x04020014 /* KEY_T */
547 0x04030023 /* KEY_H */
548 0x04040022 /* KEY_G */
549 0x0405002F /* KEY_V */
550 0x0406002E /* KEY_C */
551 0x04070039 /* KEY_SPACE */
552
553 0x0500000A /* KEY_9 */
554 0x05010009 /* KEY_8 */
555 0x05020016 /* KEY_U */
556 0x05030015 /* KEY_Y */
557 0x05040024 /* KEY_J */
558 0x05050031 /* KEY_N */
559 0x05060030 /* KEY_B */
560 0x0507002B /* KEY_BACKSLASH */
561
562 0x0600000C /* KEY_MINUS */
563 0x0601000B /* KEY_0 */
564 0x06020018 /* KEY_O */
565 0x06030017 /* KEY_I */
566 0x06040026 /* KEY_L */
567 0x06050025 /* KEY_K */
568 0x06060033 /* KEY_COMMA */
569 0x06070032 /* KEY_M */
570
571 0x0701000D /* KEY_EQUAL */
572 0x0702001B /* KEY_RIGHTBRACE */
573 0x0703001C /* KEY_ENTER */
574 0x0707008B /* KEY_MENU */
575
576 0x08040036 /* KEY_RIGHTSHIFT */
577 0x0805002A /* KEY_LEFTSHIFT */
578
579 0x09050061 /* KEY_RIGHTCTRL */
580 0x0907001D /* KEY_LEFTCTRL */
581
582 0x0B00001A /* KEY_LEFTBRACE */
583 0x0B010019 /* KEY_P */
584 0x0B020028 /* KEY_APOSTROPHE */
585 0x0B030027 /* KEY_SEMICOLON */
586 0x0B040035 /* KEY_SLASH */
587 0x0B050034 /* KEY_DOT */
588
589 0x0C000044 /* KEY_F10 */
590 0x0C010043 /* KEY_F9 */
591 0x0C02000E /* KEY_BACKSPACE */
592 0x0C030004 /* KEY_3 */
593 0x0C040003 /* KEY_2 */
594 0x0C050067 /* KEY_UP */
595 0x0C0600D2 /* KEY_PRINT */
596 0x0C070077 /* KEY_PAUSE */
597
598 0x0D00006E /* KEY_INSERT */
599 0x0D01006F /* KEY_DELETE */
600 0x0D030068 /* KEY_PAGEUP */
601 0x0D04006D /* KEY_PAGEDOWN */
602 0x0D05006A /* KEY_RIGHT */
603 0x0D06006C /* KEY_DOWN */
604 0x0D070069 /* KEY_LEFT */
605
606 0x0E000057 /* KEY_F11 */
607 0x0E010058 /* KEY_F12 */
608 0x0E020042 /* KEY_F8 */
609 0x0E030010 /* KEY_Q */
610 0x0E04003E /* KEY_F4 */
611 0x0E05003D /* KEY_F3 */
612 0x0E060002 /* KEY_1 */
613 0x0E070041 /* KEY_F7 */
614
615 0x0F000001 /* KEY_ESC */
616 0x0F010029 /* KEY_GRAVE */
617 0x0F02003F /* KEY_F5 */
618 0x0F03000F /* KEY_TAB */
619 0x0F04003B /* KEY_F1 */
620 0x0F05003C /* KEY_F2 */
621 0x0F06003A /* KEY_CAPSLOCK */
622 0x0F070040 /* KEY_F6 */
623
624 /* Software Handled Function Keys */
625 0x14000047 /* KEY_KP7 */
626
627 0x15000049 /* KEY_KP9 */
628 0x15010048 /* KEY_KP8 */
629 0x1502004B /* KEY_KP4 */
630 0x1504004F /* KEY_KP1 */
631
632 0x1601004E /* KEY_KPSLASH */
633 0x1602004D /* KEY_KP6 */
634 0x1603004C /* KEY_KP5 */
635 0x16040051 /* KEY_KP3 */
636 0x16050050 /* KEY_KP2 */
637 0x16070052 /* KEY_KP0 */
638
639 0x1B010037 /* KEY_KPASTERISK */
640 0x1B03004A /* KEY_KPMINUS */
641 0x1B04004E /* KEY_KPPLUS */
642 0x1B050053 /* KEY_KPDOT */
643
644 0x1C050073 /* KEY_VOLUMEUP */
645
646 0x1D030066 /* KEY_HOME */
647 0x1D04006B /* KEY_END */
648 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
649 0x1D060072 /* KEY_VOLUMEDOWN */
650 0x1D0700E1 /* KEY_BRIGHTNESSUP */
651
652 0x1E000045 /* KEY_NUMLOCK */
653 0x1E010046 /* KEY_SCROLLLOCK */
654 0x1E020071 /* KEY_MUTE */
655
656 0x1F04008A>; /* KEY_HELP */
657 };
Stephen Warren57899052013-11-26 14:43:45 -0700658
659 pmc@7000e400 {
660 nvidia,invert-interrupt;
661 nvidia,suspend-mode = <1>;
662 nvidia,cpu-pwr-good-time = <5000>;
663 nvidia,cpu-pwr-off-time = <5000>;
664 nvidia,core-pwr-good-time = <3845 3845>;
665 nvidia,core-pwr-off-time = <3875>;
666 nvidia,sys-clock-req-active-high;
667 };
668
669 memory-controller@7000f400 {
670 emc-table@190000 {
671 reg = <190000>;
672 compatible = "nvidia,tegra20-emc-table";
673 clock-frequency = <190000>;
674 nvidia,emc-registers = <0x0000000c 0x00000026
675 0x00000009 0x00000003 0x00000004 0x00000004
676 0x00000002 0x0000000c 0x00000003 0x00000003
677 0x00000002 0x00000001 0x00000004 0x00000005
678 0x00000004 0x00000009 0x0000000d 0x0000059f
679 0x00000000 0x00000003 0x00000003 0x00000003
680 0x00000003 0x00000001 0x0000000b 0x000000c8
681 0x00000003 0x00000007 0x00000004 0x0000000f
682 0x00000002 0x00000000 0x00000000 0x00000002
683 0x00000000 0x00000000 0x00000083 0xa06204ae
684 0x007dc010 0x00000000 0x00000000 0x00000000
685 0x00000000 0x00000000 0x00000000 0x00000000>;
686 };
687
688 emc-table@380000 {
689 reg = <380000>;
690 compatible = "nvidia,tegra20-emc-table";
691 clock-frequency = <380000>;
692 nvidia,emc-registers = <0x00000017 0x0000004b
693 0x00000012 0x00000006 0x00000004 0x00000005
694 0x00000003 0x0000000c 0x00000006 0x00000006
695 0x00000003 0x00000001 0x00000004 0x00000005
696 0x00000004 0x00000009 0x0000000d 0x00000b5f
697 0x00000000 0x00000003 0x00000003 0x00000006
698 0x00000006 0x00000001 0x00000011 0x000000c8
699 0x00000003 0x0000000e 0x00000007 0x0000000f
700 0x00000002 0x00000000 0x00000000 0x00000002
701 0x00000000 0x00000000 0x00000083 0xe044048b
702 0x007d8010 0x00000000 0x00000000 0x00000000
703 0x00000000 0x00000000 0x00000000 0x00000000>;
704 };
705 };
706
707 usb@c5000000 {
708 status = "okay";
709 dr_mode = "otg";
710 };
711
712 usb-phy@c5000000 {
713 status = "okay";
714 vbus-supply = <&vbus_reg>;
715 dr_mode = "otg";
716 };
717
718 usb@c5004000 {
719 status = "okay";
720 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
721 GPIO_ACTIVE_LOW>;
722 };
723
724 usb-phy@c5004000 {
725 status = "okay";
726 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
727 GPIO_ACTIVE_LOW>;
728 };
729
730 usb@c5008000 {
731 status = "okay";
732 };
733
734 usb-phy@c5008000 {
735 status = "okay";
736 };
737
738 sdhci@c8000000 {
739 status = "okay";
740 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
741 bus-width = <4>;
742 keep-power-in-suspend;
743 };
744
745 sdhci@c8000400 {
746 status = "okay";
747 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
748 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
749 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
750 bus-width = <4>;
751 };
752
753 sdhci@c8000600 {
754 status = "okay";
755 bus-width = <8>;
756 non-removable;
757 };
758
759 clocks {
760 compatible = "simple-bus";
761 #address-cells = <1>;
762 #size-cells = <0>;
763
764 clk32k_in: clock@0 {
765 compatible = "fixed-clock";
766 reg=<0>;
767 #clock-cells = <0>;
768 clock-frequency = <32768>;
769 };
770 };
771
772 gpio-keys {
773 compatible = "gpio-keys";
774
775 power {
776 label = "Power";
777 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
778 linux,code = <116>; /* KEY_POWER */
779 gpio-key,wakeup;
780 };
781
782 lid {
783 label = "Lid";
784 gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
785 linux,input-type = <5>; /* EV_SW */
786 linux,code = <0>; /* SW_LID */
787 debounce-interval = <1>;
788 gpio-key,wakeup;
789 };
790 };
791
Stephen Warren6529e632012-06-20 15:58:34 -0600792 regulators {
793 compatible = "simple-bus";
794 #address-cells = <1>;
795 #size-cells = <0>;
796
797 vdd_5v0_reg: regulator@0 {
798 compatible = "regulator-fixed";
799 reg = <0>;
800 regulator-name = "vdd_5v0";
801 regulator-min-microvolt = <5000000>;
802 regulator-max-microvolt = <5000000>;
803 regulator-always-on;
804 };
805
806 regulator@1 {
807 compatible = "regulator-fixed";
808 reg = <1>;
809 regulator-name = "vdd_1v5";
810 regulator-min-microvolt = <1500000>;
811 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700812 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600813 };
814
815 regulator@2 {
816 compatible = "regulator-fixed";
817 reg = <2>;
818 regulator-name = "vdd_1v2";
819 regulator-min-microvolt = <1200000>;
820 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700821 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600822 enable-active-high;
823 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530824
825 vbus_reg: regulator@3 {
826 compatible = "regulator-fixed";
827 reg = <3>;
828 regulator-name = "vdd_vbus_wup1";
829 regulator-min-microvolt = <5000000>;
830 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600831 enable-active-high;
Stephen Warren23f95ef2013-08-01 12:26:01 -0600832 gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
Stephen Warren30ca2222013-08-20 14:00:13 -0600833 regulator-always-on;
834 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530835 };
Stephen Warren6529e632012-06-20 15:58:34 -0600836 };
837
Stephen Warrenc04abb32012-05-11 17:03:26 -0600838 sound {
839 compatible = "nvidia,tegra-audio-wm8903-seaboard",
840 "nvidia,tegra-audio-wm8903";
841 nvidia,model = "NVIDIA Tegra Seaboard";
842
843 nvidia,audio-routing =
844 "Headphone Jack", "HPOUTR",
845 "Headphone Jack", "HPOUTL",
846 "Int Spk", "ROP",
847 "Int Spk", "RON",
848 "Int Spk", "LOP",
849 "Int Spk", "LON",
850 "Mic Jack", "MICBIAS",
851 "IN1R", "Mic Jack";
852
853 nvidia,i2s-controller = <&tegra_i2s1>;
854 nvidia,audio-codec = <&wm8903>;
855
Stephen Warren3325f1b2013-02-12 17:25:15 -0700856 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
857 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600858
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300859 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
860 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
861 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600862 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600863 };
Grant Likely8e267f32011-07-19 17:26:54 -0600864};