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gerrit-public.fairphone.software / kernel / msm-4.19 / 5791ce18aa660df7d1dafebf6bd89d5aa05bd742 / . / drivers / net / wireless / b43 / phy_lp.c
blob: 37ba1777667fe7bba77f336e5404119c2128a4ce [file] [log] [blame]
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11g LP-PHY driver
5
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include "b43.h"
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]26#include "main.h"
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]27#include "phy_lp.h"
28#include "phy_common.h"
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]29#include "tables_lpphy.h"
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]30
31
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]32static inline u16 channel2freq_lp(u8 channel)
33{
34 if (channel < 14)
35 return (2407 + 5 * channel);
36 else if (channel == 14)
37 return 2484;
38 else if (channel < 184)
39 return (5000 + 5 * channel);
40 else
41 return (4000 + 5 * channel);
42}
43
44static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
45{
46 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
47 return 1;
48 return 36;
49}
50
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]51static int b43_lpphy_op_allocate(struct b43_wldev *dev)
52{
53 struct b43_phy_lp *lpphy;
54
55 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
56 if (!lpphy)
57 return -ENOMEM;
58 dev->phy.lp = lpphy;
59
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]60 return 0;
61}
62
Michael Bueschfb111372008-09-02 13:00:34 +0200[diff] [blame]63static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
64{
65 struct b43_phy *phy = &dev->phy;
66 struct b43_phy_lp *lpphy = phy->lp;
67
68 memset(lpphy, 0, sizeof(*lpphy));
69
70 //TODO
71}
72
73static void b43_lpphy_op_free(struct b43_wldev *dev)
74{
75 struct b43_phy_lp *lpphy = dev->phy.lp;
76
77 kfree(lpphy);
78 dev->phy.lp = NULL;
79}
80
Gábor Stefanik84ec1672009-08-11 21:47:00 +0200[diff] [blame]81static void lpphy_read_band_sprom(struct b43_wldev *dev)
82{
83 struct b43_phy_lp *lpphy = dev->phy.lp;
84 struct ssb_bus *bus = dev->dev->bus;
85 u16 cckpo, maxpwr;
86 u32 ofdmpo;
87 int i;
88
89 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
90 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
91 lpphy->bx_arch = bus->sprom.bxa2g;
92 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
93 lpphy->rssi_vf = bus->sprom.rssismf2g;
94 lpphy->rssi_vc = bus->sprom.rssismc2g;
95 lpphy->rssi_gs = bus->sprom.rssisav2g;
96 lpphy->txpa[0] = bus->sprom.pa0b0;
97 lpphy->txpa[1] = bus->sprom.pa0b1;
98 lpphy->txpa[2] = bus->sprom.pa0b2;
99 maxpwr = bus->sprom.maxpwr_bg;
100 lpphy->max_tx_pwr_med_band = maxpwr;
101 cckpo = bus->sprom.cck2gpo;
102 ofdmpo = bus->sprom.ofdm2gpo;
103 if (cckpo) {
104 for (i = 0; i < 4; i++) {
105 lpphy->tx_max_rate[i] =
106 maxpwr - (ofdmpo & 0xF) * 2;
107 ofdmpo >>= 4;
108 }
109 ofdmpo = bus->sprom.ofdm2gpo;
110 for (i = 4; i < 15; i++) {
111 lpphy->tx_max_rate[i] =
112 maxpwr - (ofdmpo & 0xF) * 2;
113 ofdmpo >>= 4;
114 }
115 } else {
116 ofdmpo &= 0xFF;
117 for (i = 0; i < 4; i++)
118 lpphy->tx_max_rate[i] = maxpwr;
119 for (i = 4; i < 15; i++)
120 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
121 }
122 } else { /* 5GHz */
123 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
124 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
125 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
126 lpphy->bx_arch = bus->sprom.bxa5g;
127 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
128 lpphy->rssi_vf = bus->sprom.rssismf5g;
129 lpphy->rssi_vc = bus->sprom.rssismc5g;
130 lpphy->rssi_gs = bus->sprom.rssisav5g;
131 lpphy->txpa[0] = bus->sprom.pa1b0;
132 lpphy->txpa[1] = bus->sprom.pa1b1;
133 lpphy->txpa[2] = bus->sprom.pa1b2;
134 lpphy->txpal[0] = bus->sprom.pa1lob0;
135 lpphy->txpal[1] = bus->sprom.pa1lob1;
136 lpphy->txpal[2] = bus->sprom.pa1lob2;
137 lpphy->txpah[0] = bus->sprom.pa1hib0;
138 lpphy->txpah[1] = bus->sprom.pa1hib1;
139 lpphy->txpah[2] = bus->sprom.pa1hib2;
140 maxpwr = bus->sprom.maxpwr_al;
141 ofdmpo = bus->sprom.ofdm5glpo;
142 lpphy->max_tx_pwr_low_band = maxpwr;
143 for (i = 4; i < 12; i++) {
144 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
145 ofdmpo >>= 4;
146 }
147 maxpwr = bus->sprom.maxpwr_a;
148 ofdmpo = bus->sprom.ofdm5gpo;
149 lpphy->max_tx_pwr_med_band = maxpwr;
150 for (i = 4; i < 12; i++) {
151 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
152 ofdmpo >>= 4;
153 }
154 maxpwr = bus->sprom.maxpwr_ah;
155 ofdmpo = bus->sprom.ofdm5ghpo;
156 lpphy->max_tx_pwr_hi_band = maxpwr;
157 for (i = 4; i < 12; i++) {
158 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
159 ofdmpo >>= 4;
160 }
161 }
162}
163
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]164static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
Gábor Stefanikc65d6fb2009-08-10 20:39:47 +0200[diff] [blame]165{
166 struct b43_phy_lp *lpphy = dev->phy.lp;
Gábor Stefanikc65d6fb2009-08-10 20:39:47 +0200[diff] [blame]167 u16 temp[3];
168 u16 isolation;
169
170 B43_WARN_ON(dev->phy.rev >= 2);
171
172 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
173 isolation = lpphy->tx_isolation_med_band;
174 else if (freq <= 5320)
175 isolation = lpphy->tx_isolation_low_band;
176 else if (freq <= 5700)
177 isolation = lpphy->tx_isolation_med_band;
178 else
179 isolation = lpphy->tx_isolation_hi_band;
180
181 temp[0] = ((isolation - 26) / 12) << 12;
182 temp[1] = temp[0] + 0x1000;
183 temp[2] = temp[0] + 0x2000;
184
185 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
186 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
187}
188
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]189static void lpphy_table_init(struct b43_wldev *dev)
190{
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]191 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
192
Gábor Stefanikc65d6fb2009-08-10 20:39:47 +0200[diff] [blame]193 if (dev->phy.rev < 2)
194 lpphy_rev0_1_table_init(dev);
195 else
196 lpphy_rev2plus_table_init(dev);
197
198 lpphy_init_tx_gain_table(dev);
199
200 if (dev->phy.rev < 2)
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]201 lpphy_adjust_gain_table(dev, freq);
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]202}
203
204static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
205{
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]206 struct ssb_bus *bus = dev->dev->bus;
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]207 struct b43_phy_lp *lpphy = dev->phy.lp;
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]208 u16 tmp, tmp2;
209
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]210 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
211 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
212 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
213 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
214 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
215 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
216 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
217 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
218 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
219 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
220 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
221 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
222 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
223 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
224 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
225 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
226 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC10, 0x0180);
227 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3800);
228 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
229 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
230 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
231 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
232 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
233 0xFF00, lpphy->rx_pwr_offset);
234 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
235 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
236 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
237 /* TODO:
238 * Set the LDO voltage to 0x0028 - FIXME: What is this?
239 * Call sb_pmu_set_ldo_voltage with 4 and the LDO voltage
240 * as arguments
241 * Call sb_pmu_paref_ldo_enable with argument TRUE
242 */
243 if (dev->phy.rev == 0) {
244 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
245 0xFFCF, 0x0010);
246 }
247 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
248 } else {
249 //TODO: Call ssb_pmu_paref_ldo_enable with argument FALSE
250 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
251 0xFFCF, 0x0020);
252 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
253 }
254 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
255 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
256 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
257 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
258 else
259 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
260 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
261 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
262 0xFFF9, (lpphy->bx_arch << 1));
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]263 if (dev->phy.rev == 1 &&
264 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
265 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
266 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
267 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
268 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
269 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
277 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
278 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
279 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
280 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
281 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
282 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
283 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
284 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
285 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
289 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
290 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
292 } else if (dev->phy.rev == 1 ||
293 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
295 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
299 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
302 } else {
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
307 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
308 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
309 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
310 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
311 }
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]312 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]313 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
314 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
315 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
316 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
317 }
318 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
319 (bus->chip_id == 0x5354) &&
320 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
321 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
322 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
323 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]324 //FIXME the Broadcom driver caches & delays this HF write!
Gábor Stefanik7c81e982009-08-05 00:25:42 +0200[diff] [blame]325 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]326 }
327 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
328 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
329 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
330 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
331 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
332 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
333 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
334 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
335 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
336 } else { /* 5GHz */
337 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
338 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
339 }
340 if (dev->phy.rev == 1) {
341 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
342 tmp2 = (tmp & 0x03E0) >> 5;
343 tmp2 |= tmp << 5;
344 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
345 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
346 tmp2 = (tmp & 0x1F00) >> 8;
347 tmp2 |= tmp << 5;
348 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
349 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
350 tmp2 = tmp & 0x00FF;
351 tmp2 |= tmp << 8;
352 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
353 }
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]354}
355
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]356static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
357{
358 static const u16 addr[] = {
359 B43_PHY_OFDM(0xC1),
360 B43_PHY_OFDM(0xC2),
361 B43_PHY_OFDM(0xC3),
362 B43_PHY_OFDM(0xC4),
363 B43_PHY_OFDM(0xC5),
364 B43_PHY_OFDM(0xC6),
365 B43_PHY_OFDM(0xC7),
366 B43_PHY_OFDM(0xC8),
367 B43_PHY_OFDM(0xCF),
368 };
369
370 static const u16 coefs[] = {
371 0xDE5E, 0xE832, 0xE331, 0x4D26,
372 0x0026, 0x1420, 0x0020, 0xFE08,
373 0x0008,
374 };
375
376 struct b43_phy_lp *lpphy = dev->phy.lp;
377 int i;
378
379 for (i = 0; i < ARRAY_SIZE(addr); i++) {
380 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
381 b43_phy_write(dev, addr[i], coefs[i]);
382 }
383}
384
385static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
386{
387 static const u16 addr[] = {
388 B43_PHY_OFDM(0xC1),
389 B43_PHY_OFDM(0xC2),
390 B43_PHY_OFDM(0xC3),
391 B43_PHY_OFDM(0xC4),
392 B43_PHY_OFDM(0xC5),
393 B43_PHY_OFDM(0xC6),
394 B43_PHY_OFDM(0xC7),
395 B43_PHY_OFDM(0xC8),
396 B43_PHY_OFDM(0xCF),
397 };
398
399 struct b43_phy_lp *lpphy = dev->phy.lp;
400 int i;
401
402 for (i = 0; i < ARRAY_SIZE(addr); i++)
403 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
404}
405
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]406static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
407{
Michael Buesch686aa5f2009-02-03 19:36:45 +0100[diff] [blame]408 struct ssb_bus *bus = dev->dev->bus;
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]409 struct b43_phy_lp *lpphy = dev->phy.lp;
410
411 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
412 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
413 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
414 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
415 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
416 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
417 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
418 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
419 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]420 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]421 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
422 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
423 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
424 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
425 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
426 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
427 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]428 if (bus->boardinfo.rev >= 0x18) {
429 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
430 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
431 } else {
432 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
433 }
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]434 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]435 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]436 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
437 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
438 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
439 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
440 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
441 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]442 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]443 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
444 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
Michael Buesch686aa5f2009-02-03 19:36:45 +0100[diff] [blame]445 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
446 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
447 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
448 } else {
449 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
450 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
451 }
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]452 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
453 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
454 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
455 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
456 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
457 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
458 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
459 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
460 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
461 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
462
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]463 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]464 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
465 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
466 }
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]467
468 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
469 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
470 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
471 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
472 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
473 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]474 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]475 } else /* 5GHz */
476 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
477
478 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
479 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
480 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
481 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
482 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
483 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
484 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
485 0x2000 | ((u16)lpphy->rssi_gs << 10) |
486 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]487
488 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
489 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
490 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
491 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
492 }
493
494 lpphy_save_dig_flt_state(dev);
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]495}
496
497static void lpphy_baseband_init(struct b43_wldev *dev)
498{
499 lpphy_table_init(dev);
500 if (dev->phy.rev >= 2)
501 lpphy_baseband_rev2plus_init(dev);
502 else
503 lpphy_baseband_rev0_1_init(dev);
504}
505
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]506struct b2062_freqdata {
507 u16 freq;
508 u8 data[6];
509};
510
511/* Initialize the 2062 radio. */
512static void lpphy_2062_init(struct b43_wldev *dev)
513{
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]514 struct b43_phy_lp *lpphy = dev->phy.lp;
Michael Buesch99e0fca2009-02-03 20:06:14 +0100[diff] [blame]515 struct ssb_bus *bus = dev->dev->bus;
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]516 u32 crystalfreq, tmp, ref;
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]517 unsigned int i;
518 const struct b2062_freqdata *fd = NULL;
519
520 static const struct b2062_freqdata freqdata_tab[] = {
521 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
522 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
523 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
524 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
525 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
526 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
527 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
528 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
529 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
530 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
531 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
532 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
533 };
534
535 b2062_upload_init_table(dev);
536
537 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
538 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
539 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
Gábor Stefanik7e4d8522009-08-16 20:08:13 +0200[diff] [blame]540 b43_radio_write(dev, B2062_N_TX_CTL6, 0);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]541 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
542 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
543 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
544 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
Gábor Stefanik7e4d8522009-08-16 20:08:13 +0200[diff] [blame]545 if (dev->phy.rev > 0) {
546 b43_radio_write(dev, B2062_S_BG_CTL1,
547 (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80);
548 }
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]549 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
550 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
551 else
552 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
553
Michael Buesch99e0fca2009-02-03 20:06:14 +0100[diff] [blame]554 /* Get the crystal freq, in Hz. */
555 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
556
557 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
558 B43_WARN_ON(crystalfreq == 0);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]559
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]560 if (crystalfreq <= 30000000) {
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]561 lpphy->pdiv = 1;
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]562 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
563 } else {
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]564 lpphy->pdiv = 2;
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]565 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
566 }
567
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]568 tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
569 (2 * crystalfreq)) - 8) & 0xFF;
570 b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
571
572 tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
573 (32000000 * lpphy->pdiv)) - 1) & 0xFF;
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]574 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
575
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]576 tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
577 (2000000 * lpphy->pdiv)) - 1) & 0xFF;
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]578 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
579
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]580 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]581 ref &= 0xFFFF;
582 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
583 if (ref < freqdata_tab[i].freq) {
584 fd = &freqdata_tab[i];
585 break;
586 }
587 }
Michael Buesch99e0fca2009-02-03 20:06:14 +0100[diff] [blame]588 if (!fd)
589 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
590 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
591 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]592
593 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
594 ((u16)(fd->data[1]) << 4) | fd->data[0]);
595 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
Michael Buesch99e0fca2009-02-03 20:06:14 +0100[diff] [blame]596 ((u16)(fd->data[3]) << 4) | fd->data[2]);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]597 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
598 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
599}
600
601/* Initialize the 2063 radio. */
602static void lpphy_2063_init(struct b43_wldev *dev)
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]603{
Gábor Stefanikc10e47f2009-08-04 23:57:32 +0200[diff] [blame]604 b2063_upload_init_table(dev);
605 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
606 b43_radio_set(dev, B2063_COMM8, 0x38);
607 b43_radio_write(dev, B2063_REG_SP1, 0x56);
608 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
609 b43_radio_write(dev, B2063_PA_SP7, 0);
610 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
611 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
Gábor Stefanik5791ce12009-08-18 22:08:31 +0200[diff] [blame^]612 if (dev->phy.rev == 2) {
613 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
614 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
615 b43_radio_write(dev, B2063_PA_SP2, 0x18);
616 } else {
617 b43_radio_write(dev, B2063_PA_SP3, 0x20);
618 b43_radio_write(dev, B2063_PA_SP2, 0x20);
619 }
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]620}
621
Gábor Stefanik3281d952009-08-09 20:15:09 +0200[diff] [blame]622struct lpphy_stx_table_entry {
623 u16 phy_offset;
624 u16 phy_shift;
625 u16 rf_addr;
626 u16 rf_shift;
627 u16 mask;
628};
629
630static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
631 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
632 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
633 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
634 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
635 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
636 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
637 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
638 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
639 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
640 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
641 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
642 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
643 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
644 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
645 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
646 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
647 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
648 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
649 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
650 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
651 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
652 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
653 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
654 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
655 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
656 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
657 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
658 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
659 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
660};
661
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]662static void lpphy_sync_stx(struct b43_wldev *dev)
663{
Gábor Stefanik3281d952009-08-09 20:15:09 +0200[diff] [blame]664 const struct lpphy_stx_table_entry *e;
665 unsigned int i;
666 u16 tmp;
667
668 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
669 e = &lpphy_stx_table[i];
670 tmp = b43_radio_read(dev, e->rf_addr);
671 tmp >>= e->rf_shift;
672 tmp <<= e->phy_shift;
673 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
Gábor Stefanikd44517f22009-08-11 00:54:26 +0200[diff] [blame]674 ~(e->mask << e->phy_shift), tmp);
Gábor Stefanik3281d952009-08-09 20:15:09 +0200[diff] [blame]675 }
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]676}
677
678static void lpphy_radio_init(struct b43_wldev *dev)
679{
680 /* The radio is attached through the 4wire bus. */
681 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
682 udelay(1);
683 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
684 udelay(1);
685
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]686 if (dev->phy.radio_ver == 0x2062) {
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]687 lpphy_2062_init(dev);
688 } else {
689 lpphy_2063_init(dev);
690 lpphy_sync_stx(dev);
691 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
692 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
Gábor Stefanik3281d952009-08-09 20:15:09 +0200[diff] [blame]693 if (dev->dev->bus->chip_id == 0x4325) {
694 // TODO SSB PMU recalibration
695 }
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]696 }
697}
698
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]699struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
700
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]701static void lpphy_set_rc_cap(struct b43_wldev *dev)
702{
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]703 struct b43_phy_lp *lpphy = dev->phy.lp;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]704
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]705 u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
706
707 if (dev->phy.rev == 1) //FIXME check channel 14!
708 rc_cap = max_t(u8, rc_cap + 5, 15);
709
710 b43_radio_write(dev, B2062_N_RXBB_CALIB2,
711 max_t(u8, lpphy->rc_cap - 4, 0x80));
712 b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
713 b43_radio_write(dev, B2062_S_RXG_CNT16,
714 ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]715}
716
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]717static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]718{
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]719 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]720}
721
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]722static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]723{
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]724 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
725}
726
727static void lpphy_disable_crs(struct b43_wldev *dev)
728{
729 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
730 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
731 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
732 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
733 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
734 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
735 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
736 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
737 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
738 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
739 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
740 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
741 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
742 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
743 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
744 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
745 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
746 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
747 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
748 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
749 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
750 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
751 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
752 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
753 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
754 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
755}
756
757static void lpphy_restore_crs(struct b43_wldev *dev)
758{
759 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
760 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x60);
761 else
762 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x20);
763 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
764 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
765}
766
767struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
768
769static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
770{
771 struct lpphy_tx_gains gains;
772 u16 tmp;
773
774 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
775 if (dev->phy.rev < 2) {
776 tmp = b43_phy_read(dev,
777 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
778 gains.gm = tmp & 0x0007;
779 gains.pga = (tmp & 0x0078) >> 3;
780 gains.pad = (tmp & 0x780) >> 7;
781 } else {
782 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
783 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
784 gains.gm = tmp & 0xFF;
785 gains.pga = (tmp >> 8) & 0xFF;
786 }
787
788 return gains;
789}
790
791static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
792{
793 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
794 ctl |= dac << 7;
795 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
796}
797
798static void lpphy_set_tx_gains(struct b43_wldev *dev,
799 struct lpphy_tx_gains gains)
800{
801 u16 rf_gain, pa_gain;
802
803 if (dev->phy.rev < 2) {
804 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
805 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
806 0xF800, rf_gain);
807 } else {
808 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F00;
809 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
810 (gains.pga << 8) | gains.gm);
811 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
812 0x8000, gains.pad | pa_gain);
813 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
814 (gains.pga << 8) | gains.gm);
815 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
816 0x8000, gains.pad | pa_gain);
817 }
818 lpphy_set_dac_gain(dev, gains.dac);
819 if (dev->phy.rev < 2) {
820 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
821 } else {
822 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
823 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
824 }
Gábor Stefanik16373f62009-08-14 22:10:34 +0200[diff] [blame]825 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFBF, 1 << 6);
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]826}
827
828static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
829{
830 u16 trsw = gain & 0x1;
831 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
832 u16 ext_lna = (gain & 2) >> 1;
833
834 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
835 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
836 0xFBFF, ext_lna << 10);
837 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
838 0xF7FF, ext_lna << 11);
839 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
840}
841
842static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
843{
844 u16 low_gain = gain & 0xFFFF;
845 u16 high_gain = (gain >> 16) & 0xF;
846 u16 ext_lna = (gain >> 21) & 0x1;
847 u16 trsw = ~(gain >> 20) & 0x1;
848 u16 tmp;
849
850 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
851 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
852 0xFDFF, ext_lna << 9);
853 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
854 0xFBFF, ext_lna << 10);
855 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
856 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
857 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
858 tmp = (gain >> 2) & 0x3;
859 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
860 0xE7FF, tmp<<11);
861 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
862 }
863}
864
865static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
866{
867 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
868 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
869 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
870 if (dev->phy.rev >= 2) {
871 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
872 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
873 return;
874 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
875 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFF7);
876 } else {
877 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
878 }
879}
880
881static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
882{
883 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
884 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
885 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
886 if (dev->phy.rev >= 2) {
887 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
888 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
889 return;
890 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
891 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x8);
892 } else {
893 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
894 }
895}
896
897static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
898{
899 if (dev->phy.rev < 2)
900 lpphy_rev0_1_set_rx_gain(dev, gain);
901 else
902 lpphy_rev2plus_set_rx_gain(dev, gain);
903 lpphy_enable_rx_gain_override(dev);
904}
905
906static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
907{
908 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
909 lpphy_set_rx_gain(dev, gain);
910}
911
912static void lpphy_stop_ddfs(struct b43_wldev *dev)
913{
914 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
915 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
916}
917
918static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
919 int incr1, int incr2, int scale_idx)
920{
921 lpphy_stop_ddfs(dev);
922 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
923 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
924 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
925 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
926 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
927 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
928 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
929 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
930 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
931 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x20);
932}
933
934static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
935 struct lpphy_iq_est *iq_est)
936{
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]937 int i;
938
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]939 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
940 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
941 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
942 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
943 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFDFF);
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]944
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]945 for (i = 0; i < 500; i++) {
946 if (!(b43_phy_read(dev,
947 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]948 break;
949 msleep(1);
950 }
951
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]952 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
953 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
954 return false;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]955 }
956
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]957 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
958 iq_est->iq_prod <<= 16;
959 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]960
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]961 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
962 iq_est->i_pwr <<= 16;
963 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]964
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]965 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
966 iq_est->q_pwr <<= 16;
967 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]968
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]969 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
970 return true;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]971}
972
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]973static int lpphy_loopback(struct b43_wldev *dev)
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]974{
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]975 struct lpphy_iq_est iq_est;
976 int i, index = -1;
977 u32 tmp;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]978
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]979 memset(&iq_est, 0, sizeof(iq_est));
980
981 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
982 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
983 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
984 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
985 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
986 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
987 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
988 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
989 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
990 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
991 for (i = 0; i < 32; i++) {
992 lpphy_set_rx_gain_by_index(dev, i);
993 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
994 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
995 continue;
996 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
997 if ((tmp > 4000) && (tmp < 10000)) {
998 index = i;
999 break;
1000 }
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]1001 }
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1002 lpphy_stop_ddfs(dev);
1003 return index;
1004}
1005
1006static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1007{
1008 u32 quotient, remainder, rbit, roundup, tmp;
1009
1010 if (divisor == 0) {
1011 quotient = 0;
1012 remainder = 0;
1013 } else {
1014 quotient = dividend / divisor;
1015 remainder = dividend % divisor;
1016 }
1017
1018 rbit = divisor & 0x1;
1019 roundup = (divisor >> 1) + rbit;
1020 precision--;
1021
1022 while (precision != 0xFF) {
1023 tmp = remainder - roundup;
1024 quotient <<= 1;
1025 remainder <<= 1;
1026 if (remainder >= roundup) {
1027 remainder = (tmp << 1) + rbit;
1028 quotient--;
1029 }
1030 precision--;
1031 }
1032
1033 if (remainder >= roundup)
1034 quotient++;
1035
1036 return quotient;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]1037}
1038
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1039/* Read the TX power control mode from hardware. */
1040static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
1041{
1042 struct b43_phy_lp *lpphy = dev->phy.lp;
1043 u16 ctl;
1044
1045 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
1046 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
1047 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
1048 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
1049 break;
1050 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
1051 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
1052 break;
1053 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
1054 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
1055 break;
1056 default:
1057 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
1058 B43_WARN_ON(1);
1059 break;
1060 }
1061}
1062
1063/* Set the TX power control mode in hardware. */
1064static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
1065{
1066 struct b43_phy_lp *lpphy = dev->phy.lp;
1067 u16 ctl;
1068
1069 switch (lpphy->txpctl_mode) {
1070 case B43_LPPHY_TXPCTL_OFF:
1071 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
1072 break;
1073 case B43_LPPHY_TXPCTL_HW:
1074 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1075 break;
1076 case B43_LPPHY_TXPCTL_SW:
1077 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1078 break;
1079 default:
1080 ctl = 0;
1081 B43_WARN_ON(1);
1082 }
1083 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1084 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1085}
1086
1087static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1088 enum b43_lpphy_txpctl_mode mode)
1089{
1090 struct b43_phy_lp *lpphy = dev->phy.lp;
1091 enum b43_lpphy_txpctl_mode oldmode;
1092
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1093 lpphy_read_tx_pctl_mode_from_hardware(dev);
Gábor Stefanik12d4bba2009-08-14 20:29:47 +0200[diff] [blame]1094 oldmode = lpphy->txpctl_mode;
1095 if (oldmode == mode)
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1096 return;
1097 lpphy->txpctl_mode = mode;
1098
1099 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1100 //TODO Update TX Power NPT
1101 //TODO Clear all TX Power offsets
1102 } else {
1103 if (mode == B43_LPPHY_TXPCTL_HW) {
1104 //TODO Recalculate target TX power
1105 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1106 0xFF80, lpphy->tssi_idx);
1107 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1108 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1109 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1110 //TODO Disable TX gain override
1111 lpphy->tx_pwr_idx_over = -1;
1112 }
1113 }
1114 if (dev->phy.rev >= 2) {
1115 if (mode == B43_LPPHY_TXPCTL_HW)
1116 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
1117 else
1118 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
1119 }
1120 lpphy_write_tx_pctl_mode_to_hardware(dev);
1121}
1122
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]1123static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1124 unsigned int new_channel);
1125
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1126static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1127{
1128 struct b43_phy_lp *lpphy = dev->phy.lp;
1129 struct lpphy_iq_est iq_est;
1130 struct lpphy_tx_gains tx_gains;
1131 static const u32 ideal_pwr_table[22] = {
1132 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1133 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1134 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1135 0x0004c, 0x0002c, 0x0001a, 0xc0006,
1136 };
1137 bool old_txg_ovr;
1138 u8 old_bbmult;
1139 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
Gábor Stefanik12456842009-08-14 23:00:32 +0200[diff] [blame]1140 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1141 enum b43_lpphy_txpctl_mode old_txpctl;
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1142 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]1143 int loopback, i, j, inner_sum, err;
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1144
1145 memset(&iq_est, 0, sizeof(iq_est));
1146
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]1147 err = b43_lpphy_op_switch_channel(dev, 7);
1148 if (err) {
1149 b43dbg(dev->wl,
1150 "RC calib: Failed to switch to channel 7, error = %d",
1151 err);
1152 }
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1153 old_txg_ovr = (b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) >> 6) & 1;
1154 old_bbmult = lpphy_get_bb_mult(dev);
1155 if (old_txg_ovr)
1156 tx_gains = lpphy_get_tx_gains(dev);
1157 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1158 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1159 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1160 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1161 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1162 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1163 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
Gábor Stefanik12456842009-08-14 23:00:32 +0200[diff] [blame]1164 lpphy_read_tx_pctl_mode_from_hardware(dev);
1165 old_txpctl = lpphy->txpctl_mode;
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1166
Gábor Stefanik5f1c07d2009-08-14 21:19:58 +0200[diff] [blame]1167 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1168 lpphy_disable_crs(dev);
1169 loopback = lpphy_loopback(dev);
1170 if (loopback == -1)
1171 goto finish;
1172 lpphy_set_rx_gain_by_index(dev, loopback);
1173 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1174 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1175 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1176 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1177 for (i = 128; i <= 159; i++) {
1178 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1179 inner_sum = 0;
1180 for (j = 5; j <= 25; j++) {
1181 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1182 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1183 goto finish;
1184 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1185 if (j == 5)
1186 tmp = mean_sq_pwr;
1187 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1188 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1189 mean_sq_pwr = ideal_pwr - normal_pwr;
1190 mean_sq_pwr *= mean_sq_pwr;
1191 inner_sum += mean_sq_pwr;
1192 if ((i = 128) || (inner_sum < mean_sq_pwr_min)) {
1193 lpphy->rc_cap = i;
1194 mean_sq_pwr_min = inner_sum;
1195 }
1196 }
1197 }
1198 lpphy_stop_ddfs(dev);
1199
1200finish:
1201 lpphy_restore_crs(dev);
1202 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1203 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1204 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1205 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1206 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1207 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1208 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1209
1210 lpphy_set_bb_mult(dev, old_bbmult);
1211 if (old_txg_ovr) {
1212 /*
1213 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1214 * illogical. According to lwfinger, vendor driver v4.150.10.5
1215 * has a Set here, while v4.174.64.19 has a Get - regression in
1216 * the vendor driver? This should be tested this once the code
1217 * is testable.
1218 */
1219 lpphy_set_tx_gains(dev, tx_gains);
1220 }
1221 lpphy_set_tx_power_control(dev, old_txpctl);
1222 if (lpphy->rc_cap)
1223 lpphy_set_rc_cap(dev);
1224}
1225
1226static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1227{
1228 struct ssb_bus *bus = dev->dev->bus;
1229 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1230 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1231 int i;
1232
1233 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1234 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1235 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1236 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1237 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1238 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1239 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1240 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1241 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1242
1243 for (i = 0; i < 10000; i++) {
1244 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1245 break;
1246 msleep(1);
1247 }
1248
1249 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1250 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1251
1252 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1253
1254 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1255 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1256 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1257 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1258 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1259
1260 if (crystal_freq == 24000000) {
1261 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1262 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1263 } else {
1264 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1265 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1266 }
1267
1268 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1269
1270 for (i = 0; i < 10000; i++) {
1271 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1272 break;
1273 msleep(1);
1274 }
1275
1276 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1277 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1278
1279 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1280}
1281
1282static void lpphy_calibrate_rc(struct b43_wldev *dev)
1283{
1284 struct b43_phy_lp *lpphy = dev->phy.lp;
1285
1286 if (dev->phy.rev >= 2) {
1287 lpphy_rev2plus_rc_calib(dev);
1288 } else if (!lpphy->rc_cap) {
1289 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1290 lpphy_rev0_1_rc_calib(dev);
1291 } else {
1292 lpphy_set_rc_cap(dev);
1293 }
1294}
1295
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1296static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1297{
1298 struct b43_phy_lp *lpphy = dev->phy.lp;
1299
1300 lpphy->tx_pwr_idx_over = index;
1301 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1302 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1303
1304 //TODO
1305}
1306
1307static void lpphy_btcoex_override(struct b43_wldev *dev)
1308{
1309 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1310 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1311}
1312
1313static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1314{
1315 struct b43_phy_lp *lpphy = dev->phy.lp;
1316 u32 *saved_tab;
1317 const unsigned int saved_tab_size = 256;
1318 enum b43_lpphy_txpctl_mode txpctl_mode;
1319 s8 tx_pwr_idx_over;
1320 u16 tssi_npt, tssi_idx;
1321
1322 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1323 if (!saved_tab) {
1324 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1325 return;
1326 }
1327
1328 lpphy_read_tx_pctl_mode_from_hardware(dev);
1329 txpctl_mode = lpphy->txpctl_mode;
1330 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1331 tssi_npt = lpphy->tssi_npt;
1332 tssi_idx = lpphy->tssi_idx;
1333
1334 if (dev->phy.rev < 2) {
1335 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1336 saved_tab_size, saved_tab);
1337 } else {
1338 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1339 saved_tab_size, saved_tab);
1340 }
1341 //TODO
1342
1343 kfree(saved_tab);
1344}
1345
1346static void lpphy_calibration(struct b43_wldev *dev)
1347{
1348 struct b43_phy_lp *lpphy = dev->phy.lp;
1349 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1350
1351 b43_mac_suspend(dev);
1352
1353 lpphy_btcoex_override(dev);
1354 lpphy_read_tx_pctl_mode_from_hardware(dev);
1355 saved_pctl_mode = lpphy->txpctl_mode;
1356 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1357 //TODO Perform transmit power table I/Q LO calibration
1358 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1359 lpphy_pr41573_workaround(dev);
1360 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1361 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1362 //TODO Perform I/Q calibration with a single control value set
1363
1364 b43_mac_enable(dev);
1365}
1366
Gábor Stefanik7021f622009-08-13 17:27:31 +0200[diff] [blame]1367static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1368{
1369 if (mode != TSSI_MUX_EXT) {
1370 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1371 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1372 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1373 if (mode == TSSI_MUX_POSTPA) {
1374 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1375 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1376 } else {
1377 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1378 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1379 0xFFC7, 0x20);
1380 }
1381 } else {
1382 B43_WARN_ON(1);
1383 }
1384}
1385
1386static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1387{
1388 u16 tmp;
1389 int i;
1390
1391 //SPEC TODO Call LP PHY Clear TX Power offsets
1392 for (i = 0; i < 64; i++) {
1393 if (dev->phy.rev >= 2)
1394 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1395 else
1396 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1397 }
1398
1399 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1400 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1401 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1402 if (dev->phy.rev < 2) {
1403 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1404 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1405 } else {
1406 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1407 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1408 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1409 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1410 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1411 }
1412 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1413 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1414 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1415 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1416 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1417 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1418 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1419 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1420 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1421 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1422
1423 if (dev->phy.rev < 2) {
1424 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1425 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1426 } else {
1427 lpphy_set_tx_power_by_index(dev, 0x7F);
1428 }
1429
1430 b43_dummy_transmission(dev, true, true);
1431
1432 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1433 if (tmp & 0x8000) {
1434 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1435 0xFFC0, (tmp & 0xFF) - 32);
1436 }
1437
1438 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1439
1440 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1441 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1442}
1443
1444static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1445{
1446 struct lpphy_tx_gains gains;
1447
1448 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1449 gains.gm = 4;
1450 gains.pad = 12;
1451 gains.pga = 12;
1452 gains.dac = 0;
1453 } else {
1454 gains.gm = 7;
1455 gains.pad = 14;
1456 gains.pga = 15;
1457 gains.dac = 0;
1458 }
1459 lpphy_set_tx_gains(dev, gains);
1460 lpphy_set_bb_mult(dev, 150);
1461}
1462
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1463/* Initialize TX power control */
1464static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1465{
1466 if (0/*FIXME HWPCTL capable */) {
Gábor Stefanik7021f622009-08-13 17:27:31 +0200[diff] [blame]1467 lpphy_tx_pctl_init_hw(dev);
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1468 } else { /* This device is only software TX power control capable. */
Gábor Stefanik7021f622009-08-13 17:27:31 +0200[diff] [blame]1469 lpphy_tx_pctl_init_sw(dev);
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1470 }
1471}
1472
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1473static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1474{
Michael Buesch08887072008-08-30 11:49:45 +0200[diff] [blame]1475 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1476 return b43_read16(dev, B43_MMIO_PHY_DATA);
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1477}
1478
1479static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1480{
Michael Buesch08887072008-08-30 11:49:45 +0200[diff] [blame]1481 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1482 b43_write16(dev, B43_MMIO_PHY_DATA, value);
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1483}
1484
1485static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1486{
Michael Buesch08887072008-08-30 11:49:45 +0200[diff] [blame]1487 /* Register 1 is a 32-bit register. */
1488 B43_WARN_ON(reg == 1);
1489 /* LP-PHY needs a special bit set for read access */
1490 if (dev->phy.rev < 2) {
1491 if (reg != 0x4001)
1492 reg |= 0x100;
1493 } else
1494 reg |= 0x200;
1495
1496 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1497 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1498}
1499
1500static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1501{
1502 /* Register 1 is a 32-bit register. */
1503 B43_WARN_ON(reg == 1);
1504
Michael Buesch08887072008-08-30 11:49:45 +0200[diff] [blame]1505 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1506 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1507}
1508
1509static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
Johannes Berg19d337d2009-06-02 13:01:37 +0200[diff] [blame]1510 bool blocked)
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1511{
1512 //TODO
1513}
1514
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]1515struct b206x_channel {
1516 u8 channel;
1517 u16 freq;
1518 u8 data[12];
1519};
1520
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1521static const struct b206x_channel b2062_chantbl[] = {
1522 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
1523 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1524 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1525 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
1526 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1527 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1528 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
1529 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1530 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1531 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
1532 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1533 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1534 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
1535 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1536 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1537 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
1538 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1539 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1540 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
1541 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1542 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1543 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
1544 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1545 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1546 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
1547 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1548 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1549 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
1550 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1551 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1552 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
1553 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1554 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1555 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
1556 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1557 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1558 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
1559 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1560 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1561 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
1562 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1563 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1564 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
1565 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1566 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1567 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
1568 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1569 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1570 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
1571 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1572 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1573 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
1574 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1575 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1576 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
1577 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1578 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1579 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
1580 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1581 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1582 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
1583 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1584 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1585 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
1586 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1587 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1588 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
1589 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1590 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1591 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
1592 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1593 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1594 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
1595 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
1596 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1597 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
1598 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
1599 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1600 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
1601 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
1602 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1603 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
1604 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1605 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1606 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
1607 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1608 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1609 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
1610 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1611 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1612 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
1613 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
1614 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1615 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
1616 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1617 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1618 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
1619 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1620 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1621 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
1622 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1623 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1624 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
1625 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1626 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1627 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
1628 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1629 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1630 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
1631 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1632 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1633 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
1634 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1635 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1636 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
1637 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1638 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1639 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
1640 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1641 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1642 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
1643 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1644 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1645 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
1646 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1647 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1648 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
1649 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
1650 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1651 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
1652 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1653 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1654 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
1655 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1656 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1657 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
1658 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1659 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1660 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
1661 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
1662 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1663 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
1664 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1665 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1666 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
1667 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1668 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1669 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
1670 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
1671 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1672 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
1673 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
1674 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1675};
1676
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]1677static const struct b206x_channel b2063_chantbl[] = {
1678 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
1679 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1680 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1681 .data[10] = 0x80, .data[11] = 0x70, },
1682 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
1683 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1684 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1685 .data[10] = 0x80, .data[11] = 0x70, },
1686 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
1687 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1688 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1689 .data[10] = 0x80, .data[11] = 0x70, },
1690 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
1691 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1692 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1693 .data[10] = 0x80, .data[11] = 0x70, },
1694 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
1695 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1696 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1697 .data[10] = 0x80, .data[11] = 0x70, },
1698 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
1699 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1700 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1701 .data[10] = 0x80, .data[11] = 0x70, },
1702 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
1703 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1704 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1705 .data[10] = 0x80, .data[11] = 0x70, },
1706 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
1707 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1708 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1709 .data[10] = 0x80, .data[11] = 0x70, },
1710 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
1711 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1712 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1713 .data[10] = 0x80, .data[11] = 0x70, },
1714 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
1715 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1716 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1717 .data[10] = 0x80, .data[11] = 0x70, },
1718 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
1719 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1720 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1721 .data[10] = 0x80, .data[11] = 0x70, },
1722 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
1723 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1724 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1725 .data[10] = 0x80, .data[11] = 0x70, },
1726 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
1727 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1728 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1729 .data[10] = 0x80, .data[11] = 0x70, },
1730 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
1731 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1732 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1733 .data[10] = 0x80, .data[11] = 0x70, },
1734 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
1735 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
1736 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
1737 .data[10] = 0x20, .data[11] = 0x00, },
1738 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
1739 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
1740 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1741 .data[10] = 0x20, .data[11] = 0x00, },
1742 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
1743 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1744 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1745 .data[10] = 0x20, .data[11] = 0x00, },
1746 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
1747 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1748 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1749 .data[10] = 0x20, .data[11] = 0x00, },
1750 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
1751 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1752 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1753 .data[10] = 0x20, .data[11] = 0x00, },
1754 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
1755 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
1756 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1757 .data[10] = 0x20, .data[11] = 0x00, },
1758 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
1759 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1760 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1761 .data[10] = 0x20, .data[11] = 0x00, },
1762 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
1763 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1764 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
1765 .data[10] = 0x20, .data[11] = 0x00, },
1766 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
1767 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
1768 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
1769 .data[10] = 0x20, .data[11] = 0x00, },
1770 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
1771 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1772 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1773 .data[10] = 0x10, .data[11] = 0x00, },
1774 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
1775 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1776 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1777 .data[10] = 0x10, .data[11] = 0x00, },
1778 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
1779 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1780 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1781 .data[10] = 0x10, .data[11] = 0x00, },
1782 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
1783 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1784 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1785 .data[10] = 0x00, .data[11] = 0x00, },
1786 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
1787 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1788 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1789 .data[10] = 0x00, .data[11] = 0x00, },
1790 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
1791 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1792 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1793 .data[10] = 0x00, .data[11] = 0x00, },
1794 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
1795 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1796 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1797 .data[10] = 0x00, .data[11] = 0x00, },
1798 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
1799 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1800 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1801 .data[10] = 0x00, .data[11] = 0x00, },
1802 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
1803 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1804 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1805 .data[10] = 0x00, .data[11] = 0x00, },
1806 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
1807 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1808 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1809 .data[10] = 0x00, .data[11] = 0x00, },
1810 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
1811 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1812 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1813 .data[10] = 0x00, .data[11] = 0x00, },
1814 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
1815 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1816 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1817 .data[10] = 0x00, .data[11] = 0x00, },
1818 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
1819 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1820 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1821 .data[10] = 0x00, .data[11] = 0x00, },
1822 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
1823 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1824 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1825 .data[10] = 0x00, .data[11] = 0x00, },
1826 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
1827 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1828 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1829 .data[10] = 0x00, .data[11] = 0x00, },
1830 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
1831 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1832 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1833 .data[10] = 0x00, .data[11] = 0x00, },
1834 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
1835 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1836 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1837 .data[10] = 0x00, .data[11] = 0x00, },
1838 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
1839 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1840 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1841 .data[10] = 0x00, .data[11] = 0x00, },
1842 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
1843 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1844 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1845 .data[10] = 0x00, .data[11] = 0x00, },
1846 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
1847 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
1848 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
1849 .data[10] = 0x50, .data[11] = 0x00, },
1850 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
1851 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
1852 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1853 .data[10] = 0x50, .data[11] = 0x00, },
1854 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
1855 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1856 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1857 .data[10] = 0x50, .data[11] = 0x00, },
1858 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
1859 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1860 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1861 .data[10] = 0x40, .data[11] = 0x00, },
1862 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
1863 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
1864 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1865 .data[10] = 0x40, .data[11] = 0x00, },
1866 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
1867 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
1868 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1869 .data[10] = 0x40, .data[11] = 0x00, },
1870 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
1871 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
1872 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1873 .data[10] = 0x40, .data[11] = 0x00, },
1874 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
1875 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
1876 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1877 .data[10] = 0x40, .data[11] = 0x00, },
1878 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
1879 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
1880 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1881 .data[10] = 0x40, .data[11] = 0x00, },
1882};
1883
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1884static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]1885{
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1886 struct ssb_bus *bus = dev->dev->bus;
1887
1888 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
1889 udelay(20);
1890 if (bus->chip_id == 0x5354) {
1891 b43_radio_write(dev, B2062_N_COMM1, 4);
1892 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
1893 } else {
1894 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
1895 }
1896 udelay(5);
1897}
1898
1899static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
1900{
1901 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x42);
1902 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x62);
1903 udelay(200);
1904}
1905
1906static int lpphy_b2062_tune(struct b43_wldev *dev,
1907 unsigned int channel)
1908{
1909 struct b43_phy_lp *lpphy = dev->phy.lp;
1910 struct ssb_bus *bus = dev->dev->bus;
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]1911 const struct b206x_channel *chandata = NULL;
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1912 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1913 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
1914 int i, err = 0;
1915
Gábor Stefanik5269102e2009-08-16 18:05:09 +0200[diff] [blame]1916 for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
1917 if (b2062_chantbl[i].channel == channel) {
1918 chandata = &b2062_chantbl[i];
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1919 break;
1920 }
1921 }
1922
1923 if (B43_WARN_ON(!chandata))
1924 return -EINVAL;
1925
1926 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
1927 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
1928 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
1929 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
1930 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
1931 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
1932 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
1933 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
1934 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
1935 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
1936
1937 tmp1 = crystal_freq / 1000;
1938 tmp2 = lpphy->pdiv * 1000;
1939 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
1940 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
1941 lpphy_b2062_reset_pll_bias(dev);
1942 tmp3 = tmp2 * channel2freq_lp(channel);
1943 if (channel2freq_lp(channel) < 4000)
1944 tmp3 *= 2;
1945 tmp4 = 48 * tmp1;
1946 tmp6 = tmp3 / tmp4;
1947 tmp7 = tmp3 % tmp4;
1948 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
1949 tmp5 = tmp7 * 0x100;
1950 tmp6 = tmp5 / tmp4;
1951 tmp7 = tmp5 % tmp4;
Gábor Stefanik055114a2009-08-16 15:32:40 +0200[diff] [blame]1952 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
1953 tmp5 = tmp7 * 0x100;
1954 tmp6 = tmp5 / tmp4;
1955 tmp7 = tmp5 % tmp4;
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1956 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
1957 tmp5 = tmp7 * 0x100;
1958 tmp6 = tmp5 / tmp4;
1959 tmp7 = tmp5 % tmp4;
1960 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
1961 tmp8 = b43_phy_read(dev, B2062_S_RFPLL_CTL19);
1962 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
Gábor Stefaniked07c4b2009-08-16 18:40:09 +0200[diff] [blame]1963 b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16);
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1964 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
1965
1966 lpphy_b2062_vco_calib(dev);
1967 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
1968 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
1969 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
1970 lpphy_b2062_reset_pll_bias(dev);
1971 lpphy_b2062_vco_calib(dev);
1972 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]1973 err = -EIO;
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1974 }
1975
1976 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
1977 return err;
1978}
1979
Gábor Stefanik5791ce12009-08-18 22:08:31 +0200[diff] [blame^]1980
1981/* This was previously called lpphy_japan_filter */
1982static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1983{
1984 struct b43_phy_lp *lpphy = dev->phy.lp;
1985 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
1986
1987 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
1988 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
1989 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
1990 lpphy_set_rc_cap(dev);
1991 } else {
1992 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
1993 }
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]1994}
1995
1996static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
1997{
1998 u16 tmp;
1999
2000 b43_phy_mask(dev, B2063_PLL_SP1, ~0x40);
2001 tmp = b43_phy_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
2002 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
2003 udelay(1);
2004 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
2005 udelay(1);
2006 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
2007 udelay(1);
2008 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
2009 udelay(300);
2010 b43_phy_set(dev, B2063_PLL_SP1, 0x40);
2011}
2012
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2013static int lpphy_b2063_tune(struct b43_wldev *dev,
2014 unsigned int channel)
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2015{
2016 struct ssb_bus *bus = dev->dev->bus;
2017
2018 static const struct b206x_channel *chandata = NULL;
2019 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2020 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
2021 u16 old_comm15, scale;
2022 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
2023 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
2024
2025 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
2026 if (b2063_chantbl[i].channel == channel) {
2027 chandata = &b2063_chantbl[i];
2028 break;
2029 }
2030 }
2031
2032 if (B43_WARN_ON(!chandata))
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2033 return -EINVAL;
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2034
2035 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
2036 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
2037 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
2038 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
2039 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
2040 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
2041 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
2042 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
2043 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
2044 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
2045 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
2046 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
2047
2048 old_comm15 = b43_radio_read(dev, B2063_COMM15);
2049 b43_radio_set(dev, B2063_COMM15, 0x1E);
2050
2051 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
2052 vco_freq = chandata->freq << 1;
2053 else
2054 vco_freq = chandata->freq << 2;
2055
2056 freqref = crystal_freq * 3;
2057 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
2058 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
2059 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
2060 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
2061 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
2062 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
2063 0xFFF8, timeout >> 2);
2064 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2065 0xFF9F,timeout << 5);
2066
2067 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
2068 999999) / 1000000) + 1;
2069 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
2070
2071 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
2072 count *= (timeout + 1) * (timeoutref + 1);
2073 count--;
2074 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2075 0xF0, count >> 8);
2076 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
2077
2078 tmp1 = ((val3 * 62500) / freqref) << 4;
2079 tmp2 = ((val3 * 62500) % freqref) << 4;
2080 while (tmp2 >= freqref) {
2081 tmp1++;
2082 tmp2 -= freqref;
2083 }
2084 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
2085 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
2086 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
2087 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
2088 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2089
2090 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2091 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2092 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2093 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2094
2095 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2096 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2097
2098 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2099 scale = 1;
2100 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2101 } else {
2102 scale = 0;
2103 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2104 }
2105 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2106 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2107
2108 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2109 tmp6 *= (tmp5 * 8) * (scale + 1);
2110 if (tmp6 > 150)
2111 tmp6 = 0;
2112
2113 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2114 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2115
2116 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2117 if (crystal_freq > 26000000)
2118 b43_phy_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2119 else
2120 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2121
2122 if (val1 == 45)
2123 b43_phy_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2124 else
2125 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2126
2127 b43_phy_set(dev, B2063_PLL_SP2, 0x3);
2128 udelay(1);
2129 b43_phy_mask(dev, B2063_PLL_SP2, 0xFFFC);
2130 lpphy_b2063_vco_calib(dev);
2131 b43_radio_write(dev, B2063_COMM15, old_comm15);
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2132
2133 return 0;
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2134}
2135
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2136static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2137 unsigned int new_channel)
2138{
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2139 int err;
2140
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2141 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2142
2143 if (dev->phy.radio_ver == 0x2063) {
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2144 err = lpphy_b2063_tune(dev, new_channel);
2145 if (err)
2146 return err;
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2147 } else {
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2148 err = lpphy_b2062_tune(dev, new_channel);
2149 if (err)
2150 return err;
Gábor Stefanik5791ce12009-08-18 22:08:31 +0200[diff] [blame^]2151 lpphy_set_analog_filter(dev, new_channel);
Gábor Stefanik0c61bb92009-08-14 21:11:59 +0200[diff] [blame]2152 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2153 }
2154
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2155 return 0;
2156}
2157
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2158static int b43_lpphy_op_init(struct b43_wldev *dev)
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2159{
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]2160 int err;
2161
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2162 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2163 lpphy_baseband_init(dev);
2164 lpphy_radio_init(dev);
2165 lpphy_calibrate_rc(dev);
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]2166 err = b43_lpphy_op_switch_channel(dev,
2167 b43_lpphy_op_get_default_chan(dev));
2168 if (err) {
2169 b43dbg(dev->wl, "Switch to init channel failed, error = %d.\n",
2170 err);
2171 }
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2172 lpphy_tx_pctl_init(dev);
2173 lpphy_calibration(dev);
2174 //TODO ACI init
2175
2176 return 0;
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2177}
2178
2179static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2180{
2181 //TODO
2182}
2183
2184static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2185{
2186 //TODO
2187}
2188
2189static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2190 bool ignore_tssi)
2191{
2192 //TODO
2193 return B43_TXPWR_RES_DONE;
2194}
2195
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2196const struct b43_phy_operations b43_phyops_lp = {
2197 .allocate = b43_lpphy_op_allocate,
Michael Bueschfb111372008-09-02 13:00:34 +0200[diff] [blame]2198 .free = b43_lpphy_op_free,
2199 .prepare_structs = b43_lpphy_op_prepare_structs,
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2200 .init = b43_lpphy_op_init,
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2201 .phy_read = b43_lpphy_op_read,
2202 .phy_write = b43_lpphy_op_write,
2203 .radio_read = b43_lpphy_op_radio_read,
2204 .radio_write = b43_lpphy_op_radio_write,
2205 .software_rfkill = b43_lpphy_op_software_rfkill,
Michael Bueschcb24f572008-09-03 12:12:20 +0200[diff] [blame]2206 .switch_analog = b43_phyop_switch_analog_generic,
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2207 .switch_channel = b43_lpphy_op_switch_channel,
2208 .get_default_chan = b43_lpphy_op_get_default_chan,
2209 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2210 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2211 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2212};