blob: 9cb39644b6f1f588570bb7b8984ad54383c417d4 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
Thiemo Seufer115f2a42006-07-09 01:47:06 +01008 * Copyright (C) 2004,2005,2006 by Thiemo Seufer
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00009 * Copyright (C) 2005 Maciej W. Rozycki
Ralf Baechle41c594a2006-04-05 09:45:45 +010010 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 *
12 * ... and the days got worse and worse and now you see
13 * I've gone completly out of my mind.
14 *
15 * They're coming to take me a away haha
16 * they're coming to take me a away hoho hihi haha
17 * to the funny farm where code is beautiful all the time ...
18 *
19 * (Condolences to Napoleon XIV)
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 */
21
22#include <stdarg.h>
23
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/mm.h>
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/string.h>
28#include <linux/init.h>
29
30#include <asm/pgtable.h>
31#include <asm/cacheflush.h>
32#include <asm/mmu_context.h>
33#include <asm/inst.h>
34#include <asm/elf.h>
35#include <asm/smp.h>
36#include <asm/war.h>
37
David Rientjese8b6d402007-05-10 22:51:05 -070038static __init int __maybe_unused r45k_bvahwbug(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039{
40 /* XXX: We should probe for the presence of this bug, but we don't. */
41 return 0;
42}
43
David Rientjese8b6d402007-05-10 22:51:05 -070044static __init int __maybe_unused r4k_250MHZhwbug(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070045{
46 /* XXX: We should probe for the presence of this bug, but we don't. */
47 return 0;
48}
49
David Rientjese8b6d402007-05-10 22:51:05 -070050static __init int __maybe_unused bcm1250_m3_war(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070051{
52 return BCM1250_M3_WAR;
53}
54
David Rientjese8b6d402007-05-10 22:51:05 -070055static __init int __maybe_unused r10000_llsc_war(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070056{
57 return R10000_LLSC_WAR;
58}
59
60/*
61 * A little micro-assembler, intended for TLB refill handler
62 * synthesizing. It is intentionally kept simple, does only support
63 * a subset of instructions, and does not try to hide pipeline effects
64 * like branch delay slots.
65 */
66
67enum fields
68{
69 RS = 0x001,
70 RT = 0x002,
71 RD = 0x004,
72 RE = 0x008,
73 SIMM = 0x010,
74 UIMM = 0x020,
75 BIMM = 0x040,
76 JIMM = 0x080,
77 FUNC = 0x100,
Ralf Baechle41c594a2006-04-05 09:45:45 +010078 SET = 0x200
Linus Torvalds1da177e2005-04-16 15:20:36 -070079};
80
Thiemo Seufer603c3382007-09-05 12:11:22 +010081#define OP_MASK 0x3f
Linus Torvalds1da177e2005-04-16 15:20:36 -070082#define OP_SH 26
83#define RS_MASK 0x1f
84#define RS_SH 21
85#define RT_MASK 0x1f
86#define RT_SH 16
87#define RD_MASK 0x1f
88#define RD_SH 11
89#define RE_MASK 0x1f
90#define RE_SH 6
91#define IMM_MASK 0xffff
92#define IMM_SH 0
93#define JIMM_MASK 0x3ffffff
94#define JIMM_SH 0
Thiemo Seufer603c3382007-09-05 12:11:22 +010095#define FUNC_MASK 0x3f
Linus Torvalds1da177e2005-04-16 15:20:36 -070096#define FUNC_SH 0
Ralf Baechle41c594a2006-04-05 09:45:45 +010097#define SET_MASK 0x7
98#define SET_SH 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
100enum opcode {
101 insn_invalid,
102 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
103 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
104 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
Ralf Baechle242954b2006-10-24 02:29:01 +0100105 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
107 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
108 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
109 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi,
110 insn_tlbwr, insn_xor, insn_xori
111};
112
113struct insn {
114 enum opcode opcode;
115 u32 match;
116 enum fields fields;
117};
118
119/* This macro sets the non-variable bits of an instruction. */
120#define M(a, b, c, d, e, f) \
121 ((a) << OP_SH \
122 | (b) << RS_SH \
123 | (c) << RT_SH \
124 | (d) << RD_SH \
125 | (e) << RE_SH \
126 | (f) << FUNC_SH)
127
128static __initdata struct insn insn_table[] = {
129 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM },
130 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD },
131 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD },
132 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM },
133 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM },
134 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM },
135 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM },
136 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM },
137 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM },
138 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM },
139 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM },
140 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM },
141 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD },
Ralf Baechle41c594a2006-04-05 09:45:45 +0100142 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET},
143 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE },
145 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
146 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
147 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
Ralf Baechle242954b2006-10-24 02:29:01 +0100148 { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
150 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
151 { insn_j, M(j_op,0,0,0,0,0), JIMM },
152 { insn_jal, M(jal_op,0,0,0,0,0), JIMM },
153 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS },
154 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM },
155 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM },
156 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM },
157 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM },
158 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM },
Ralf Baechle41c594a2006-04-05 09:45:45 +0100159 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET},
160 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM },
162 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 },
163 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM },
164 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM },
165 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM },
166 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE },
167 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE },
168 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE },
169 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD },
170 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM },
171 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 },
172 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 },
173 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 },
174 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD },
175 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM },
176 { insn_invalid, 0, 0 }
177};
178
179#undef M
180
181static __init u32 build_rs(u32 arg)
182{
183 if (arg & ~RS_MASK)
184 printk(KERN_WARNING "TLB synthesizer field overflow\n");
185
186 return (arg & RS_MASK) << RS_SH;
187}
188
189static __init u32 build_rt(u32 arg)
190{
191 if (arg & ~RT_MASK)
192 printk(KERN_WARNING "TLB synthesizer field overflow\n");
193
194 return (arg & RT_MASK) << RT_SH;
195}
196
197static __init u32 build_rd(u32 arg)
198{
199 if (arg & ~RD_MASK)
200 printk(KERN_WARNING "TLB synthesizer field overflow\n");
201
202 return (arg & RD_MASK) << RD_SH;
203}
204
205static __init u32 build_re(u32 arg)
206{
207 if (arg & ~RE_MASK)
208 printk(KERN_WARNING "TLB synthesizer field overflow\n");
209
210 return (arg & RE_MASK) << RE_SH;
211}
212
213static __init u32 build_simm(s32 arg)
214{
215 if (arg > 0x7fff || arg < -0x8000)
216 printk(KERN_WARNING "TLB synthesizer field overflow\n");
217
218 return arg & 0xffff;
219}
220
221static __init u32 build_uimm(u32 arg)
222{
223 if (arg & ~IMM_MASK)
224 printk(KERN_WARNING "TLB synthesizer field overflow\n");
225
226 return arg & IMM_MASK;
227}
228
229static __init u32 build_bimm(s32 arg)
230{
231 if (arg > 0x1ffff || arg < -0x20000)
232 printk(KERN_WARNING "TLB synthesizer field overflow\n");
233
234 if (arg & 0x3)
235 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n");
236
237 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
238}
239
240static __init u32 build_jimm(u32 arg)
241{
242 if (arg & ~((JIMM_MASK) << 2))
243 printk(KERN_WARNING "TLB synthesizer field overflow\n");
244
245 return (arg >> 2) & JIMM_MASK;
246}
247
248static __init u32 build_func(u32 arg)
249{
250 if (arg & ~FUNC_MASK)
251 printk(KERN_WARNING "TLB synthesizer field overflow\n");
252
253 return arg & FUNC_MASK;
254}
255
Ralf Baechle41c594a2006-04-05 09:45:45 +0100256static __init u32 build_set(u32 arg)
257{
258 if (arg & ~SET_MASK)
259 printk(KERN_WARNING "TLB synthesizer field overflow\n");
260
261 return arg & SET_MASK;
262}
263
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264/*
265 * The order of opcode arguments is implicitly left to right,
266 * starting with RS and ending with FUNC or IMM.
267 */
268static void __init build_insn(u32 **buf, enum opcode opc, ...)
269{
270 struct insn *ip = NULL;
271 unsigned int i;
272 va_list ap;
273 u32 op;
274
275 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
276 if (insn_table[i].opcode == opc) {
277 ip = &insn_table[i];
278 break;
279 }
280
281 if (!ip)
282 panic("Unsupported TLB synthesizer instruction %d", opc);
283
284 op = ip->match;
285 va_start(ap, opc);
286 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32));
287 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32));
288 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32));
289 if (ip->fields & RE) op |= build_re(va_arg(ap, u32));
290 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32));
291 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32));
292 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32));
293 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32));
294 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32));
Ralf Baechle41c594a2006-04-05 09:45:45 +0100295 if (ip->fields & SET) op |= build_set(va_arg(ap, u32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296 va_end(ap);
297
298 **buf = op;
299 (*buf)++;
300}
301
302#define I_u1u2u3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000303 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 unsigned int b, unsigned int c) \
305 { \
306 build_insn(buf, insn##op, a, b, c); \
307 }
308
309#define I_u2u1u3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000310 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311 unsigned int b, unsigned int c) \
312 { \
313 build_insn(buf, insn##op, b, a, c); \
314 }
315
316#define I_u3u1u2(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000317 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318 unsigned int b, unsigned int c) \
319 { \
320 build_insn(buf, insn##op, b, c, a); \
321 }
322
323#define I_u1u2s3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000324 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 unsigned int b, signed int c) \
326 { \
327 build_insn(buf, insn##op, a, b, c); \
328 }
329
330#define I_u2s3u1(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000331 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 signed int b, unsigned int c) \
333 { \
334 build_insn(buf, insn##op, c, a, b); \
335 }
336
337#define I_u2u1s3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000338 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339 unsigned int b, signed int c) \
340 { \
341 build_insn(buf, insn##op, b, a, c); \
342 }
343
344#define I_u1u2(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000345 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346 unsigned int b) \
347 { \
348 build_insn(buf, insn##op, a, b); \
349 }
350
351#define I_u1s2(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000352 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 signed int b) \
354 { \
355 build_insn(buf, insn##op, a, b); \
356 }
357
358#define I_u1(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000359 static inline void __init i##op(u32 **buf, unsigned int a) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 { \
361 build_insn(buf, insn##op, a); \
362 }
363
364#define I_0(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000365 static inline void __init i##op(u32 **buf) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366 { \
367 build_insn(buf, insn##op); \
368 }
369
370I_u2u1s3(_addiu);
371I_u3u1u2(_addu);
372I_u2u1u3(_andi);
373I_u3u1u2(_and);
374I_u1u2s3(_beq);
375I_u1u2s3(_beql);
376I_u1s2(_bgez);
377I_u1s2(_bgezl);
378I_u1s2(_bltz);
379I_u1s2(_bltzl);
380I_u1u2s3(_bne);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100381I_u1u2u3(_dmfc0);
382I_u1u2u3(_dmtc0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383I_u2u1s3(_daddiu);
384I_u3u1u2(_daddu);
385I_u2u1u3(_dsll);
386I_u2u1u3(_dsll32);
387I_u2u1u3(_dsra);
388I_u2u1u3(_dsrl);
Ralf Baechle242954b2006-10-24 02:29:01 +0100389I_u2u1u3(_dsrl32);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390I_u3u1u2(_dsubu);
391I_0(_eret);
392I_u1(_j);
393I_u1(_jal);
394I_u1(_jr);
395I_u2s3u1(_ld);
396I_u2s3u1(_ll);
397I_u2s3u1(_lld);
398I_u1s2(_lui);
399I_u2s3u1(_lw);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100400I_u1u2u3(_mfc0);
401I_u1u2u3(_mtc0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402I_u2u1u3(_ori);
403I_0(_rfe);
404I_u2s3u1(_sc);
405I_u2s3u1(_scd);
406I_u2s3u1(_sd);
407I_u2u1u3(_sll);
408I_u2u1u3(_sra);
409I_u2u1u3(_srl);
410I_u3u1u2(_subu);
411I_u2s3u1(_sw);
412I_0(_tlbp);
413I_0(_tlbwi);
414I_0(_tlbwr);
415I_u3u1u2(_xor)
416I_u2u1u3(_xori);
417
418/*
419 * handling labels
420 */
421
422enum label_id {
423 label_invalid,
424 label_second_part,
425 label_leave,
Atsushi Nemoto656be922006-10-26 00:08:31 +0900426#ifdef MODULE_START
427 label_module_alloc,
428#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429 label_vmalloc,
430 label_vmalloc_done,
431 label_tlbw_hazard,
432 label_split,
433 label_nopage_tlbl,
434 label_nopage_tlbs,
435 label_nopage_tlbm,
436 label_smp_pgtable_change,
437 label_r3000_write_probe_fail,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438};
439
440struct label {
441 u32 *addr;
442 enum label_id lab;
443};
444
445static __init void build_label(struct label **lab, u32 *addr,
446 enum label_id l)
447{
448 (*lab)->addr = addr;
449 (*lab)->lab = l;
450 (*lab)++;
451}
452
453#define L_LA(lb) \
454 static inline void l##lb(struct label **lab, u32 *addr) \
455 { \
456 build_label(lab, addr, label##lb); \
457 }
458
459L_LA(_second_part)
460L_LA(_leave)
Atsushi Nemoto656be922006-10-26 00:08:31 +0900461#ifdef MODULE_START
462L_LA(_module_alloc)
463#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464L_LA(_vmalloc)
465L_LA(_vmalloc_done)
466L_LA(_tlbw_hazard)
467L_LA(_split)
468L_LA(_nopage_tlbl)
469L_LA(_nopage_tlbs)
470L_LA(_nopage_tlbm)
471L_LA(_smp_pgtable_change)
472L_LA(_r3000_write_probe_fail)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473
474/* convenience macros for instructions */
Ralf Baechle875d43e2005-09-03 15:56:16 -0700475#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476# define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off)
477# define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off)
478# define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh)
479# define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh)
480# define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100481# define i_MFC0(buf, rt, rd...) i_dmfc0(buf, rt, rd)
482# define i_MTC0(buf, rt, rd...) i_dmtc0(buf, rt, rd)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483# define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val)
484# define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd)
485# define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd)
486# define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off)
487# define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off)
488#else
489# define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off)
490# define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off)
491# define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh)
492# define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh)
493# define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100494# define i_MFC0(buf, rt, rd...) i_mfc0(buf, rt, rd)
495# define i_MTC0(buf, rt, rd...) i_mtc0(buf, rt, rd)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496# define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val)
497# define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd)
498# define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd)
499# define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off)
500# define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off)
501#endif
502
503#define i_b(buf, off) i_beq(buf, 0, 0, off)
504#define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off)
505#define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off)
506#define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off)
507#define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off)
508#define i_move(buf, a, b) i_ADDU(buf, a, 0, b)
509#define i_nop(buf) i_sll(buf, 0, 0, 0)
510#define i_ssnop(buf) i_sll(buf, 0, 0, 1)
511#define i_ehb(buf) i_sll(buf, 0, 0, 3)
512
Ralf Baechle875d43e2005-09-03 15:56:16 -0700513#ifdef CONFIG_64BIT
David Rientjese8b6d402007-05-10 22:51:05 -0700514static __init int __maybe_unused in_compat_space_p(long addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515{
516 /* Is this address in 32bit compat space? */
Ralf Baechle3ef33e62005-07-08 20:10:17 +0000517 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518}
519
David Rientjese8b6d402007-05-10 22:51:05 -0700520static __init int __maybe_unused rel_highest(long val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521{
522 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
523}
524
David Rientjese8b6d402007-05-10 22:51:05 -0700525static __init int __maybe_unused rel_higher(long val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526{
527 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
528}
529#endif
530
531static __init int rel_hi(long val)
532{
533 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
534}
535
536static __init int rel_lo(long val)
537{
538 return ((val & 0xffff) ^ 0x8000) - 0x8000;
539}
540
541static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
542{
Yoichi Yuasa766160c2005-09-03 15:56:22 -0700543#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 if (!in_compat_space_p(addr)) {
545 i_lui(buf, rs, rel_highest(addr));
546 if (rel_higher(addr))
547 i_daddiu(buf, rs, rs, rel_higher(addr));
548 if (rel_hi(addr)) {
549 i_dsll(buf, rs, rs, 16);
550 i_daddiu(buf, rs, rs, rel_hi(addr));
551 i_dsll(buf, rs, rs, 16);
552 } else
553 i_dsll32(buf, rs, rs, 0);
554 } else
555#endif
556 i_lui(buf, rs, rel_hi(addr));
557}
558
David Rientjese8b6d402007-05-10 22:51:05 -0700559static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs,
560 long addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561{
562 i_LA_mostly(buf, rs, addr);
563 if (rel_lo(addr))
564 i_ADDIU(buf, rs, rs, rel_lo(addr));
565}
566
567/*
568 * handle relocations
569 */
570
571struct reloc {
572 u32 *addr;
573 unsigned int type;
574 enum label_id lab;
575};
576
577static __init void r_mips_pc16(struct reloc **rel, u32 *addr,
578 enum label_id l)
579{
580 (*rel)->addr = addr;
581 (*rel)->type = R_MIPS_PC16;
582 (*rel)->lab = l;
583 (*rel)++;
584}
585
586static inline void __resolve_relocs(struct reloc *rel, struct label *lab)
587{
588 long laddr = (long)lab->addr;
589 long raddr = (long)rel->addr;
590
591 switch (rel->type) {
592 case R_MIPS_PC16:
593 *rel->addr |= build_bimm(laddr - (raddr + 4));
594 break;
595
596 default:
597 panic("Unsupported TLB synthesizer relocation %d",
598 rel->type);
599 }
600}
601
602static __init void resolve_relocs(struct reloc *rel, struct label *lab)
603{
604 struct label *l;
605
606 for (; rel->lab != label_invalid; rel++)
607 for (l = lab; l->lab != label_invalid; l++)
608 if (rel->lab == l->lab)
609 __resolve_relocs(rel, l);
610}
611
612static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
613 long off)
614{
615 for (; rel->lab != label_invalid; rel++)
616 if (rel->addr >= first && rel->addr < end)
617 rel->addr += off;
618}
619
620static __init void move_labels(struct label *lab, u32 *first, u32 *end,
621 long off)
622{
623 for (; lab->lab != label_invalid; lab++)
624 if (lab->addr >= first && lab->addr < end)
625 lab->addr += off;
626}
627
628static __init void copy_handler(struct reloc *rel, struct label *lab,
629 u32 *first, u32 *end, u32 *target)
630{
631 long off = (long)(target - first);
632
633 memcpy(target, first, (end - first) * sizeof(u32));
634
635 move_relocs(rel, first, end, off);
636 move_labels(lab, first, end, off);
637}
638
David Rientjese8b6d402007-05-10 22:51:05 -0700639static __init int __maybe_unused insn_has_bdelay(struct reloc *rel,
640 u32 *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641{
642 for (; rel->lab != label_invalid; rel++) {
643 if (rel->addr == addr
644 && (rel->type == R_MIPS_PC16
645 || rel->type == R_MIPS_26))
646 return 1;
647 }
648
649 return 0;
650}
651
652/* convenience functions for labeled branches */
David Rientjese8b6d402007-05-10 22:51:05 -0700653static void __init __maybe_unused
Ralf Baechle1443e482006-03-08 15:37:26 +0000654 il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655{
656 r_mips_pc16(r, *p, l);
657 i_bltz(p, reg, 0);
658}
659
David Rientjese8b6d402007-05-10 22:51:05 -0700660static void __init __maybe_unused il_b(u32 **p, struct reloc **r,
661 enum label_id l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662{
663 r_mips_pc16(r, *p, l);
664 i_b(p, 0);
665}
666
Ralf Baechle1443e482006-03-08 15:37:26 +0000667static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 enum label_id l)
669{
670 r_mips_pc16(r, *p, l);
671 i_beqz(p, reg, 0);
672}
673
David Rientjese8b6d402007-05-10 22:51:05 -0700674static void __init __maybe_unused
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
676{
677 r_mips_pc16(r, *p, l);
678 i_beqzl(p, reg, 0);
679}
680
Ralf Baechle1443e482006-03-08 15:37:26 +0000681static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 enum label_id l)
683{
684 r_mips_pc16(r, *p, l);
685 i_bnez(p, reg, 0);
686}
687
Ralf Baechle1443e482006-03-08 15:37:26 +0000688static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689 enum label_id l)
690{
691 r_mips_pc16(r, *p, l);
692 i_bgezl(p, reg, 0);
693}
694
David Rientjese8b6d402007-05-10 22:51:05 -0700695static void __init __maybe_unused
Atsushi Nemoto656be922006-10-26 00:08:31 +0900696il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
697{
698 r_mips_pc16(r, *p, l);
699 i_bgez(p, reg, 0);
700}
701
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702/* The only general purpose registers allowed in TLB handlers. */
703#define K0 26
704#define K1 27
705
706/* Some CP0 registers */
Ralf Baechle41c594a2006-04-05 09:45:45 +0100707#define C0_INDEX 0, 0
708#define C0_ENTRYLO0 2, 0
709#define C0_TCBIND 2, 2
710#define C0_ENTRYLO1 3, 0
711#define C0_CONTEXT 4, 0
712#define C0_BADVADDR 8, 0
713#define C0_ENTRYHI 10, 0
714#define C0_EPC 14, 0
715#define C0_XCONTEXT 20, 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716
Ralf Baechle875d43e2005-09-03 15:56:16 -0700717#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT)
719#else
720# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT)
721#endif
722
723/* The worst case length of the handler is around 18 instructions for
724 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
725 * Maximum space available is 32 instructions for R3000 and 64
726 * instructions for R4000.
727 *
728 * We deliberately chose a buffer size of 128, so we won't scribble
729 * over anything important on overflow before we panic.
730 */
731static __initdata u32 tlb_handler[128];
732
733/* simply assume worst case size for labels and relocs */
734static __initdata struct label labels[128];
735static __initdata struct reloc relocs[128];
736
737/*
738 * The R3000 TLB handler is simple.
739 */
740static void __init build_r3000_tlb_refill_handler(void)
741{
742 long pgdc = (long)pgd_current;
743 u32 *p;
Thiemo Seufer115f2a42006-07-09 01:47:06 +0100744 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745
746 memset(tlb_handler, 0, sizeof(tlb_handler));
747 p = tlb_handler;
748
749 i_mfc0(&p, K0, C0_BADVADDR);
750 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */
751 i_lw(&p, K1, rel_lo(pgdc), K1);
752 i_srl(&p, K0, K0, 22); /* load delay */
753 i_sll(&p, K0, K0, 2);
754 i_addu(&p, K1, K1, K0);
755 i_mfc0(&p, K0, C0_CONTEXT);
756 i_lw(&p, K1, 0, K1); /* cp0 delay */
757 i_andi(&p, K0, K0, 0xffc); /* load delay */
758 i_addu(&p, K1, K1, K0);
759 i_lw(&p, K0, 0, K1);
760 i_nop(&p); /* load delay */
761 i_mtc0(&p, K0, C0_ENTRYLO0);
762 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
763 i_tlbwr(&p); /* cp0 delay */
764 i_jr(&p, K1);
765 i_rfe(&p); /* branch delay */
766
767 if (p > tlb_handler + 32)
768 panic("TLB refill handler space exceeded");
769
Thiemo Seufer115f2a42006-07-09 01:47:06 +0100770 pr_info("Synthesized TLB refill handler (%u instructions).\n",
771 (unsigned int)(p - tlb_handler));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772
Thiemo Seufer115f2a42006-07-09 01:47:06 +0100773 pr_debug("\t.set push\n");
774 pr_debug("\t.set noreorder\n");
775 for (i = 0; i < (p - tlb_handler); i++)
776 pr_debug("\t.word 0x%08x\n", tlb_handler[i]);
777 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778
Ralf Baechle91b05e62006-03-29 18:53:00 +0100779 memcpy((void *)ebase, tlb_handler, 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780}
781
782/*
783 * The R4000 TLB handler is much more complicated. We have two
784 * consecutive handler areas with 32 instructions space each.
785 * Since they aren't used at the same time, we can overflow in the
786 * other one.To keep things simple, we first assume linear space,
787 * then we relocate it to the final handler layout as needed.
788 */
789static __initdata u32 final_handler[64];
790
791/*
792 * Hazards
793 *
794 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
795 * 2. A timing hazard exists for the TLBP instruction.
796 *
797 * stalling_instruction
798 * TLBP
799 *
800 * The JTLB is being read for the TLBP throughout the stall generated by the
801 * previous instruction. This is not really correct as the stalling instruction
802 * can modify the address used to access the JTLB. The failure symptom is that
803 * the TLBP instruction will use an address created for the stalling instruction
804 * and not the address held in C0_ENHI and thus report the wrong results.
805 *
806 * The software work-around is to not allow the instruction preceding the TLBP
807 * to stall - make it an NOP or some other instruction guaranteed not to stall.
808 *
809 * Errata 2 will not be fixed. This errata is also on the R5000.
810 *
811 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
812 */
David Rientjese8b6d402007-05-10 22:51:05 -0700813static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814{
815 switch (current_cpu_data.cputype) {
Thiemo Seuferf5b4d952005-09-09 17:11:50 +0000816 /* Found by experiment: R4600 v2.0 needs this, too. */
817 case CPU_R4600:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 case CPU_R5000:
819 case CPU_R5000A:
820 case CPU_NEVADA:
821 i_nop(p);
822 i_tlbp(p);
823 break;
824
825 default:
826 i_tlbp(p);
827 break;
828 }
829}
830
831/*
832 * Write random or indexed TLB entry, and care about the hazards from
833 * the preceeding mtc0 and for the following eret.
834 */
835enum tlb_write_entry { tlb_random, tlb_indexed };
836
837static __init void build_tlb_write_entry(u32 **p, struct label **l,
838 struct reloc **r,
839 enum tlb_write_entry wmode)
840{
841 void(*tlbw)(u32 **) = NULL;
842
843 switch (wmode) {
844 case tlb_random: tlbw = i_tlbwr; break;
845 case tlb_indexed: tlbw = i_tlbwi; break;
846 }
847
848 switch (current_cpu_data.cputype) {
849 case CPU_R4000PC:
850 case CPU_R4000SC:
851 case CPU_R4000MC:
852 case CPU_R4400PC:
853 case CPU_R4400SC:
854 case CPU_R4400MC:
855 /*
856 * This branch uses up a mtc0 hazard nop slot and saves
857 * two nops after the tlbw instruction.
858 */
859 il_bgezl(p, r, 0, label_tlbw_hazard);
860 tlbw(p);
861 l_tlbw_hazard(l, *p);
862 i_nop(p);
863 break;
864
865 case CPU_R4600:
866 case CPU_R4700:
867 case CPU_R5000:
868 case CPU_R5000A:
Maciej W. Rozycki2c93e122005-06-30 10:51:01 +0000869 i_nop(p);
870 tlbw(p);
871 i_nop(p);
872 break;
873
874 case CPU_R4300:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 case CPU_5KC:
876 case CPU_TX49XX:
877 case CPU_AU1000:
878 case CPU_AU1100:
879 case CPU_AU1500:
880 case CPU_AU1550:
Pete Popove3ad1c22005-03-01 06:33:16 +0000881 case CPU_AU1200:
Pete Popovbdf21b12005-07-14 17:47:57 +0000882 case CPU_PR4450:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 i_nop(p);
884 tlbw(p);
885 break;
886
887 case CPU_R10000:
888 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -0400889 case CPU_R14000:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 case CPU_4KC:
891 case CPU_SB1:
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700892 case CPU_SB1A:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893 case CPU_4KSC:
894 case CPU_20KC:
895 case CPU_25KF:
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800896 case CPU_LOONGSON2:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897 tlbw(p);
898 break;
899
900 case CPU_NEVADA:
901 i_nop(p); /* QED specifies 2 nops hazard */
902 /*
903 * This branch uses up a mtc0 hazard nop slot and saves
904 * a nop after the tlbw instruction.
905 */
906 il_bgezl(p, r, 0, label_tlbw_hazard);
907 tlbw(p);
908 l_tlbw_hazard(l, *p);
909 break;
910
911 case CPU_RM7000:
912 i_nop(p);
913 i_nop(p);
914 i_nop(p);
915 i_nop(p);
916 tlbw(p);
917 break;
918
919 case CPU_4KEC:
920 case CPU_24K:
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000921 case CPU_34K:
Chris Dearmanc6209532006-05-02 14:08:46 +0100922 case CPU_74K:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700923 i_ehb(p);
924 tlbw(p);
925 break;
926
927 case CPU_RM9000:
928 /*
929 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
930 * use of the JTLB for instructions should not occur for 4
931 * cpu cycles and use for data translations should not occur
932 * for 3 cpu cycles.
933 */
934 i_ssnop(p);
935 i_ssnop(p);
936 i_ssnop(p);
937 i_ssnop(p);
938 tlbw(p);
939 i_ssnop(p);
940 i_ssnop(p);
941 i_ssnop(p);
942 i_ssnop(p);
943 break;
944
945 case CPU_VR4111:
946 case CPU_VR4121:
947 case CPU_VR4122:
948 case CPU_VR4181:
949 case CPU_VR4181A:
950 i_nop(p);
951 i_nop(p);
952 tlbw(p);
953 i_nop(p);
954 i_nop(p);
955 break;
956
957 case CPU_VR4131:
958 case CPU_VR4133:
Ralf Baechle7623deb2005-08-29 16:49:55 +0000959 case CPU_R5432:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960 i_nop(p);
961 i_nop(p);
962 tlbw(p);
963 break;
964
965 default:
966 panic("No TLB refill handler yet (CPU type: %d)",
967 current_cpu_data.cputype);
968 break;
969 }
970}
971
Ralf Baechle875d43e2005-09-03 15:56:16 -0700972#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973/*
974 * TMP and PTR are scratch.
975 * TMP will be clobbered, PTR will hold the pmd entry.
976 */
977static __init void
978build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
979 unsigned int tmp, unsigned int ptr)
980{
981 long pgdc = (long)pgd_current;
982
983 /*
984 * The vmalloc handling is not in the hotpath.
985 */
986 i_dmfc0(p, tmp, C0_BADVADDR);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900987#ifdef MODULE_START
988 il_bltz(p, r, tmp, label_module_alloc);
989#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990 il_bltz(p, r, tmp, label_vmalloc);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900991#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992 /* No i_nop needed here, since the next insn doesn't touch TMP. */
993
994#ifdef CONFIG_SMP
Ralf Baechle41c594a2006-04-05 09:45:45 +0100995# ifdef CONFIG_MIPS_MT_SMTC
996 /*
997 * SMTC uses TCBind value as "CPU" index
998 */
999 i_mfc0(p, ptr, C0_TCBIND);
1000 i_dsrl(p, ptr, ptr, 19);
1001# else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002 /*
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +00001003 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 * stored in CONTEXT.
1005 */
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +00001006 i_dmfc0(p, ptr, C0_CONTEXT);
1007 i_dsrl(p, ptr, ptr, 23);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001008#endif
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +00001009 i_LA_mostly(p, tmp, pgdc);
1010 i_daddu(p, ptr, ptr, tmp);
1011 i_dmfc0(p, tmp, C0_BADVADDR);
1012 i_ld(p, ptr, rel_lo(pgdc), ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013#else
1014 i_LA_mostly(p, ptr, pgdc);
1015 i_ld(p, ptr, rel_lo(pgdc), ptr);
1016#endif
1017
1018 l_vmalloc_done(l, *p);
Ralf Baechle242954b2006-10-24 02:29:01 +01001019
1020 if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */
1021 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3);
1022 else
1023 i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32);
1024
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
1026 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
1027 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
1028 i_ld(p, ptr, 0, ptr); /* get pmd pointer */
1029 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
1030 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
1031 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
1032}
1033
1034/*
1035 * BVADDR is the faulting address, PTR is scratch.
1036 * PTR will hold the pgd for vmalloc.
1037 */
1038static __init void
1039build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1040 unsigned int bvaddr, unsigned int ptr)
1041{
1042 long swpd = (long)swapper_pg_dir;
1043
Atsushi Nemoto656be922006-10-26 00:08:31 +09001044#ifdef MODULE_START
1045 long modd = (long)module_pg_dir;
1046
1047 l_module_alloc(l, *p);
1048 /*
1049 * Assumption:
1050 * VMALLOC_START >= 0xc000000000000000UL
1051 * MODULE_START >= 0xe000000000000000UL
1052 */
1053 i_SLL(p, ptr, bvaddr, 2);
1054 il_bgez(p, r, ptr, label_vmalloc);
1055
1056 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START)) {
1057 i_lui(p, ptr, rel_hi(MODULE_START)); /* delay slot */
1058 } else {
1059 /* unlikely configuration */
1060 i_nop(p); /* delay slot */
1061 i_LA(p, ptr, MODULE_START);
1062 }
1063 i_dsubu(p, bvaddr, bvaddr, ptr);
1064
1065 if (in_compat_space_p(modd) && !rel_lo(modd)) {
1066 il_b(p, r, label_vmalloc_done);
1067 i_lui(p, ptr, rel_hi(modd));
1068 } else {
1069 i_LA_mostly(p, ptr, modd);
1070 il_b(p, r, label_vmalloc_done);
1071 i_daddiu(p, ptr, ptr, rel_lo(modd));
1072 }
1073
1074 l_vmalloc(l, *p);
1075 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START) &&
1076 MODULE_START << 32 == VMALLOC_START)
1077 i_dsll32(p, ptr, ptr, 0); /* typical case */
1078 else
1079 i_LA(p, ptr, VMALLOC_START);
1080#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001081 l_vmalloc(l, *p);
1082 i_LA(p, ptr, VMALLOC_START);
Atsushi Nemoto656be922006-10-26 00:08:31 +09001083#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084 i_dsubu(p, bvaddr, bvaddr, ptr);
1085
1086 if (in_compat_space_p(swpd) && !rel_lo(swpd)) {
1087 il_b(p, r, label_vmalloc_done);
1088 i_lui(p, ptr, rel_hi(swpd));
1089 } else {
1090 i_LA_mostly(p, ptr, swpd);
1091 il_b(p, r, label_vmalloc_done);
1092 i_daddiu(p, ptr, ptr, rel_lo(swpd));
1093 }
1094}
1095
Ralf Baechle875d43e2005-09-03 15:56:16 -07001096#else /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097
1098/*
1099 * TMP and PTR are scratch.
1100 * TMP will be clobbered, PTR will hold the pgd entry.
1101 */
David Rientjese8b6d402007-05-10 22:51:05 -07001102static __init void __maybe_unused
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1104{
1105 long pgdc = (long)pgd_current;
1106
1107 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
1108#ifdef CONFIG_SMP
Ralf Baechle41c594a2006-04-05 09:45:45 +01001109#ifdef CONFIG_MIPS_MT_SMTC
1110 /*
1111 * SMTC uses TCBind value as "CPU" index
1112 */
1113 i_mfc0(p, ptr, C0_TCBIND);
1114 i_LA_mostly(p, tmp, pgdc);
1115 i_srl(p, ptr, ptr, 19);
1116#else
1117 /*
1118 * smp_processor_id() << 3 is stored in CONTEXT.
1119 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120 i_mfc0(p, ptr, C0_CONTEXT);
1121 i_LA_mostly(p, tmp, pgdc);
1122 i_srl(p, ptr, ptr, 23);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001123#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124 i_addu(p, ptr, tmp, ptr);
1125#else
1126 i_LA_mostly(p, ptr, pgdc);
1127#endif
1128 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
1129 i_lw(p, ptr, rel_lo(pgdc), ptr);
1130 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
1131 i_sll(p, tmp, tmp, PGD_T_LOG2);
1132 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1133}
1134
Ralf Baechle875d43e2005-09-03 15:56:16 -07001135#endif /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001136
1137static __init void build_adjust_context(u32 **p, unsigned int ctx)
1138{
Ralf Baechle242954b2006-10-24 02:29:01 +01001139 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1141
1142 switch (current_cpu_data.cputype) {
1143 case CPU_VR41XX:
1144 case CPU_VR4111:
1145 case CPU_VR4121:
1146 case CPU_VR4122:
1147 case CPU_VR4131:
1148 case CPU_VR4181:
1149 case CPU_VR4181A:
1150 case CPU_VR4133:
1151 shift += 2;
1152 break;
1153
1154 default:
1155 break;
1156 }
1157
1158 if (shift)
1159 i_SRL(p, ctx, ctx, shift);
1160 i_andi(p, ctx, ctx, mask);
1161}
1162
1163static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1164{
1165 /*
1166 * Bug workaround for the Nevada. It seems as if under certain
1167 * circumstances the move from cp0_context might produce a
1168 * bogus result when the mfc0 instruction and its consumer are
1169 * in a different cacheline or a load instruction, probably any
1170 * memory reference, is between them.
1171 */
1172 switch (current_cpu_data.cputype) {
1173 case CPU_NEVADA:
1174 i_LW(p, ptr, 0, ptr);
1175 GET_CONTEXT(p, tmp); /* get context reg */
1176 break;
1177
1178 default:
1179 GET_CONTEXT(p, tmp); /* get context reg */
1180 i_LW(p, ptr, 0, ptr);
1181 break;
1182 }
1183
1184 build_adjust_context(p, tmp);
1185 i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1186}
1187
1188static __init void build_update_entries(u32 **p, unsigned int tmp,
1189 unsigned int ptep)
1190{
1191 /*
1192 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1193 * Kernel is a special case. Only a few CPUs use it.
1194 */
1195#ifdef CONFIG_64BIT_PHYS_ADDR
1196 if (cpu_has_64bits) {
1197 i_ld(p, tmp, 0, ptep); /* get even pte */
1198 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1199 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
1200 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1201 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
1202 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1203 } else {
1204 int pte_off_even = sizeof(pte_t) / 2;
1205 int pte_off_odd = pte_off_even + sizeof(pte_t);
1206
1207 /* The pte entries are pre-shifted */
1208 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1209 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1210 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1211 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1212 }
1213#else
1214 i_LW(p, tmp, 0, ptep); /* get even pte */
1215 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1216 if (r45k_bvahwbug())
1217 build_tlb_probe_entry(p);
1218 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
1219 if (r4k_250MHZhwbug())
1220 i_mtc0(p, 0, C0_ENTRYLO0);
1221 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1222 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
1223 if (r45k_bvahwbug())
1224 i_mfc0(p, tmp, C0_INDEX);
1225 if (r4k_250MHZhwbug())
1226 i_mtc0(p, 0, C0_ENTRYLO1);
1227 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1228#endif
1229}
1230
1231static void __init build_r4000_tlb_refill_handler(void)
1232{
1233 u32 *p = tlb_handler;
1234 struct label *l = labels;
1235 struct reloc *r = relocs;
1236 u32 *f;
1237 unsigned int final_len;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001238 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239
1240 memset(tlb_handler, 0, sizeof(tlb_handler));
1241 memset(labels, 0, sizeof(labels));
1242 memset(relocs, 0, sizeof(relocs));
1243 memset(final_handler, 0, sizeof(final_handler));
1244
1245 /*
1246 * create the plain linear handler
1247 */
1248 if (bcm1250_m3_war()) {
1249 i_MFC0(&p, K0, C0_BADVADDR);
1250 i_MFC0(&p, K1, C0_ENTRYHI);
1251 i_xor(&p, K0, K0, K1);
1252 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1253 il_bnez(&p, &r, K0, label_leave);
1254 /* No need for i_nop */
1255 }
1256
Ralf Baechle875d43e2005-09-03 15:56:16 -07001257#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1259#else
1260 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1261#endif
1262
1263 build_get_ptep(&p, K0, K1);
1264 build_update_entries(&p, K0, K1);
1265 build_tlb_write_entry(&p, &l, &r, tlb_random);
1266 l_leave(&l, p);
1267 i_eret(&p); /* return from trap */
1268
Ralf Baechle875d43e2005-09-03 15:56:16 -07001269#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
1271#endif
1272
1273 /*
1274 * Overflow check: For the 64bit handler, we need at least one
1275 * free instruction slot for the wrap-around branch. In worst
1276 * case, if the intended insertion point is a delay slot, we
Matt LaPlante4b3f6862006-10-03 22:21:02 +02001277 * need three, with the second nop'ed and the third being
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278 * unused.
1279 */
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001280 /* Loongson2 ebase is different than r4k, we have more space */
1281#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001282 if ((p - tlb_handler) > 64)
1283 panic("TLB refill handler space exceeded");
1284#else
1285 if (((p - tlb_handler) > 63)
1286 || (((p - tlb_handler) > 61)
1287 && insn_has_bdelay(relocs, tlb_handler + 29)))
1288 panic("TLB refill handler space exceeded");
1289#endif
1290
1291 /*
1292 * Now fold the handler in the TLB refill handler space.
1293 */
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001294#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001295 f = final_handler;
1296 /* Simplest case, just copy the handler. */
1297 copy_handler(relocs, labels, tlb_handler, p, f);
1298 final_len = p - tlb_handler;
Ralf Baechle875d43e2005-09-03 15:56:16 -07001299#else /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300 f = final_handler + 32;
1301 if ((p - tlb_handler) <= 32) {
1302 /* Just copy the handler. */
1303 copy_handler(relocs, labels, tlb_handler, p, f);
1304 final_len = p - tlb_handler;
1305 } else {
1306 u32 *split = tlb_handler + 30;
1307
1308 /*
1309 * Find the split point.
1310 */
1311 if (insn_has_bdelay(relocs, split - 1))
1312 split--;
1313
1314 /* Copy first part of the handler. */
1315 copy_handler(relocs, labels, tlb_handler, split, f);
1316 f += split - tlb_handler;
1317
1318 /* Insert branch. */
1319 l_split(&l, final_handler);
1320 il_b(&f, &r, label_split);
1321 if (insn_has_bdelay(relocs, split))
1322 i_nop(&f);
1323 else {
1324 copy_handler(relocs, labels, split, split + 1, f);
1325 move_labels(labels, f, f + 1, -1);
1326 f++;
1327 split++;
1328 }
1329
1330 /* Copy the rest of the handler. */
1331 copy_handler(relocs, labels, split, p, final_handler);
1332 final_len = (f - (final_handler + 32)) + (p - split);
1333 }
Ralf Baechle875d43e2005-09-03 15:56:16 -07001334#endif /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001335
1336 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001337 pr_info("Synthesized TLB refill handler (%u instructions).\n",
1338 final_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001340 f = final_handler;
Fuxin Zhang2a21c732007-06-06 14:52:43 +08001341#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2)
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001342 if (final_len > 32)
1343 final_len = 64;
1344 else
1345 f = final_handler + 32;
Maciej W. Rozycki4c0a2d42005-06-29 10:43:51 +00001346#endif /* CONFIG_64BIT */
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001347 pr_debug("\t.set push\n");
1348 pr_debug("\t.set noreorder\n");
1349 for (i = 0; i < final_len; i++)
1350 pr_debug("\t.word 0x%08x\n", f[i]);
1351 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352
Ralf Baechle91b05e62006-03-29 18:53:00 +01001353 memcpy((void *)ebase, final_handler, 0x100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354}
1355
1356/*
1357 * TLB load/store/modify handlers.
1358 *
1359 * Only the fastpath gets synthesized at runtime, the slowpath for
1360 * do_page_fault remains normal asm.
1361 */
1362extern void tlb_do_page_fault_0(void);
1363extern void tlb_do_page_fault_1(void);
1364
1365#define __tlb_handler_align \
1366 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
1367
1368/*
1369 * 128 instructions for the fastpath handler is generous and should
1370 * never be exceeded.
1371 */
1372#define FASTPATH_SIZE 128
1373
1374u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE];
1375u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE];
1376u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
1377
1378static void __init
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001379iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380{
1381#ifdef CONFIG_SMP
1382# ifdef CONFIG_64BIT_PHYS_ADDR
1383 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001384 i_lld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385 else
1386# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001387 i_LL(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388#else
1389# ifdef CONFIG_64BIT_PHYS_ADDR
1390 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001391 i_ld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001392 else
1393# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001394 i_LW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395#endif
1396}
1397
1398static void __init
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001399iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr,
1400 unsigned int mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001402#ifdef CONFIG_64BIT_PHYS_ADDR
1403 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1404#endif
1405
1406 i_ori(p, pte, pte, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407#ifdef CONFIG_SMP
1408# ifdef CONFIG_64BIT_PHYS_ADDR
1409 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001410 i_scd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001411 else
1412# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001413 i_SC(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414
1415 if (r10000_llsc_war())
1416 il_beqzl(p, r, pte, label_smp_pgtable_change);
1417 else
1418 il_beqz(p, r, pte, label_smp_pgtable_change);
1419
1420# ifdef CONFIG_64BIT_PHYS_ADDR
1421 if (!cpu_has_64bits) {
1422 /* no i_nop needed */
1423 i_ll(p, pte, sizeof(pte_t) / 2, ptr);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001424 i_ori(p, pte, pte, hwmode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425 i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1426 il_beqz(p, r, pte, label_smp_pgtable_change);
1427 /* no i_nop needed */
1428 i_lw(p, pte, 0, ptr);
1429 } else
1430 i_nop(p);
1431# else
1432 i_nop(p);
1433# endif
1434#else
1435# ifdef CONFIG_64BIT_PHYS_ADDR
1436 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001437 i_sd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438 else
1439# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001440 i_SW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001441
1442# ifdef CONFIG_64BIT_PHYS_ADDR
1443 if (!cpu_has_64bits) {
1444 i_lw(p, pte, sizeof(pte_t) / 2, ptr);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001445 i_ori(p, pte, pte, hwmode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446 i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1447 i_lw(p, pte, 0, ptr);
1448 }
1449# endif
1450#endif
1451}
1452
1453/*
1454 * Check if PTE is present, if not then jump to LABEL. PTR points to
1455 * the page table where this PTE is located, PTE will be re-loaded
1456 * with it's original value.
1457 */
1458static void __init
1459build_pte_present(u32 **p, struct label **l, struct reloc **r,
1460 unsigned int pte, unsigned int ptr, enum label_id lid)
1461{
1462 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1463 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1464 il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001465 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466}
1467
1468/* Make PTE valid, store result in PTR. */
1469static void __init
1470build_make_valid(u32 **p, struct reloc **r, unsigned int pte,
1471 unsigned int ptr)
1472{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001473 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1474
1475 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476}
1477
1478/*
1479 * Check if PTE can be written to, if not branch to LABEL. Regardless
1480 * restore PTE with value from PTR when done.
1481 */
1482static void __init
1483build_pte_writable(u32 **p, struct label **l, struct reloc **r,
1484 unsigned int pte, unsigned int ptr, enum label_id lid)
1485{
1486 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1487 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1488 il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001489 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490}
1491
1492/* Make PTE writable, update software status bits as well, then store
1493 * at PTR.
1494 */
1495static void __init
1496build_make_write(u32 **p, struct reloc **r, unsigned int pte,
1497 unsigned int ptr)
1498{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001499 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1500 | _PAGE_DIRTY);
1501
1502 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001503}
1504
1505/*
1506 * Check if PTE can be modified, if not branch to LABEL. Regardless
1507 * restore PTE with value from PTR when done.
1508 */
1509static void __init
1510build_pte_modifiable(u32 **p, struct label **l, struct reloc **r,
1511 unsigned int pte, unsigned int ptr, enum label_id lid)
1512{
1513 i_andi(p, pte, pte, _PAGE_WRITE);
1514 il_beqz(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001515 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001516}
1517
1518/*
1519 * R3000 style TLB load/store/modify handlers.
1520 */
1521
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001522/*
1523 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1524 * Then it returns.
1525 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526static void __init
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001527build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528{
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001529 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1530 i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1531 i_tlbwi(p);
1532 i_jr(p, tmp);
1533 i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534}
1535
1536/*
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001537 * This places the pte into ENTRYLO0 and writes it with tlbwi
1538 * or tlbwr as appropriate. This is because the index register
1539 * may have the probe fail bit set as a result of a trap on a
1540 * kseg2 access, i.e. without refill. Then it returns.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541 */
1542static void __init
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001543build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r,
1544 unsigned int pte, unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545{
1546 i_mfc0(p, tmp, C0_INDEX);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001547 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1548 il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1549 i_mfc0(p, tmp, C0_EPC); /* branch delay */
1550 i_tlbwi(p); /* cp0 delay */
1551 i_jr(p, tmp);
1552 i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 l_r3000_write_probe_fail(l, *p);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001554 i_tlbwr(p); /* cp0 delay */
1555 i_jr(p, tmp);
1556 i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557}
1558
1559static void __init
1560build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1561 unsigned int ptr)
1562{
1563 long pgdc = (long)pgd_current;
1564
1565 i_mfc0(p, pte, C0_BADVADDR);
1566 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */
1567 i_lw(p, ptr, rel_lo(pgdc), ptr);
1568 i_srl(p, pte, pte, 22); /* load delay */
1569 i_sll(p, pte, pte, 2);
1570 i_addu(p, ptr, ptr, pte);
1571 i_mfc0(p, pte, C0_CONTEXT);
1572 i_lw(p, ptr, 0, ptr); /* cp0 delay */
1573 i_andi(p, pte, pte, 0xffc); /* load delay */
1574 i_addu(p, ptr, ptr, pte);
1575 i_lw(p, pte, 0, ptr);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001576 i_tlbp(p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001577}
1578
1579static void __init build_r3000_tlb_load_handler(void)
1580{
1581 u32 *p = handle_tlbl;
1582 struct label *l = labels;
1583 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001584 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585
1586 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1587 memset(labels, 0, sizeof(labels));
1588 memset(relocs, 0, sizeof(relocs));
1589
1590 build_r3000_tlbchange_handler_head(&p, K0, K1);
1591 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001592 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001593 build_make_valid(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001594 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001595
1596 l_nopage_tlbl(&l, p);
1597 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1598 i_nop(&p);
1599
1600 if ((p - handle_tlbl) > FASTPATH_SIZE)
1601 panic("TLB load handler fastpath space exceeded");
1602
1603 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001604 pr_info("Synthesized TLB load handler fastpath (%u instructions).\n",
1605 (unsigned int)(p - handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001607 pr_debug("\t.set push\n");
1608 pr_debug("\t.set noreorder\n");
1609 for (i = 0; i < (p - handle_tlbl); i++)
1610 pr_debug("\t.word 0x%08x\n", handle_tlbl[i]);
1611 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001612}
1613
1614static void __init build_r3000_tlb_store_handler(void)
1615{
1616 u32 *p = handle_tlbs;
1617 struct label *l = labels;
1618 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001619 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001620
1621 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1622 memset(labels, 0, sizeof(labels));
1623 memset(relocs, 0, sizeof(relocs));
1624
1625 build_r3000_tlbchange_handler_head(&p, K0, K1);
1626 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001627 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001628 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001629 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630
1631 l_nopage_tlbs(&l, p);
1632 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1633 i_nop(&p);
1634
1635 if ((p - handle_tlbs) > FASTPATH_SIZE)
1636 panic("TLB store handler fastpath space exceeded");
1637
1638 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001639 pr_info("Synthesized TLB store handler fastpath (%u instructions).\n",
1640 (unsigned int)(p - handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001641
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001642 pr_debug("\t.set push\n");
1643 pr_debug("\t.set noreorder\n");
1644 for (i = 0; i < (p - handle_tlbs); i++)
1645 pr_debug("\t.word 0x%08x\n", handle_tlbs[i]);
1646 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001647}
1648
1649static void __init build_r3000_tlb_modify_handler(void)
1650{
1651 u32 *p = handle_tlbm;
1652 struct label *l = labels;
1653 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001654 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001655
1656 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1657 memset(labels, 0, sizeof(labels));
1658 memset(relocs, 0, sizeof(relocs));
1659
1660 build_r3000_tlbchange_handler_head(&p, K0, K1);
1661 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001662 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001663 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001664 build_r3000_pte_reload_tlbwi(&p, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001665
1666 l_nopage_tlbm(&l, p);
1667 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1668 i_nop(&p);
1669
1670 if ((p - handle_tlbm) > FASTPATH_SIZE)
1671 panic("TLB modify handler fastpath space exceeded");
1672
1673 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001674 pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n",
1675 (unsigned int)(p - handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001676
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001677 pr_debug("\t.set push\n");
1678 pr_debug("\t.set noreorder\n");
1679 for (i = 0; i < (p - handle_tlbm); i++)
1680 pr_debug("\t.word 0x%08x\n", handle_tlbm[i]);
1681 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682}
1683
1684/*
1685 * R4000 style TLB load/store/modify handlers.
1686 */
1687static void __init
1688build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
1689 struct reloc **r, unsigned int pte,
1690 unsigned int ptr)
1691{
Ralf Baechle875d43e2005-09-03 15:56:16 -07001692#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001693 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1694#else
1695 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1696#endif
1697
1698 i_MFC0(p, pte, C0_BADVADDR);
1699 i_LW(p, ptr, 0, ptr);
1700 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1701 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1702 i_ADDU(p, ptr, ptr, pte);
1703
1704#ifdef CONFIG_SMP
1705 l_smp_pgtable_change(l, *p);
1706# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001707 iPTE_LW(p, l, pte, ptr); /* get even pte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001708 build_tlb_probe_entry(p);
1709}
1710
1711static void __init
1712build_r4000_tlbchange_handler_tail(u32 **p, struct label **l,
1713 struct reloc **r, unsigned int tmp,
1714 unsigned int ptr)
1715{
1716 i_ori(p, ptr, ptr, sizeof(pte_t));
1717 i_xori(p, ptr, ptr, sizeof(pte_t));
1718 build_update_entries(p, tmp, ptr);
1719 build_tlb_write_entry(p, l, r, tlb_indexed);
1720 l_leave(l, *p);
1721 i_eret(p); /* return from trap */
1722
Ralf Baechle875d43e2005-09-03 15:56:16 -07001723#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1725#endif
1726}
1727
1728static void __init build_r4000_tlb_load_handler(void)
1729{
1730 u32 *p = handle_tlbl;
1731 struct label *l = labels;
1732 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001733 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734
1735 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1736 memset(labels, 0, sizeof(labels));
1737 memset(relocs, 0, sizeof(relocs));
1738
1739 if (bcm1250_m3_war()) {
1740 i_MFC0(&p, K0, C0_BADVADDR);
1741 i_MFC0(&p, K1, C0_ENTRYHI);
1742 i_xor(&p, K0, K0, K1);
1743 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1744 il_bnez(&p, &r, K0, label_leave);
1745 /* No need for i_nop */
1746 }
1747
1748 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1749 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
1750 build_make_valid(&p, &r, K0, K1);
1751 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1752
1753 l_nopage_tlbl(&l, p);
1754 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1755 i_nop(&p);
1756
1757 if ((p - handle_tlbl) > FASTPATH_SIZE)
1758 panic("TLB load handler fastpath space exceeded");
1759
1760 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001761 pr_info("Synthesized TLB load handler fastpath (%u instructions).\n",
1762 (unsigned int)(p - handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001763
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001764 pr_debug("\t.set push\n");
1765 pr_debug("\t.set noreorder\n");
1766 for (i = 0; i < (p - handle_tlbl); i++)
1767 pr_debug("\t.word 0x%08x\n", handle_tlbl[i]);
1768 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769}
1770
1771static void __init build_r4000_tlb_store_handler(void)
1772{
1773 u32 *p = handle_tlbs;
1774 struct label *l = labels;
1775 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001776 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001777
1778 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1779 memset(labels, 0, sizeof(labels));
1780 memset(relocs, 0, sizeof(relocs));
1781
1782 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1783 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
1784 build_make_write(&p, &r, K0, K1);
1785 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1786
1787 l_nopage_tlbs(&l, p);
1788 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1789 i_nop(&p);
1790
1791 if ((p - handle_tlbs) > FASTPATH_SIZE)
1792 panic("TLB store handler fastpath space exceeded");
1793
1794 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001795 pr_info("Synthesized TLB store handler fastpath (%u instructions).\n",
1796 (unsigned int)(p - handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001797
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001798 pr_debug("\t.set push\n");
1799 pr_debug("\t.set noreorder\n");
1800 for (i = 0; i < (p - handle_tlbs); i++)
1801 pr_debug("\t.word 0x%08x\n", handle_tlbs[i]);
1802 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001803}
1804
1805static void __init build_r4000_tlb_modify_handler(void)
1806{
1807 u32 *p = handle_tlbm;
1808 struct label *l = labels;
1809 struct reloc *r = relocs;
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001810 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811
1812 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1813 memset(labels, 0, sizeof(labels));
1814 memset(relocs, 0, sizeof(relocs));
1815
1816 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1817 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
1818 /* Present and writable bits set, set accessed and dirty bits. */
1819 build_make_write(&p, &r, K0, K1);
1820 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1821
1822 l_nopage_tlbm(&l, p);
1823 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1824 i_nop(&p);
1825
1826 if ((p - handle_tlbm) > FASTPATH_SIZE)
1827 panic("TLB modify handler fastpath space exceeded");
1828
1829 resolve_relocs(relocs, labels);
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001830 pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n",
1831 (unsigned int)(p - handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832
Thiemo Seufer115f2a42006-07-09 01:47:06 +01001833 pr_debug("\t.set push\n");
1834 pr_debug("\t.set noreorder\n");
1835 for (i = 0; i < (p - handle_tlbm); i++)
1836 pr_debug("\t.word 0x%08x\n", handle_tlbm[i]);
1837 pr_debug("\t.set pop\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001838}
1839
1840void __init build_tlb_refill_handler(void)
1841{
1842 /*
1843 * The refill handler is generated per-CPU, multi-node systems
1844 * may have local storage for it. The other handlers are only
1845 * needed once.
1846 */
1847 static int run_once = 0;
1848
1849 switch (current_cpu_data.cputype) {
1850 case CPU_R2000:
1851 case CPU_R3000:
1852 case CPU_R3000A:
1853 case CPU_R3081E:
1854 case CPU_TX3912:
1855 case CPU_TX3922:
1856 case CPU_TX3927:
1857 build_r3000_tlb_refill_handler();
1858 if (!run_once) {
1859 build_r3000_tlb_load_handler();
1860 build_r3000_tlb_store_handler();
1861 build_r3000_tlb_modify_handler();
1862 run_once++;
1863 }
1864 break;
1865
1866 case CPU_R6000:
1867 case CPU_R6000A:
1868 panic("No R6000 TLB refill handler yet");
1869 break;
1870
1871 case CPU_R8000:
1872 panic("No R8000 TLB refill handler yet");
1873 break;
1874
1875 default:
1876 build_r4000_tlb_refill_handler();
1877 if (!run_once) {
1878 build_r4000_tlb_load_handler();
1879 build_r4000_tlb_store_handler();
1880 build_r4000_tlb_modify_handler();
1881 run_once++;
1882 }
1883 }
1884}
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001885
1886void __init flush_tlb_handlers(void)
1887{
1888 flush_icache_range((unsigned long)handle_tlbl,
1889 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
1890 flush_icache_range((unsigned long)handle_tlbs,
1891 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
1892 flush_icache_range((unsigned long)handle_tlbm,
1893 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
1894}